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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -run-pass=si-lower-sgpr-spills -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s3 4# A simple SGPR spill. Implicit def for lane VGPR should be inserted just before the spill instruction.5---6name: sgpr32_spill7tracksRegLiveness: true8frameInfo:9 maxAlignment: 410stack:11 - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }12machineFunctionInfo:13 isEntryFunction: false14 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'15 stackPtrOffsetReg: '$sgpr32'16 frameOffsetReg: '$sgpr33'17 hasSpilledSGPRs: true18body: |19 bb.0:20 liveins: $sgpr30_sgpr31, $sgpr1021 ; GCN-LABEL: name: sgpr32_spill22 ; GCN: liveins: $sgpr30_sgpr31, $sgpr1023 ; GCN-NEXT: {{ $}}24 ; GCN-NEXT: S_NOP 025 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF26 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]27 ; GCN-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 028 ; GCN-NEXT: S_SETPC_B64 $sgpr30_sgpr3129 S_NOP 030 SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr3231 renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr3232 S_SETPC_B64 $sgpr30_sgpr3133...34 35# Needed an additional virtual lane register as the lanes of current register are fully occupied while spilling a wide SGPR tuple.36# There must be two implicit def for the two lane VGPRs.37 38---39name: sgpr_spill_lane_crossover40tracksRegLiveness: true41frameInfo:42 maxAlignment: 443stack:44 - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }45 - { id: 1, type: spill-slot, size: 128, alignment: 4, stack-id: sgpr-spill }46machineFunctionInfo:47 isEntryFunction: false48 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'49 stackPtrOffsetReg: '$sgpr32'50 frameOffsetReg: '$sgpr33'51 hasSpilledSGPRs: true52body: |53 bb.0:54 liveins: $sgpr30_sgpr31, $sgpr10, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr9555 ; GCN-LABEL: name: sgpr_spill_lane_crossover56 ; GCN: liveins: $sgpr10, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $vgpr63, $sgpr30_sgpr31, $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71, $sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79, $sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87, $sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr9557 ; GCN-NEXT: {{ $}}58 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, $vgpr6359 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr6360 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr6361 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr67, 3, $vgpr6362 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr68, 4, $vgpr6363 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr69, 5, $vgpr6364 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr70, 6, $vgpr6365 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr71, 7, $vgpr6366 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr80, 8, $vgpr6367 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr81, 9, $vgpr6368 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr82, 10, $vgpr6369 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr83, 11, $vgpr6370 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr84, 12, $vgpr6371 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr85, 13, $vgpr6372 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr86, 14, $vgpr6373 ; GCN-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr87, 15, $vgpr6374 ; GCN-NEXT: S_NOP 075 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF76 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]77 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr64, 1, [[DEF]], implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr9578 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr65, 2, [[DEF]]79 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr66, 3, [[DEF]]80 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr67, 4, [[DEF]]81 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr68, 5, [[DEF]]82 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr69, 6, [[DEF]]83 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr70, 7, [[DEF]]84 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr71, 8, [[DEF]]85 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr72, 9, [[DEF]]86 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr73, 10, [[DEF]]87 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr74, 11, [[DEF]]88 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr75, 12, [[DEF]]89 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr76, 13, [[DEF]]90 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr77, 14, [[DEF]]91 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr78, 15, [[DEF]]92 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr79, 16, [[DEF]]93 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr80, 17, [[DEF]]94 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr81, 18, [[DEF]]95 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr82, 19, [[DEF]]96 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr83, 20, [[DEF]]97 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr84, 21, [[DEF]]98 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr85, 22, [[DEF]]99 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr86, 23, [[DEF]]100 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr87, 24, [[DEF]]101 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr88, 25, [[DEF]]102 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr89, 26, [[DEF]]103 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr90, 27, [[DEF]]104 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr91, 28, [[DEF]]105 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr92, 29, [[DEF]]106 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr93, 30, [[DEF]]107 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr94, 31, [[DEF]]108 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr95, 32, [[DEF]], implicit killed $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95109 ; GCN-NEXT: S_NOP 0110 ; GCN-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95111 ; GCN-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 2112 ; GCN-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 3113 ; GCN-NEXT: $sgpr67 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4114 ; GCN-NEXT: $sgpr68 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 5115 ; GCN-NEXT: $sgpr69 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 6116 ; GCN-NEXT: $sgpr70 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 7117 ; GCN-NEXT: $sgpr71 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 8118 ; GCN-NEXT: $sgpr72 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 9119 ; GCN-NEXT: $sgpr73 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 10120 ; GCN-NEXT: $sgpr74 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 11121 ; GCN-NEXT: $sgpr75 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 12122 ; GCN-NEXT: $sgpr76 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 13123 ; GCN-NEXT: $sgpr77 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 14124 ; GCN-NEXT: $sgpr78 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 15125 ; GCN-NEXT: $sgpr79 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 16126 ; GCN-NEXT: $sgpr80 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 17127 ; GCN-NEXT: $sgpr81 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 18128 ; GCN-NEXT: $sgpr82 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 19129 ; GCN-NEXT: $sgpr83 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 20130 ; GCN-NEXT: $sgpr84 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 21131 ; GCN-NEXT: $sgpr85 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 22132 ; GCN-NEXT: $sgpr86 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 23133 ; GCN-NEXT: $sgpr87 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 24134 ; GCN-NEXT: $sgpr88 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 25135 ; GCN-NEXT: $sgpr89 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 26136 ; GCN-NEXT: $sgpr90 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 27137 ; GCN-NEXT: $sgpr91 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 28138 ; GCN-NEXT: $sgpr92 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 29139 ; GCN-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 30140 ; GCN-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 31141 ; GCN-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 32142 ; GCN-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0143 ; GCN-NEXT: S_SETPC_B64 $sgpr30_sgpr31144 S_NOP 0145 SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32146 SI_SPILL_S1024_SAVE killed $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32147 S_NOP 0148 renamable $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 = SI_SPILL_S1024_RESTORE %stack.1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32149 renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32150 S_SETPC_B64 $sgpr30_sgpr31151...152 153# The implicit def for the lane VGPR should be inserted at the common dominator block (the entry block here).154 155---156name: lane_vgpr_implicit_def_at_common_dominator_block157tracksRegLiveness: true158frameInfo:159 maxAlignment: 4160stack:161 - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }162machineFunctionInfo:163 isEntryFunction: false164 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'165 stackPtrOffsetReg: '$sgpr32'166 frameOffsetReg: '$sgpr33'167 hasSpilledSGPRs: true168body: |169 ; GCN-LABEL: name: lane_vgpr_implicit_def_at_common_dominator_block170 ; GCN: bb.0:171 ; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)172 ; GCN-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31173 ; GCN-NEXT: {{ $}}174 ; GCN-NEXT: S_NOP 0175 ; GCN-NEXT: S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc176 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF177 ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc178 ; GCN-NEXT: {{ $}}179 ; GCN-NEXT: bb.1:180 ; GCN-NEXT: successors: %bb.3(0x80000000)181 ; GCN-NEXT: liveins: $sgpr10, $sgpr30_sgpr31182 ; GCN-NEXT: {{ $}}183 ; GCN-NEXT: $sgpr10 = S_MOV_B32 10184 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]185 ; GCN-NEXT: S_BRANCH %bb.3186 ; GCN-NEXT: {{ $}}187 ; GCN-NEXT: bb.2:188 ; GCN-NEXT: successors: %bb.3(0x80000000)189 ; GCN-NEXT: liveins: $sgpr10, $sgpr30_sgpr31190 ; GCN-NEXT: {{ $}}191 ; GCN-NEXT: $sgpr10 = S_MOV_B32 20192 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]193 ; GCN-NEXT: S_BRANCH %bb.3194 ; GCN-NEXT: {{ $}}195 ; GCN-NEXT: bb.3:196 ; GCN-NEXT: liveins: $sgpr10, $sgpr30_sgpr31197 ; GCN-NEXT: {{ $}}198 ; GCN-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0199 ; GCN-NEXT: S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10200 bb.0:201 liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31202 S_NOP 0203 S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc204 S_CBRANCH_SCC1 %bb.2, implicit killed $scc205 bb.1:206 liveins: $sgpr10, $sgpr30_sgpr31207 $sgpr10 = S_MOV_B32 10208 SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32209 S_BRANCH %bb.3210 bb.2:211 liveins: $sgpr10, $sgpr30_sgpr31212 $sgpr10 = S_MOV_B32 20213 SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32214 S_BRANCH %bb.3215 bb.3:216 liveins: $sgpr10, $sgpr30_sgpr31217 renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32218 S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10219...220 221# The common dominator block is visited only at the end. The insertion point was initially identified to the222# terminator instruction in the dominator block which later becomes the point where a spill get inserted in the same block.223 224---225name: dominator_block_follows_the_successors_bbs226tracksRegLiveness: true227frameInfo:228 maxAlignment: 4229stack:230 - { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }231machineFunctionInfo:232 isEntryFunction: false233 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'234 stackPtrOffsetReg: '$sgpr32'235 frameOffsetReg: '$sgpr33'236 hasSpilledSGPRs: true237body: |238 ; GCN-LABEL: name: dominator_block_follows_the_successors_bbs239 ; GCN: bb.0:240 ; GCN-NEXT: successors: %bb.3(0x80000000)241 ; GCN-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31242 ; GCN-NEXT: {{ $}}243 ; GCN-NEXT: S_NOP 0244 ; GCN-NEXT: S_BRANCH %bb.3245 ; GCN-NEXT: {{ $}}246 ; GCN-NEXT: bb.1:247 ; GCN-NEXT: successors: %bb.2(0x80000000)248 ; GCN-NEXT: liveins: $sgpr10, $sgpr30_sgpr31249 ; GCN-NEXT: {{ $}}250 ; GCN-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR %0, 0251 ; GCN-NEXT: $sgpr10 = S_ADD_I32 $sgpr10, 15, implicit-def dead $scc252 ; GCN-NEXT: S_BRANCH %bb.2253 ; GCN-NEXT: {{ $}}254 ; GCN-NEXT: bb.2:255 ; GCN-NEXT: successors: %bb.3(0x80000000)256 ; GCN-NEXT: liveins: $sgpr10, $sgpr30_sgpr31257 ; GCN-NEXT: {{ $}}258 ; GCN-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR %0, 0259 ; GCN-NEXT: $sgpr10 = S_ADD_I32 $sgpr10, 20, implicit-def dead $scc260 ; GCN-NEXT: S_BRANCH %bb.3261 ; GCN-NEXT: {{ $}}262 ; GCN-NEXT: bb.3:263 ; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)264 ; GCN-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31265 ; GCN-NEXT: {{ $}}266 ; GCN-NEXT: $sgpr10 = S_MOV_B32 10267 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF268 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]269 ; GCN-NEXT: S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc270 ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc271 ; GCN-NEXT: S_BRANCH %bb.1272 ; GCN-NEXT: {{ $}}273 ; GCN-NEXT: bb.4:274 ; GCN-NEXT: liveins: $sgpr10, $sgpr30_sgpr31275 ; GCN-NEXT: {{ $}}276 ; GCN-NEXT: S_NOP 0277 ; GCN-NEXT: S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10278 bb.0:279 liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31280 S_NOP 0281 S_BRANCH %bb.3282 bb.1:283 liveins: $sgpr10, $sgpr30_sgpr31284 renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32285 $sgpr10 = S_ADD_I32 $sgpr10, 15, implicit-def dead $scc286 S_BRANCH %bb.2287 bb.2:288 liveins: $sgpr10, $sgpr30_sgpr31289 renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32290 $sgpr10 = S_ADD_I32 $sgpr10, 20, implicit-def dead $scc291 S_BRANCH %bb.3292 bb.3:293 liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31294 $sgpr10 = S_MOV_B32 10295 SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32296 S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc297 S_CBRANCH_SCC1 %bb.2, implicit killed $scc298 S_BRANCH %bb.1299 bb.4:300 liveins: $sgpr10, $sgpr30_sgpr31301 S_NOP 0302 S_SETPC_B64 $sgpr30_sgpr31, implicit $sgpr10303...304