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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -o - %s | FileCheck %s3 4; Regression test for `processFunctionBeforeFrameFinalized`:5; Check that it correctly updates RegisterScavenger so we6; don't end up with bad machine code due to using undefined7; physical registers.8 9define void @test() {10; CHECK-LABEL: test:11; CHECK: ; %bb.0: ; %bb.012; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -114; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; 4-byte Folded Spill15; CHECK-NEXT: s_mov_b64 exec, s[4:5]16; CHECK-NEXT: .LBB0_1: ; %bb.117; CHECK-NEXT: ; =>This Inner Loop Header: Depth=118; CHECK-NEXT: s_cbranch_scc1 .LBB0_319; CHECK-NEXT: ; %bb.2: ; %bb.220; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=121; CHECK-NEXT: .LBB0_3: ; %bb.322; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=123; CHECK-NEXT: ; implicit-def: $sgpr424; CHECK-NEXT: v_mov_b32_e32 v0, s425; CHECK-NEXT: v_readfirstlane_b32 s6, v026; CHECK-NEXT: s_mov_b64 s[4:5], -127; CHECK-NEXT: s_mov_b32 s7, 028; CHECK-NEXT: s_cmp_eq_u32 s6, s729; CHECK-NEXT: ; implicit-def: $vgpr1 : SGPR spill to VGPR lane30; CHECK-NEXT: v_writelane_b32 v1, s4, 031; CHECK-NEXT: v_writelane_b32 v1, s5, 132; CHECK-NEXT: s_mov_b64 s[10:11], exec33; CHECK-NEXT: s_mov_b64 exec, -134; CHECK-NEXT: v_accvgpr_write_b32 a0, v1 ; Reload Reuse35; CHECK-NEXT: s_mov_b64 exec, s[10:11]36; CHECK-NEXT: s_cbranch_scc1 .LBB0_537; CHECK-NEXT: ; %bb.4: ; %bb.438; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=139; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -140; CHECK-NEXT: v_accvgpr_read_b32 v1, a0 ; Reload Reuse41; CHECK-NEXT: s_mov_b64 exec, s[10:11]42; CHECK-NEXT: s_mov_b64 s[4:5], 043; CHECK-NEXT: v_writelane_b32 v1, s4, 044; CHECK-NEXT: v_writelane_b32 v1, s5, 145; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -146; CHECK-NEXT: s_nop 047; CHECK-NEXT: v_accvgpr_write_b32 a0, v1 ; Reload Reuse48; CHECK-NEXT: s_mov_b64 exec, s[10:11]49; CHECK-NEXT: .LBB0_5: ; %Flow50; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=151; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -152; CHECK-NEXT: s_nop 053; CHECK-NEXT: v_accvgpr_read_b32 v1, a0 ; Reload Reuse54; CHECK-NEXT: s_mov_b64 exec, s[10:11]55; CHECK-NEXT: v_readlane_b32 s4, v1, 056; CHECK-NEXT: v_readlane_b32 s5, v1, 157; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]58; CHECK-NEXT: s_mov_b32 s4, 159; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, s460; CHECK-NEXT: s_and_b64 vcc, exec, s[4:5]61; CHECK-NEXT: s_cbranch_vccnz .LBB0_162; CHECK-NEXT: ; %bb.6: ; %bb.563; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -164; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 ; 4-byte Folded Reload65; CHECK-NEXT: s_mov_b64 exec, s[4:5]66; CHECK-NEXT: s_waitcnt vmcnt(0)67; CHECK-NEXT: s_setpc_b64 s[30:31]68bb.0:69 br label %bb.170bb.1: ; preds = %bb.4, %bb.071 br i1 poison, label %bb.2, label %bb.372bb.2: ; preds = %bb.173 br label %bb.374bb.3: ; preds = %bb.2, %bb.175 %call = tail call i32 @llvm.amdgcn.readfirstlane(i32 poison)76 %cmp = icmp eq i32 %call, 077 br i1 %cmp, label %bb.5, label %bb.478bb.4: ; preds = %bb.379 br label %bb.180bb.5: ; preds = %bb.381 ret void82}83 84declare i32 @llvm.amdgcn.readfirstlane(i32)85