303 lines · plain
1; RUN: llc -O0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN -check-prefix=VGPR %s2; RUN: llc -O0 -mtriple=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VMEM %s3 4; GCN-LABEL: {{^}}spill_sgpr_x2:5 6; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 07; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 18; VGPR: s_cbranch_scc19 10; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 011; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 112 13 14; VMEM: buffer_store_dword15; VMEM: s_cbranch_scc116 17; VMEM: buffer_load_dword18define amdgpu_kernel void @spill_sgpr_x2(ptr addrspace(1) %out, i32 %in) #0 {19 %wide.sgpr = call <2 x i32> asm sideeffect "; def $0", "=s" () #020 %cmp = icmp eq i32 %in, 021 br i1 %cmp, label %bb0, label %ret22 23bb0:24 call void asm sideeffect "; use $0", "s"(<2 x i32> %wide.sgpr) #025 br label %ret26 27ret:28 ret void29}30 31; GCN-LABEL: {{^}}spill_sgpr_x3:32 33; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 034; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 135; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 236; VGPR: s_cbranch_scc137 38; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 039; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 140; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 241 42 43; VMEM: buffer_store_dword44; VMEM: s_cbranch_scc145 46; VMEM: buffer_load_dword47define amdgpu_kernel void @spill_sgpr_x3(ptr addrspace(1) %out, i32 %in) #0 {48 %wide.sgpr = call <3 x i32> asm sideeffect "; def $0", "=s" () #049 %cmp = icmp eq i32 %in, 050 br i1 %cmp, label %bb0, label %ret51 52bb0:53 call void asm sideeffect "; use $0", "s"(<3 x i32> %wide.sgpr) #054 br label %ret55 56ret:57 ret void58}59 60; GCN-LABEL: {{^}}spill_sgpr_x4:61 62; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 063; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 164; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 265; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 366; VGPR: s_cbranch_scc167 68; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 069; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 170; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 271; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 372 73 74; VMEM: buffer_store_dword75; VMEM: s_cbranch_scc176 77; VMEM: buffer_load_dword78define amdgpu_kernel void @spill_sgpr_x4(ptr addrspace(1) %out, i32 %in) #0 {79 %wide.sgpr = call <4 x i32> asm sideeffect "; def $0", "=s" () #080 %cmp = icmp eq i32 %in, 081 br i1 %cmp, label %bb0, label %ret82 83bb0:84 call void asm sideeffect "; use $0", "s"(<4 x i32> %wide.sgpr) #085 br label %ret86 87ret:88 ret void89}90 91; GCN-LABEL: {{^}}spill_sgpr_x5:92 93; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 094; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 195; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 296; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 397; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 498; VGPR: s_cbranch_scc199 100; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0101; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1102; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2103; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3104; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4105 106 107; VMEM: buffer_store_dword108; VMEM: s_cbranch_scc1109 110; VMEM: buffer_load_dword111define amdgpu_kernel void @spill_sgpr_x5(ptr addrspace(1) %out, i32 %in) #0 {112 %wide.sgpr = call <5 x i32> asm sideeffect "; def $0", "=s" () #0113 %cmp = icmp eq i32 %in, 0114 br i1 %cmp, label %bb0, label %ret115 116bb0:117 call void asm sideeffect "; use $0", "s"(<5 x i32> %wide.sgpr) #0118 br label %ret119 120ret:121 ret void122}123 124; GCN-LABEL: {{^}}spill_sgpr_x8:125 126; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0127; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1128; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2129; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3130; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4131; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5132; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6133; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7134; VGPR: s_cbranch_scc1135 136; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0137; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1138; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2139; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3140; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4141; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5142; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6143; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7144 145; VMEM: buffer_store_dword146; VMEM: s_cbranch_scc1147 148; VMEM: buffer_load_dword149define amdgpu_kernel void @spill_sgpr_x8(ptr addrspace(1) %out, i32 %in) #0 {150 %wide.sgpr = call <8 x i32> asm sideeffect "; def $0", "=s" () #0151 %cmp = icmp eq i32 %in, 0152 br i1 %cmp, label %bb0, label %ret153 154bb0:155 call void asm sideeffect "; use $0", "s"(<8 x i32> %wide.sgpr) #0156 br label %ret157 158ret:159 ret void160}161 162; GCN-LABEL: {{^}}spill_sgpr_x16:163 164; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0165; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1166; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2167; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3168; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4169; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5170; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6171; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7172; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 8173; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 9174; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 10175; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 11176; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 12177; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 13178; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 14179; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 15180; VGPR: s_cbranch_scc1181 182; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0183; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1184; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2185; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3186; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4187; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5188; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6189; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7190; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 8191; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 9192; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 10193; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 11194; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 12195; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 13196; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 14197; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 15198 199; VMEM: buffer_store_dword200; VMEM: s_cbranch_scc1201 202; VMEM: buffer_load_dword203define amdgpu_kernel void @spill_sgpr_x16(ptr addrspace(1) %out, i32 %in) #0 {204 %wide.sgpr = call <16 x i32> asm sideeffect "; def $0", "=s" () #0205 %cmp = icmp eq i32 %in, 0206 br i1 %cmp, label %bb0, label %ret207 208bb0:209 call void asm sideeffect "; use $0", "s"(<16 x i32> %wide.sgpr) #0210 br label %ret211 212ret:213 ret void214}215 216; GCN-LABEL: {{^}}spill_sgpr_x32:217 218; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0219; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1220; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2221; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3222; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 4223; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 5224; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 6225; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 7226; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 8227; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 9228; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 10229; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 11230; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 12231; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 13232; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 14233; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 15234; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 16235; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 17236; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 18237; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 19238; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 20239; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 21240; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 22241; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 23242; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 24243; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 25244; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 26245; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 27246; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 28247; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 29248; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 30249; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 31250; VGPR: s_cbranch_scc1251 252; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0253; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1254; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2255; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3256; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 4257; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 5258; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 6259; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 7260; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 8261; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 9262; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 10263; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 11264; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 12265; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 13266; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 14267; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 15268; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 16269; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 17270; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 18271; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 19272; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 20273; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 21274; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 22275; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 23276; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 24277; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 25278; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 26279; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 27280; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 28281; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 29282; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 30283; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 31284 285; VMEM: buffer_store_dword286; VMEM: s_cbranch_scc1287 288; VMEM: buffer_load_dword289define amdgpu_kernel void @spill_sgpr_x32(ptr addrspace(1) %out, i32 %in) #0 {290 %wide.sgpr = call <32 x i32> asm sideeffect "; def $0", "=s" () #0291 %cmp = icmp eq i32 %in, 0292 br i1 %cmp, label %bb0, label %ret293 294bb0:295 call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr) #0296 br label %ret297 298ret:299 ret void300}301 302attributes #0 = { nounwind }303