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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -o - %s | FileCheck -check-prefix=GCN %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -o - %s | FileCheck -check-prefix=GCN %s4 5; Callee must preserve the VGPR modified by writelane even if it is marked Caller-saved.6 7declare i32 @llvm.amdgcn.writelane(i32, i32, i32)8 9define void @sgpr_spill_writelane() {10; GCN-LABEL: sgpr_spill_writelane:11; GCN: ; %bb.0:12; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -114; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill15; GCN-NEXT: s_mov_b64 exec, s[4:5]16; GCN-NEXT: v_writelane_b32 v0, s35, 017; GCN-NEXT: ;;#ASMSTART18; GCN-NEXT: ;;#ASMEND19; GCN-NEXT: v_readlane_b32 s35, v0, 020; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -121; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload22; GCN-NEXT: s_mov_b64 exec, s[4:5]23; GCN-NEXT: s_waitcnt vmcnt(0)24; GCN-NEXT: s_setpc_b64 s[30:31]25 call void asm sideeffect "", "~{s35}"()26 ret void27}28 29define void @device_writelane_intrinsic(ptr addrspace(1) %out, i32 %src) {30; GCN-LABEL: device_writelane_intrinsic:31; GCN: ; %bb.0:32; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GCN-NEXT: v_mov_b32_e32 v3, 1534; GCN-NEXT: v_readfirstlane_b32 s4, v235; GCN-NEXT: v_writelane_b32 v3, s4, 2336; GCN-NEXT: global_store_dword v[0:1], v3, off37; GCN-NEXT: s_waitcnt vmcnt(0)38; GCN-NEXT: s_setpc_b64 s[30:31]39 %writelane = call i32 @llvm.amdgcn.writelane(i32 %src, i32 23, i32 15)40 store i32 %writelane, ptr addrspace(1) %out, align 441 ret void42}43 44define amdgpu_kernel void @kernel_writelane_intrinsic(ptr addrspace(1) %out, i32 %src0, i32 %src1) {45; GCN-LABEL: kernel_writelane_intrinsic:46; GCN: ; %bb.0:47; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x048; GCN-NEXT: v_mov_b32_e32 v1, 4549; GCN-NEXT: v_mov_b32_e32 v0, 050; GCN-NEXT: s_waitcnt lgkmcnt(0)51; GCN-NEXT: s_mov_b32 m0, s352; GCN-NEXT: v_writelane_b32 v1, s2, m053; GCN-NEXT: global_store_dword v0, v1, s[0:1]54; GCN-NEXT: s_endpgm55 %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 45)56 store i32 %writelane, ptr addrspace(1) %out, align 457 ret void58}59