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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s3# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s4# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s5 6# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s7 8# Make sure spill/restore of 192 bit registers works. We have to9# settle for a MIR test for now since inlineasm fails without 192-bit10# MVT.11 12---13name: spill_restore_sgpr19214tracksRegLiveness: true15machineFunctionInfo:16 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr317 stackPtrOffsetReg: $sgpr3218body: |19 ; SPILLED-LABEL: name: spill_restore_sgpr19220 ; SPILLED: bb.0:21 ; SPILLED-NEXT: successors: %bb.1(0x80000000)22 ; SPILLED-NEXT: {{ $}}23 ; SPILLED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr924 ; SPILLED-NEXT: SI_SPILL_S192_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s192) into %stack.0, align 4, addrspace 5)25 ; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc26 ; SPILLED-NEXT: {{ $}}27 ; SPILLED-NEXT: bb.1:28 ; SPILLED-NEXT: successors: %bb.2(0x80000000)29 ; SPILLED-NEXT: {{ $}}30 ; SPILLED-NEXT: S_NOP 131 ; SPILLED-NEXT: {{ $}}32 ; SPILLED-NEXT: bb.2:33 ; SPILLED-NEXT: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 = SI_SPILL_S192_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s192) from %stack.0, align 4, addrspace 5)34 ; SPILLED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr935 ;36 ; EXPANDED-LABEL: name: spill_restore_sgpr19237 ; EXPANDED: bb.0:38 ; EXPANDED-NEXT: successors: %bb.1(0x80000000)39 ; EXPANDED-NEXT: {{ $}}40 ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr941 ; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF42 ; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, [[DEF]], implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr943 ; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, [[DEF]]44 ; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr6, 2, [[DEF]]45 ; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr7, 3, [[DEF]]46 ; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr8, 4, [[DEF]]47 ; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr9, 5, [[DEF]], implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr948 ; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc49 ; EXPANDED-NEXT: {{ $}}50 ; EXPANDED-NEXT: bb.1:51 ; EXPANDED-NEXT: successors: %bb.2(0x80000000)52 ; EXPANDED-NEXT: {{ $}}53 ; EXPANDED-NEXT: S_NOP 154 ; EXPANDED-NEXT: {{ $}}55 ; EXPANDED-NEXT: bb.2:56 ; EXPANDED-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr957 ; EXPANDED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 158 ; EXPANDED-NEXT: $sgpr6 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 259 ; EXPANDED-NEXT: $sgpr7 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 360 ; EXPANDED-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 461 ; EXPANDED-NEXT: $sgpr9 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 562 ; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr963 bb.0:64 S_NOP 0, implicit-def %0:sgpr_19265 S_CBRANCH_SCC1 implicit undef $scc, %bb.166 67 bb.1:68 S_NOP 169 70 bb.2:71 S_NOP 0, implicit %072...73 74---75name: spill_restore_vgpr19276tracksRegLiveness: true77machineFunctionInfo:78 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr379 stackPtrOffsetReg: $sgpr3280body: |81 ; SPILLED-LABEL: name: spill_restore_vgpr19282 ; SPILLED: bb.0:83 ; SPILLED-NEXT: successors: %bb.1(0x80000000)84 ; SPILLED-NEXT: {{ $}}85 ; SPILLED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr586 ; SPILLED-NEXT: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %stack.0, align 4, addrspace 5)87 ; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc88 ; SPILLED-NEXT: {{ $}}89 ; SPILLED-NEXT: bb.1:90 ; SPILLED-NEXT: successors: %bb.2(0x80000000)91 ; SPILLED-NEXT: {{ $}}92 ; SPILLED-NEXT: S_NOP 193 ; SPILLED-NEXT: {{ $}}94 ; SPILLED-NEXT: bb.2:95 ; SPILLED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s192) from %stack.0, align 4, addrspace 5)96 ; SPILLED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr597 ;98 ; EXPANDED-LABEL: name: spill_restore_vgpr19299 ; EXPANDED: bb.0:100 ; EXPANDED-NEXT: successors: %bb.1(0x80000000)101 ; EXPANDED-NEXT: {{ $}}102 ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5103 ; EXPANDED-NEXT: SI_SPILL_V192_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %stack.0, align 4, addrspace 5)104 ; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc105 ; EXPANDED-NEXT: {{ $}}106 ; EXPANDED-NEXT: bb.1:107 ; EXPANDED-NEXT: successors: %bb.2(0x80000000)108 ; EXPANDED-NEXT: {{ $}}109 ; EXPANDED-NEXT: S_NOP 1110 ; EXPANDED-NEXT: {{ $}}111 ; EXPANDED-NEXT: bb.2:112 ; EXPANDED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s192) from %stack.0, align 4, addrspace 5)113 ; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5114 bb.0:115 S_NOP 0, implicit-def %0:vreg_192116 S_CBRANCH_SCC1 implicit undef $scc, %bb.1117 118 bb.1:119 S_NOP 1120 121 bb.2:122 S_NOP 0, implicit %0123...124