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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=verde < %s | FileCheck %s -check-prefixes=SI3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s -check-prefixes=VI4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600-- -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG5 6declare i32 @llvm.amdgcn.workitem.id.x() #07 8define amdgpu_kernel void @ashr_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {9; SI-LABEL: ashr_v2i32:10; SI: ; %bb.0:11; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x912; SI-NEXT: s_mov_b32 s7, 0xf00013; SI-NEXT: s_mov_b32 s6, -114; SI-NEXT: s_mov_b32 s10, s615; SI-NEXT: s_mov_b32 s11, s716; SI-NEXT: s_waitcnt lgkmcnt(0)17; SI-NEXT: s_mov_b32 s8, s218; SI-NEXT: s_mov_b32 s9, s319; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 020; SI-NEXT: s_mov_b32 s4, s021; SI-NEXT: s_mov_b32 s5, s122; SI-NEXT: s_waitcnt vmcnt(0)23; SI-NEXT: v_ashr_i32_e32 v1, v1, v324; SI-NEXT: v_ashr_i32_e32 v0, v0, v225; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 026; SI-NEXT: s_endpgm27;28; VI-LABEL: ashr_v2i32:29; VI: ; %bb.0:30; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2431; VI-NEXT: s_mov_b32 s7, 0xf00032; VI-NEXT: s_mov_b32 s6, -133; VI-NEXT: s_mov_b32 s10, s634; VI-NEXT: s_mov_b32 s11, s735; VI-NEXT: s_waitcnt lgkmcnt(0)36; VI-NEXT: s_mov_b32 s8, s237; VI-NEXT: s_mov_b32 s9, s338; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 039; VI-NEXT: s_mov_b32 s4, s040; VI-NEXT: s_mov_b32 s5, s141; VI-NEXT: s_waitcnt vmcnt(0)42; VI-NEXT: v_ashrrev_i32_e32 v1, v3, v143; VI-NEXT: v_ashrrev_i32_e32 v0, v2, v044; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 045; VI-NEXT: s_endpgm46;47; EG-LABEL: ashr_v2i32:48; EG: ; %bb.0:49; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]50; EG-NEXT: TEX 0 @651; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]52; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 153; EG-NEXT: CF_END54; EG-NEXT: PAD55; EG-NEXT: Fetch clause starting at 6:56; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #157; EG-NEXT: ALU clause starting at 8:58; EG-NEXT: MOV * T0.X, KC0[2].Z,59; EG-NEXT: ALU clause starting at 9:60; EG-NEXT: ASHR * T0.Y, T0.Y, T0.W,61; EG-NEXT: ASHR T0.X, T0.X, T0.Z,62; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,63; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)64 %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 165 %a = load <2 x i32>, ptr addrspace(1) %in66 %b = load <2 x i32>, ptr addrspace(1) %b_ptr67 %result = ashr <2 x i32> %a, %b68 store <2 x i32> %result, ptr addrspace(1) %out69 ret void70}71 72define amdgpu_kernel void @ashr_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {73; SI-LABEL: ashr_v4i32:74; SI: ; %bb.0:75; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x976; SI-NEXT: s_mov_b32 s7, 0xf00077; SI-NEXT: s_mov_b32 s6, -178; SI-NEXT: s_mov_b32 s10, s679; SI-NEXT: s_mov_b32 s11, s780; SI-NEXT: s_waitcnt lgkmcnt(0)81; SI-NEXT: s_mov_b32 s8, s282; SI-NEXT: s_mov_b32 s9, s383; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 084; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:1685; SI-NEXT: s_mov_b32 s4, s086; SI-NEXT: s_mov_b32 s5, s187; SI-NEXT: s_waitcnt vmcnt(0)88; SI-NEXT: v_ashr_i32_e32 v3, v3, v789; SI-NEXT: v_ashr_i32_e32 v2, v2, v690; SI-NEXT: v_ashr_i32_e32 v1, v1, v591; SI-NEXT: v_ashr_i32_e32 v0, v0, v492; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 093; SI-NEXT: s_endpgm94;95; VI-LABEL: ashr_v4i32:96; VI: ; %bb.0:97; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2498; VI-NEXT: s_mov_b32 s7, 0xf00099; VI-NEXT: s_mov_b32 s6, -1100; VI-NEXT: s_mov_b32 s10, s6101; VI-NEXT: s_mov_b32 s11, s7102; VI-NEXT: s_waitcnt lgkmcnt(0)103; VI-NEXT: s_mov_b32 s8, s2104; VI-NEXT: s_mov_b32 s9, s3105; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0106; VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16107; VI-NEXT: s_mov_b32 s4, s0108; VI-NEXT: s_mov_b32 s5, s1109; VI-NEXT: s_waitcnt vmcnt(0)110; VI-NEXT: v_ashrrev_i32_e32 v3, v7, v3111; VI-NEXT: v_ashrrev_i32_e32 v2, v6, v2112; VI-NEXT: v_ashrrev_i32_e32 v1, v5, v1113; VI-NEXT: v_ashrrev_i32_e32 v0, v4, v0114; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0115; VI-NEXT: s_endpgm116;117; EG-LABEL: ashr_v4i32:118; EG: ; %bb.0:119; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]120; EG-NEXT: TEX 1 @6121; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]122; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1123; EG-NEXT: CF_END124; EG-NEXT: PAD125; EG-NEXT: Fetch clause starting at 6:126; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1127; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1128; EG-NEXT: ALU clause starting at 10:129; EG-NEXT: MOV * T0.X, KC0[2].Z,130; EG-NEXT: ALU clause starting at 11:131; EG-NEXT: ASHR * T0.W, T0.W, T1.W,132; EG-NEXT: ASHR * T0.Z, T0.Z, T1.Z,133; EG-NEXT: ASHR * T0.Y, T0.Y, T1.Y,134; EG-NEXT: ASHR T0.X, T0.X, T1.X,135; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,136; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)137 %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1138 %a = load <4 x i32>, ptr addrspace(1) %in139 %b = load <4 x i32>, ptr addrspace(1) %b_ptr140 %result = ashr <4 x i32> %a, %b141 store <4 x i32> %result, ptr addrspace(1) %out142 ret void143}144 145; FIXME: The ashr operation is uniform, but because its operands come from a146; global load we end up with the vector instructions rather than scalar.147define amdgpu_kernel void @ashr_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {148; SI-LABEL: ashr_v2i16:149; SI: ; %bb.0:150; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9151; SI-NEXT: s_mov_b32 s7, 0xf000152; SI-NEXT: s_mov_b32 s6, -1153; SI-NEXT: s_mov_b32 s10, s6154; SI-NEXT: s_mov_b32 s11, s7155; SI-NEXT: s_waitcnt lgkmcnt(0)156; SI-NEXT: s_mov_b32 s8, s2157; SI-NEXT: s_mov_b32 s9, s3158; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0159; SI-NEXT: s_mov_b32 s4, s0160; SI-NEXT: s_mov_b32 s5, s1161; SI-NEXT: s_waitcnt vmcnt(0)162; SI-NEXT: v_readfirstlane_b32 s0, v0163; SI-NEXT: v_readfirstlane_b32 s1, v1164; SI-NEXT: s_sext_i32_i16 s2, s0165; SI-NEXT: s_ashr_i32 s0, s0, 16166; SI-NEXT: s_lshr_b32 s3, s1, 16167; SI-NEXT: s_ashr_i32 s0, s0, s3168; SI-NEXT: s_ashr_i32 s1, s2, s1169; SI-NEXT: s_lshl_b32 s0, s0, 16170; SI-NEXT: s_and_b32 s1, s1, 0xffff171; SI-NEXT: s_or_b32 s0, s1, s0172; SI-NEXT: v_mov_b32_e32 v0, s0173; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0174; SI-NEXT: s_endpgm175;176; VI-LABEL: ashr_v2i16:177; VI: ; %bb.0:178; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24179; VI-NEXT: s_mov_b32 s7, 0xf000180; VI-NEXT: s_mov_b32 s6, -1181; VI-NEXT: s_mov_b32 s10, s6182; VI-NEXT: s_mov_b32 s11, s7183; VI-NEXT: s_waitcnt lgkmcnt(0)184; VI-NEXT: s_mov_b32 s8, s2185; VI-NEXT: s_mov_b32 s9, s3186; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0187; VI-NEXT: s_mov_b32 s4, s0188; VI-NEXT: s_mov_b32 s5, s1189; VI-NEXT: s_waitcnt vmcnt(0)190; VI-NEXT: v_readfirstlane_b32 s0, v0191; VI-NEXT: v_readfirstlane_b32 s1, v1192; VI-NEXT: s_lshr_b32 s2, s1, 16193; VI-NEXT: s_ashr_i32 s3, s0, 16194; VI-NEXT: s_sext_i32_i16 s0, s0195; VI-NEXT: s_ashr_i32 s2, s3, s2196; VI-NEXT: s_ashr_i32 s0, s0, s1197; VI-NEXT: s_lshl_b32 s1, s2, 16198; VI-NEXT: s_and_b32 s0, s0, 0xffff199; VI-NEXT: s_or_b32 s0, s0, s1200; VI-NEXT: v_mov_b32_e32 v0, s0201; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0202; VI-NEXT: s_endpgm203;204; EG-LABEL: ashr_v2i16:205; EG: ; %bb.0:206; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]207; EG-NEXT: TEX 0 @6208; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]209; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T7.X, 1210; EG-NEXT: CF_END211; EG-NEXT: PAD212; EG-NEXT: Fetch clause starting at 6:213; EG-NEXT: VTX_READ_64 T6.XY, T6.X, 0, #1214; EG-NEXT: ALU clause starting at 8:215; EG-NEXT: MOV * T6.X, KC0[2].Z,216; EG-NEXT: ALU clause starting at 9:217; EG-NEXT: LSHR * T0.W, T6.X, literal.x,218; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)219; EG-NEXT: BFE_INT T0.Y, PV.W, 0.0, literal.x,220; EG-NEXT: LSHR T0.Z, T6.Y, literal.x,221; EG-NEXT: BFE_INT T0.W, T6.X, 0.0, literal.x,222; EG-NEXT: AND_INT * T1.W, T6.Y, literal.y,223; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)224; EG-NEXT: ASHR T0.W, PV.W, PS,225; EG-NEXT: ASHR * T1.W, PV.Y, PV.Z,226; EG-NEXT: LSHL T1.W, PS, literal.x,227; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,228; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)229; EG-NEXT: OR_INT T6.X, PS, PV.W,230; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,231; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)232 %b_ptr = getelementptr <2 x i16>, ptr addrspace(1) %in, i16 1233 %a = load <2 x i16>, ptr addrspace(1) %in234 %b = load <2 x i16>, ptr addrspace(1) %b_ptr235 %result = ashr <2 x i16> %a, %b236 store <2 x i16> %result, ptr addrspace(1) %out237 ret void238}239 240; FIXME: The ashr operation is uniform, but because its operands come from a241; global load we end up with the vector instructions rather than scalar.242define amdgpu_kernel void @ashr_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {243; SI-LABEL: ashr_v4i16:244; SI: ; %bb.0:245; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9246; SI-NEXT: s_mov_b32 s7, 0xf000247; SI-NEXT: s_mov_b32 s6, -1248; SI-NEXT: s_mov_b32 s10, s6249; SI-NEXT: s_mov_b32 s11, s7250; SI-NEXT: s_waitcnt lgkmcnt(0)251; SI-NEXT: s_mov_b32 s8, s2252; SI-NEXT: s_mov_b32 s9, s3253; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0254; SI-NEXT: s_mov_b32 s4, s0255; SI-NEXT: s_mov_b32 s5, s1256; SI-NEXT: s_waitcnt vmcnt(0)257; SI-NEXT: v_readfirstlane_b32 s0, v3258; SI-NEXT: v_readfirstlane_b32 s1, v2259; SI-NEXT: v_readfirstlane_b32 s2, v1260; SI-NEXT: v_readfirstlane_b32 s3, v0261; SI-NEXT: s_sext_i32_i16 s8, s3262; SI-NEXT: s_ashr_i32 s3, s3, 16263; SI-NEXT: s_sext_i32_i16 s9, s2264; SI-NEXT: s_ashr_i32 s2, s2, 16265; SI-NEXT: s_lshr_b32 s10, s1, 16266; SI-NEXT: s_lshr_b32 s11, s0, 16267; SI-NEXT: s_ashr_i32 s2, s2, s11268; SI-NEXT: s_ashr_i32 s0, s9, s0269; SI-NEXT: s_ashr_i32 s3, s3, s10270; SI-NEXT: s_ashr_i32 s1, s8, s1271; SI-NEXT: s_lshl_b32 s2, s2, 16272; SI-NEXT: s_and_b32 s0, s0, 0xffff273; SI-NEXT: s_lshl_b32 s3, s3, 16274; SI-NEXT: s_and_b32 s1, s1, 0xffff275; SI-NEXT: s_or_b32 s0, s0, s2276; SI-NEXT: s_or_b32 s1, s1, s3277; SI-NEXT: v_mov_b32_e32 v0, s1278; SI-NEXT: v_mov_b32_e32 v1, s0279; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0280; SI-NEXT: s_endpgm281;282; VI-LABEL: ashr_v4i16:283; VI: ; %bb.0:284; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24285; VI-NEXT: s_mov_b32 s3, 0xf000286; VI-NEXT: s_mov_b32 s2, -1287; VI-NEXT: s_mov_b32 s10, s2288; VI-NEXT: s_mov_b32 s11, s3289; VI-NEXT: s_waitcnt lgkmcnt(0)290; VI-NEXT: s_mov_b32 s8, s6291; VI-NEXT: s_mov_b32 s9, s7292; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0293; VI-NEXT: s_mov_b32 s0, s4294; VI-NEXT: s_mov_b32 s1, s5295; VI-NEXT: s_waitcnt vmcnt(0)296; VI-NEXT: v_readfirstlane_b32 s4, v0297; VI-NEXT: v_readfirstlane_b32 s5, v2298; VI-NEXT: v_readfirstlane_b32 s6, v1299; VI-NEXT: v_readfirstlane_b32 s7, v3300; VI-NEXT: s_lshr_b32 s8, s7, 16301; VI-NEXT: s_ashr_i32 s9, s6, 16302; VI-NEXT: s_sext_i32_i16 s6, s6303; VI-NEXT: s_lshr_b32 s10, s5, 16304; VI-NEXT: s_ashr_i32 s11, s4, 16305; VI-NEXT: s_sext_i32_i16 s4, s4306; VI-NEXT: s_ashr_i32 s8, s9, s8307; VI-NEXT: s_ashr_i32 s6, s6, s7308; VI-NEXT: s_ashr_i32 s7, s11, s10309; VI-NEXT: s_ashr_i32 s4, s4, s5310; VI-NEXT: s_lshl_b32 s5, s8, 16311; VI-NEXT: s_and_b32 s6, s6, 0xffff312; VI-NEXT: s_lshl_b32 s7, s7, 16313; VI-NEXT: s_and_b32 s4, s4, 0xffff314; VI-NEXT: s_or_b32 s5, s6, s5315; VI-NEXT: s_or_b32 s4, s4, s7316; VI-NEXT: v_mov_b32_e32 v0, s4317; VI-NEXT: v_mov_b32_e32 v1, s5318; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0319; VI-NEXT: s_endpgm320;321; EG-LABEL: ashr_v4i16:322; EG: ; %bb.0:323; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]324; EG-NEXT: TEX 0 @6325; EG-NEXT: ALU 48, @10, KC0[CB0:0-32], KC1[]326; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T9.X, 1327; EG-NEXT: CF_END328; EG-NEXT: PAD329; EG-NEXT: Fetch clause starting at 6:330; EG-NEXT: VTX_READ_128 T9.XYZW, T9.X, 0, #1331; EG-NEXT: ALU clause starting at 8:332; EG-NEXT: MOV * T0.Y, T6.X,333; EG-NEXT: MOV * T9.X, KC0[2].Z,334; EG-NEXT: ALU clause starting at 10:335; EG-NEXT: BFE_INT T0.W, T9.X, 0.0, literal.x,336; EG-NEXT: AND_INT * T1.W, T9.Z, literal.y,337; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)338; EG-NEXT: ASHR * T0.W, PV.W, PS,339; EG-NEXT: AND_INT T0.W, PV.W, literal.x,340; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,341; EG-NEXT: 65535(9.183409e-41), -65536(nan)342; EG-NEXT: OR_INT * T0.W, PS, PV.W,343; EG-NEXT: MOV * T6.X, PV.W,344; EG-NEXT: MOV T0.Y, PV.X,345; EG-NEXT: LSHR * T0.W, T9.X, literal.x,346; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)347; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,348; EG-NEXT: LSHR * T1.W, T9.Z, literal.x,349; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)350; EG-NEXT: ASHR T0.W, PV.W, PS,351; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,352; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)353; EG-NEXT: LSHL * T0.W, PV.W, literal.x,354; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)355; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,356; EG-NEXT: MOV T6.X, PV.W,357; EG-NEXT: MOV T0.Y, T7.X,358; EG-NEXT: BFE_INT T0.W, T9.Y, 0.0, literal.x,359; EG-NEXT: AND_INT * T1.W, T9.W, literal.y,360; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)361; EG-NEXT: ASHR T0.W, PV.W, PS,362; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,363; EG-NEXT: -65536(nan), 0(0.000000e+00)364; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,365; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)366; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,367; EG-NEXT: MOV * T7.X, PV.W,368; EG-NEXT: MOV T0.Y, PV.X,369; EG-NEXT: LSHR * T0.W, T9.Y, literal.x,370; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)371; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,372; EG-NEXT: LSHR * T1.W, T9.W, literal.x,373; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)374; EG-NEXT: ASHR T0.W, PV.W, PS,375; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,376; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)377; EG-NEXT: LSHL * T0.W, PV.W, literal.x,378; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)379; EG-NEXT: LSHR T9.X, KC0[2].Y, literal.x,380; EG-NEXT: OR_INT * T10.Y, T1.W, PV.W,381; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)382; EG-NEXT: MOV T7.X, PV.Y,383; EG-NEXT: MOV * T10.X, T6.X,384 %b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %in, i16 1385 %a = load <4 x i16>, ptr addrspace(1) %in386 %b = load <4 x i16>, ptr addrspace(1) %b_ptr387 %result = ashr <4 x i16> %a, %b388 store <4 x i16> %result, ptr addrspace(1) %out389 ret void390}391 392define amdgpu_kernel void @s_ashr_i64(ptr addrspace(1) %out, i32 %in) {393; SI-LABEL: s_ashr_i64:394; SI: ; %bb.0: ; %entry395; SI-NEXT: s_load_dword s6, s[4:5], 0xb396; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9397; SI-NEXT: s_mov_b32 s3, 0xf000398; SI-NEXT: s_mov_b32 s2, -1399; SI-NEXT: s_waitcnt lgkmcnt(0)400; SI-NEXT: s_ashr_i32 s7, s6, 31401; SI-NEXT: s_ashr_i64 s[4:5], s[6:7], 8402; SI-NEXT: v_mov_b32_e32 v0, s4403; SI-NEXT: v_mov_b32_e32 v1, s5404; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0405; SI-NEXT: s_endpgm406;407; VI-LABEL: s_ashr_i64:408; VI: ; %bb.0: ; %entry409; VI-NEXT: s_load_dword s6, s[4:5], 0x2c410; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24411; VI-NEXT: s_mov_b32 s3, 0xf000412; VI-NEXT: s_mov_b32 s2, -1413; VI-NEXT: s_waitcnt lgkmcnt(0)414; VI-NEXT: s_ashr_i32 s7, s6, 31415; VI-NEXT: s_ashr_i64 s[4:5], s[6:7], 8416; VI-NEXT: v_mov_b32_e32 v0, s4417; VI-NEXT: v_mov_b32_e32 v1, s5418; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0419; VI-NEXT: s_endpgm420;421; EG-LABEL: s_ashr_i64:422; EG: ; %bb.0: ; %entry423; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]424; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1425; EG-NEXT: CF_END426; EG-NEXT: PAD427; EG-NEXT: ALU clause starting at 4:428; EG-NEXT: ASHR * T0.Y, KC0[2].Z, literal.x,429; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)430; EG-NEXT: BIT_ALIGN_INT T0.X, PV.Y, KC0[2].Z, literal.x,431; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,432; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)433entry:434 %in.ext = sext i32 %in to i64435 %ashr = ashr i64 %in.ext, 8436 store i64 %ashr, ptr addrspace(1) %out437 ret void438}439 440define amdgpu_kernel void @ashr_i64_2(ptr addrspace(1) %out, ptr addrspace(1) %in) {441; SI-LABEL: ashr_i64_2:442; SI: ; %bb.0: ; %entry443; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9444; SI-NEXT: s_mov_b32 s7, 0xf000445; SI-NEXT: s_mov_b32 s6, -1446; SI-NEXT: s_mov_b32 s10, s6447; SI-NEXT: s_mov_b32 s11, s7448; SI-NEXT: s_waitcnt lgkmcnt(0)449; SI-NEXT: s_mov_b32 s8, s2450; SI-NEXT: s_mov_b32 s9, s3451; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0452; SI-NEXT: s_mov_b32 s4, s0453; SI-NEXT: s_mov_b32 s5, s1454; SI-NEXT: s_waitcnt vmcnt(0)455; SI-NEXT: v_ashr_i64 v[0:1], v[0:1], v2456; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0457; SI-NEXT: s_endpgm458;459; VI-LABEL: ashr_i64_2:460; VI: ; %bb.0: ; %entry461; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24462; VI-NEXT: s_mov_b32 s7, 0xf000463; VI-NEXT: s_mov_b32 s6, -1464; VI-NEXT: s_mov_b32 s10, s6465; VI-NEXT: s_mov_b32 s11, s7466; VI-NEXT: s_waitcnt lgkmcnt(0)467; VI-NEXT: s_mov_b32 s8, s2468; VI-NEXT: s_mov_b32 s9, s3469; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0470; VI-NEXT: s_mov_b32 s4, s0471; VI-NEXT: s_mov_b32 s5, s1472; VI-NEXT: s_waitcnt vmcnt(0)473; VI-NEXT: v_ashrrev_i64 v[0:1], v2, v[0:1]474; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0475; VI-NEXT: s_endpgm476;477; EG-LABEL: ashr_i64_2:478; EG: ; %bb.0: ; %entry479; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]480; EG-NEXT: TEX 0 @6481; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]482; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1483; EG-NEXT: CF_END484; EG-NEXT: PAD485; EG-NEXT: Fetch clause starting at 6:486; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1487; EG-NEXT: ALU clause starting at 8:488; EG-NEXT: MOV * T0.X, KC0[2].Z,489; EG-NEXT: ALU clause starting at 9:490; EG-NEXT: AND_INT * T0.W, T0.Z, literal.x,491; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)492; EG-NEXT: ASHR T1.Z, T0.Y, PV.W,493; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, T0.Z,494; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,495; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)496; EG-NEXT: CNDE_INT T0.X, PS, PV.W, PV.Z,497; EG-NEXT: ASHR T0.W, T0.Y, literal.x,498; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,499; EG-NEXT: 31(4.344025e-44), 2(2.802597e-45)500; EG-NEXT: CNDE_INT * T0.Y, T1.W, T1.Z, PV.W,501entry:502 %b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1503 %a = load i64, ptr addrspace(1) %in504 %b = load i64, ptr addrspace(1) %b_ptr505 %result = ashr i64 %a, %b506 store i64 %result, ptr addrspace(1) %out507 ret void508}509 510define amdgpu_kernel void @ashr_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {511; SI-LABEL: ashr_v2i64:512; SI: ; %bb.0:513; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9514; SI-NEXT: s_mov_b32 s7, 0xf000515; SI-NEXT: s_mov_b32 s6, -1516; SI-NEXT: s_mov_b32 s10, s6517; SI-NEXT: s_mov_b32 s11, s7518; SI-NEXT: s_waitcnt lgkmcnt(0)519; SI-NEXT: s_mov_b32 s8, s2520; SI-NEXT: s_mov_b32 s9, s3521; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0522; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16523; SI-NEXT: s_mov_b32 s4, s0524; SI-NEXT: s_mov_b32 s5, s1525; SI-NEXT: s_waitcnt vmcnt(0)526; SI-NEXT: v_ashr_i64 v[2:3], v[2:3], v6527; SI-NEXT: v_ashr_i64 v[0:1], v[0:1], v4528; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0529; SI-NEXT: s_endpgm530;531; VI-LABEL: ashr_v2i64:532; VI: ; %bb.0:533; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24534; VI-NEXT: s_mov_b32 s7, 0xf000535; VI-NEXT: s_mov_b32 s6, -1536; VI-NEXT: s_mov_b32 s10, s6537; VI-NEXT: s_mov_b32 s11, s7538; VI-NEXT: s_waitcnt lgkmcnt(0)539; VI-NEXT: s_mov_b32 s8, s2540; VI-NEXT: s_mov_b32 s9, s3541; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0542; VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16543; VI-NEXT: s_mov_b32 s4, s0544; VI-NEXT: s_mov_b32 s5, s1545; VI-NEXT: s_waitcnt vmcnt(0)546; VI-NEXT: v_ashrrev_i64 v[2:3], v6, v[2:3]547; VI-NEXT: v_ashrrev_i64 v[0:1], v4, v[0:1]548; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0549; VI-NEXT: s_endpgm550;551; EG-LABEL: ashr_v2i64:552; EG: ; %bb.0:553; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]554; EG-NEXT: TEX 1 @6555; EG-NEXT: ALU 19, @11, KC0[CB0:0-32], KC1[]556; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1557; EG-NEXT: CF_END558; EG-NEXT: PAD559; EG-NEXT: Fetch clause starting at 6:560; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1561; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1562; EG-NEXT: ALU clause starting at 10:563; EG-NEXT: MOV * T0.X, KC0[2].Z,564; EG-NEXT: ALU clause starting at 11:565; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,566; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)567; EG-NEXT: ASHR T1.Y, T0.W, PV.W,568; EG-NEXT: AND_INT T2.Z, T1.Z, literal.x,569; EG-NEXT: BIT_ALIGN_INT T1.W, T0.W, T0.Z, T1.Z,570; EG-NEXT: AND_INT * T2.W, T1.X, literal.y,571; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)572; EG-NEXT: ASHR T2.Y, T0.Y, PS,573; EG-NEXT: CNDE_INT T0.Z, PV.Z, PV.W, PV.Y,574; EG-NEXT: BIT_ALIGN_INT T1.W, T0.Y, T0.X, T1.X,575; EG-NEXT: AND_INT * T2.W, T1.X, literal.x,576; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)577; EG-NEXT: CNDE_INT T0.X, PS, PV.W, PV.Y,578; EG-NEXT: ASHR T0.W, T0.W, literal.x,579; EG-NEXT: ASHR * T1.W, T0.Y, literal.x,580; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)581; EG-NEXT: CNDE_INT * T0.W, T2.Z, T1.Y, PV.W,582; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,583; EG-NEXT: CNDE_INT * T0.Y, T2.W, T2.Y, T1.W,584; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)585 %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %in, i64 1586 %a = load <2 x i64>, ptr addrspace(1) %in587 %b = load <2 x i64>, ptr addrspace(1) %b_ptr588 %result = ashr <2 x i64> %a, %b589 store <2 x i64> %result, ptr addrspace(1) %out590 ret void591}592 593; FIXME: Broken on r600594define amdgpu_kernel void @ashr_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {595; SI-LABEL: ashr_v4i64:596; SI: ; %bb.0:597; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9598; SI-NEXT: s_mov_b32 s7, 0xf000599; SI-NEXT: s_mov_b32 s6, -1600; SI-NEXT: s_mov_b32 s10, s6601; SI-NEXT: s_mov_b32 s11, s7602; SI-NEXT: s_waitcnt lgkmcnt(0)603; SI-NEXT: s_mov_b32 s8, s2604; SI-NEXT: s_mov_b32 s9, s3605; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48606; SI-NEXT: buffer_load_dwordx4 v[3:6], off, s[8:11], 0 offset:16607; SI-NEXT: buffer_load_dwordx4 v[7:10], off, s[8:11], 0608; SI-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:32609; SI-NEXT: s_mov_b32 s4, s0610; SI-NEXT: s_mov_b32 s5, s1611; SI-NEXT: s_waitcnt vmcnt(2)612; SI-NEXT: v_ashr_i64 v[5:6], v[5:6], v2613; SI-NEXT: v_ashr_i64 v[3:4], v[3:4], v0614; SI-NEXT: s_waitcnt vmcnt(0)615; SI-NEXT: v_ashr_i64 v[9:10], v[9:10], v13616; SI-NEXT: v_ashr_i64 v[7:8], v[7:8], v11617; SI-NEXT: buffer_store_dwordx4 v[3:6], off, s[4:7], 0 offset:16618; SI-NEXT: buffer_store_dwordx4 v[7:10], off, s[4:7], 0619; SI-NEXT: s_endpgm620;621; VI-LABEL: ashr_v4i64:622; VI: ; %bb.0:623; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24624; VI-NEXT: s_mov_b32 s3, 0xf000625; VI-NEXT: s_mov_b32 s2, -1626; VI-NEXT: s_mov_b32 s10, s2627; VI-NEXT: s_mov_b32 s11, s3628; VI-NEXT: s_waitcnt lgkmcnt(0)629; VI-NEXT: s_mov_b32 s8, s6630; VI-NEXT: s_mov_b32 s9, s7631; VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48632; VI-NEXT: buffer_load_dwordx4 v[3:6], off, s[8:11], 0 offset:16633; VI-NEXT: buffer_load_dwordx4 v[7:10], off, s[8:11], 0634; VI-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:32635; VI-NEXT: s_mov_b32 s0, s4636; VI-NEXT: s_mov_b32 s1, s5637; VI-NEXT: s_waitcnt vmcnt(2)638; VI-NEXT: v_ashrrev_i64 v[5:6], v2, v[5:6]639; VI-NEXT: v_ashrrev_i64 v[3:4], v0, v[3:4]640; VI-NEXT: s_waitcnt vmcnt(0)641; VI-NEXT: v_ashrrev_i64 v[9:10], v13, v[9:10]642; VI-NEXT: v_ashrrev_i64 v[7:8], v11, v[7:8]643; VI-NEXT: buffer_store_dwordx4 v[3:6], off, s[0:3], 0 offset:16644; VI-NEXT: buffer_store_dwordx4 v[7:10], off, s[0:3], 0645; VI-NEXT: s_endpgm646;647; EG-LABEL: ashr_v4i64:648; EG: ; %bb.0:649; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]650; EG-NEXT: TEX 3 @6651; EG-NEXT: ALU 39, @15, KC0[CB0:0-32], KC1[]652; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 0653; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1654; EG-NEXT: CF_END655; EG-NEXT: Fetch clause starting at 6:656; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 32, #1657; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 48, #1658; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 0, #1659; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 16, #1660; EG-NEXT: ALU clause starting at 14:661; EG-NEXT: MOV * T0.X, KC0[2].Z,662; EG-NEXT: ALU clause starting at 15:663; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,664; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)665; EG-NEXT: ASHR T1.Y, T0.W, literal.x,666; EG-NEXT: ASHR T4.Z, T3.W, PV.W, BS:VEC_120/SCL_212667; EG-NEXT: AND_INT T1.W, T1.Z, literal.y,668; EG-NEXT: AND_INT * T2.W, T2.Z, literal.x,669; EG-NEXT: 31(4.344025e-44), 32(4.484155e-44)670; EG-NEXT: BIT_ALIGN_INT T4.X, T3.W, T3.Z, T1.Z,671; EG-NEXT: ASHR T2.Y, T0.W, PS, BS:VEC_120/SCL_212672; EG-NEXT: AND_INT * T1.Z, T2.Z, literal.x,673; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)674; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, T2.Z,675; EG-NEXT: AND_INT * T2.W, T2.X, literal.x,676; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)677; EG-NEXT: AND_INT T5.X, T1.X, literal.x,678; EG-NEXT: ASHR T4.Y, T0.Y, PS,679; EG-NEXT: CNDE_INT T0.Z, T1.Z, PV.W, T2.Y,680; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, T2.X,681; EG-NEXT: AND_INT * T2.W, T2.X, literal.y,682; EG-NEXT: 31(4.344025e-44), 32(4.484155e-44)683; EG-NEXT: CNDE_INT T0.X, PS, PV.W, PV.Y,684; EG-NEXT: ASHR T5.Y, T3.Y, PV.X,685; EG-NEXT: CNDE_INT T2.Z, T1.W, T4.X, T4.Z,686; EG-NEXT: BIT_ALIGN_INT T0.W, T3.Y, T3.X, T1.X, BS:VEC_102/SCL_221687; EG-NEXT: AND_INT * T4.W, T1.X, literal.x,688; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)689; EG-NEXT: CNDE_INT T2.X, PS, PV.W, PV.Y,690; EG-NEXT: ASHR T6.Y, T3.W, literal.x,691; EG-NEXT: ASHR T3.Z, T0.Y, literal.x, BS:VEC_201692; EG-NEXT: ADD_INT T3.W, KC0[2].Y, literal.y,693; EG-NEXT: CNDE_INT * T0.W, T1.Z, T2.Y, T1.Y,694; EG-NEXT: 31(4.344025e-44), 16(2.242078e-44)695; EG-NEXT: LSHR T1.X, PV.W, literal.x,696; EG-NEXT: CNDE_INT T0.Y, T2.W, T4.Y, PV.Z,697; EG-NEXT: ASHR T3.W, T3.Y, literal.y,698; EG-NEXT: CNDE_INT * T2.W, T1.W, T4.Z, PV.Y,699; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)700; EG-NEXT: LSHR T3.X, KC0[2].Y, literal.x,701; EG-NEXT: CNDE_INT * T2.Y, T4.W, T5.Y, PV.W,702; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)703 %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 1704 %a = load <4 x i64>, ptr addrspace(1) %in705 %b = load <4 x i64>, ptr addrspace(1) %b_ptr706 %result = ashr <4 x i64> %a, %b707 store <4 x i64> %result, ptr addrspace(1) %out708 ret void709}710 711define amdgpu_kernel void @s_ashr_32_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {712; SI-LABEL: s_ashr_32_i64:713; SI: ; %bb.0:714; SI-NEXT: s_load_dword s8, s[4:5], 0x14715; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x1d716; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9717; SI-NEXT: s_mov_b32 s3, 0xf000718; SI-NEXT: s_mov_b32 s2, -1719; SI-NEXT: s_waitcnt lgkmcnt(0)720; SI-NEXT: s_ashr_i32 s5, s8, 31721; SI-NEXT: s_add_u32 s4, s8, s6722; SI-NEXT: s_addc_u32 s5, s5, s7723; SI-NEXT: v_mov_b32_e32 v0, s4724; SI-NEXT: v_mov_b32_e32 v1, s5725; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0726; SI-NEXT: s_endpgm727;728; VI-LABEL: s_ashr_32_i64:729; VI: ; %bb.0:730; VI-NEXT: s_load_dword s8, s[4:5], 0x50731; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x74732; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24733; VI-NEXT: s_mov_b32 s3, 0xf000734; VI-NEXT: s_mov_b32 s2, -1735; VI-NEXT: s_waitcnt lgkmcnt(0)736; VI-NEXT: s_ashr_i32 s5, s8, 31737; VI-NEXT: s_add_u32 s4, s8, s6738; VI-NEXT: s_addc_u32 s5, s5, s7739; VI-NEXT: v_mov_b32_e32 v0, s4740; VI-NEXT: v_mov_b32_e32 v1, s5741; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0742; VI-NEXT: s_endpgm743;744; EG-LABEL: s_ashr_32_i64:745; EG: ; %bb.0:746; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]747; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1748; EG-NEXT: CF_END749; EG-NEXT: PAD750; EG-NEXT: ALU clause starting at 4:751; EG-NEXT: ASHR * T0.W, KC0[5].X, literal.x,752; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)753; EG-NEXT: ADD_INT * T0.W, PV.W, KC0[7].Z,754; EG-NEXT: ADDC_UINT * T1.W, KC0[5].X, KC0[7].Y,755; EG-NEXT: ADD_INT * T0.Y, T0.W, PV.W,756; EG-NEXT: ADD_INT * T0.X, KC0[5].X, KC0[7].Y,757; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,758; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)759 %result = ashr i64 %a, 32760 %add = add i64 %result, %b761 store i64 %add, ptr addrspace(1) %out762 ret void763}764 765define amdgpu_kernel void @v_ashr_32_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {766; SI-LABEL: v_ashr_32_i64:767; SI: ; %bb.0:768; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9769; SI-NEXT: s_mov_b32 s7, 0xf000770; SI-NEXT: s_mov_b32 s6, 0771; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0772; SI-NEXT: v_mov_b32_e32 v1, 0773; SI-NEXT: s_waitcnt lgkmcnt(0)774; SI-NEXT: s_mov_b64 s[8:9], s[2:3]775; SI-NEXT: s_mov_b64 s[10:11], s[6:7]776; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 offset:4777; SI-NEXT: s_mov_b64 s[4:5], s[0:1]778; SI-NEXT: s_waitcnt vmcnt(0)779; SI-NEXT: v_ashrrev_i32_e32 v3, 31, v2780; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64781; SI-NEXT: s_endpgm782;783; VI-LABEL: v_ashr_32_i64:784; VI: ; %bb.0:785; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24786; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0787; VI-NEXT: s_waitcnt lgkmcnt(0)788; VI-NEXT: v_mov_b32_e32 v0, s3789; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v2790; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc791; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v1792; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc793; VI-NEXT: flat_load_dword v0, v[0:1]794; VI-NEXT: v_mov_b32_e32 v1, s1795; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2796; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc797; VI-NEXT: s_waitcnt vmcnt(0)798; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0799; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]800; VI-NEXT: s_endpgm801;802; EG-LABEL: v_ashr_32_i64:803; EG: ; %bb.0:804; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]805; EG-NEXT: TEX 0 @6806; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]807; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1808; EG-NEXT: CF_END809; EG-NEXT: PAD810; EG-NEXT: Fetch clause starting at 6:811; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1812; EG-NEXT: ALU clause starting at 8:813; EG-NEXT: LSHL * T0.W, T0.X, literal.x,814; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)815; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,816; EG-NEXT: ALU clause starting at 11:817; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,818; EG-NEXT: LSHR T1.X, PV.W, literal.x,819; EG-NEXT: ASHR * T0.Y, T0.X, literal.y,820; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)821 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0822 %gep.in = getelementptr i64, ptr addrspace(1) %in, i32 %tid823 %gep.out = getelementptr i64, ptr addrspace(1) %out, i32 %tid824 %a = load i64, ptr addrspace(1) %gep.in825 %result = ashr i64 %a, 32826 store i64 %result, ptr addrspace(1) %gep.out827 ret void828}829 830define amdgpu_kernel void @s_ashr_33_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {831; SI-LABEL: s_ashr_33_i64:832; SI: ; %bb.0:833; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13834; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9835; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x1d836; SI-NEXT: s_mov_b32 s3, 0xf000837; SI-NEXT: s_mov_b32 s2, -1838; SI-NEXT: s_waitcnt lgkmcnt(0)839; SI-NEXT: s_ashr_i32 s6, s7, 31840; SI-NEXT: s_ashr_i32 s7, s7, 1841; SI-NEXT: s_add_u32 s4, s7, s4842; SI-NEXT: s_addc_u32 s5, s6, s5843; SI-NEXT: v_mov_b32_e32 v0, s4844; SI-NEXT: v_mov_b32_e32 v1, s5845; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0846; SI-NEXT: s_endpgm847;848; VI-LABEL: s_ashr_33_i64:849; VI: ; %bb.0:850; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x4c851; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24852; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x74853; VI-NEXT: s_mov_b32 s3, 0xf000854; VI-NEXT: s_mov_b32 s2, -1855; VI-NEXT: s_waitcnt lgkmcnt(0)856; VI-NEXT: s_ashr_i32 s6, s7, 31857; VI-NEXT: s_ashr_i32 s7, s7, 1858; VI-NEXT: s_add_u32 s4, s7, s4859; VI-NEXT: s_addc_u32 s5, s6, s5860; VI-NEXT: v_mov_b32_e32 v0, s4861; VI-NEXT: v_mov_b32_e32 v1, s5862; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0863; VI-NEXT: s_endpgm864;865; EG-LABEL: s_ashr_33_i64:866; EG: ; %bb.0:867; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]868; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1869; EG-NEXT: CF_END870; EG-NEXT: PAD871; EG-NEXT: ALU clause starting at 4:872; EG-NEXT: ASHR T0.W, KC0[5].X, 1,873; EG-NEXT: ASHR * T1.W, KC0[5].X, literal.x,874; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)875; EG-NEXT: ADD_INT T1.W, PS, KC0[7].Z,876; EG-NEXT: ADDC_UINT * T2.W, PV.W, KC0[7].Y,877; EG-NEXT: ADD_INT * T0.Y, PV.W, PS,878; EG-NEXT: ADD_INT T0.X, T0.W, KC0[7].Y,879; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,880; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)881 %result = ashr i64 %a, 33882 %add = add i64 %result, %b883 store i64 %add, ptr addrspace(1) %out884 ret void885}886 887define amdgpu_kernel void @v_ashr_33_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {888; SI-LABEL: v_ashr_33_i64:889; SI: ; %bb.0:890; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9891; SI-NEXT: s_mov_b32 s7, 0xf000892; SI-NEXT: s_mov_b32 s6, 0893; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0894; SI-NEXT: v_mov_b32_e32 v1, 0895; SI-NEXT: s_waitcnt lgkmcnt(0)896; SI-NEXT: s_mov_b64 s[4:5], s[2:3]897; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64898; SI-NEXT: s_mov_b64 s[2:3], s[6:7]899; SI-NEXT: s_waitcnt vmcnt(0)900; SI-NEXT: v_ashrrev_i32_e32 v4, 31, v3901; SI-NEXT: v_ashrrev_i32_e32 v3, 1, v3902; SI-NEXT: buffer_store_dwordx2 v[3:4], v[0:1], s[0:3], 0 addr64903; SI-NEXT: s_endpgm904;905; VI-LABEL: v_ashr_33_i64:906; VI: ; %bb.0:907; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24908; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0909; VI-NEXT: s_waitcnt lgkmcnt(0)910; VI-NEXT: v_mov_b32_e32 v1, s3911; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2912; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc913; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]914; VI-NEXT: s_waitcnt vmcnt(0)915; VI-NEXT: v_mov_b32_e32 v0, s1916; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2917; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc918; VI-NEXT: v_ashrrev_i32_e32 v5, 31, v1919; VI-NEXT: v_ashrrev_i32_e32 v4, 1, v1920; VI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]921; VI-NEXT: s_endpgm922;923; EG-LABEL: v_ashr_33_i64:924; EG: ; %bb.0:925; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]926; EG-NEXT: TEX 0 @6927; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]928; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1929; EG-NEXT: CF_END930; EG-NEXT: PAD931; EG-NEXT: Fetch clause starting at 6:932; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1933; EG-NEXT: ALU clause starting at 8:934; EG-NEXT: LSHL * T0.W, T0.X, literal.x,935; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)936; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,937; EG-NEXT: ALU clause starting at 11:938; EG-NEXT: ASHR * T0.Y, T0.X, literal.x,939; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)940; EG-NEXT: ASHR T0.X, T0.X, 1,941; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,942; EG-NEXT: LSHR * T1.X, PV.W, literal.x,943; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)944 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0945 %gep.in = getelementptr i64, ptr addrspace(1) %in, i32 %tid946 %gep.out = getelementptr i64, ptr addrspace(1) %out, i32 %tid947 %a = load i64, ptr addrspace(1) %gep.in948 %result = ashr i64 %a, 33949 store i64 %result, ptr addrspace(1) %gep.out950 ret void951}952 953define amdgpu_kernel void @s_ashr_62_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {954; SI-LABEL: s_ashr_62_i64:955; SI: ; %bb.0:956; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13957; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9958; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x1d959; SI-NEXT: s_mov_b32 s3, 0xf000960; SI-NEXT: s_mov_b32 s2, -1961; SI-NEXT: s_waitcnt lgkmcnt(0)962; SI-NEXT: s_ashr_i32 s6, s7, 31963; SI-NEXT: s_ashr_i32 s7, s7, 30964; SI-NEXT: s_add_u32 s4, s7, s4965; SI-NEXT: s_addc_u32 s5, s6, s5966; SI-NEXT: v_mov_b32_e32 v0, s4967; SI-NEXT: v_mov_b32_e32 v1, s5968; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0969; SI-NEXT: s_endpgm970;971; VI-LABEL: s_ashr_62_i64:972; VI: ; %bb.0:973; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x4c974; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24975; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x74976; VI-NEXT: s_mov_b32 s3, 0xf000977; VI-NEXT: s_mov_b32 s2, -1978; VI-NEXT: s_waitcnt lgkmcnt(0)979; VI-NEXT: s_ashr_i32 s6, s7, 31980; VI-NEXT: s_ashr_i32 s7, s7, 30981; VI-NEXT: s_add_u32 s4, s7, s4982; VI-NEXT: s_addc_u32 s5, s6, s5983; VI-NEXT: v_mov_b32_e32 v0, s4984; VI-NEXT: v_mov_b32_e32 v1, s5985; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0986; VI-NEXT: s_endpgm987;988; EG-LABEL: s_ashr_62_i64:989; EG: ; %bb.0:990; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]991; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1992; EG-NEXT: CF_END993; EG-NEXT: PAD994; EG-NEXT: ALU clause starting at 4:995; EG-NEXT: ASHR T0.W, KC0[5].X, literal.x,996; EG-NEXT: ASHR * T1.W, KC0[5].X, literal.y,997; EG-NEXT: 30(4.203895e-44), 31(4.344025e-44)998; EG-NEXT: ADD_INT T1.W, PS, KC0[7].Z,999; EG-NEXT: ADDC_UINT * T2.W, PV.W, KC0[7].Y,1000; EG-NEXT: ADD_INT * T0.Y, PV.W, PS,1001; EG-NEXT: ADD_INT T0.X, T0.W, KC0[7].Y,1002; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1003; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1004 %result = ashr i64 %a, 621005 %add = add i64 %result, %b1006 store i64 %add, ptr addrspace(1) %out1007 ret void1008}1009 1010define amdgpu_kernel void @v_ashr_62_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {1011; SI-LABEL: v_ashr_62_i64:1012; SI: ; %bb.0:1013; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91014; SI-NEXT: s_mov_b32 s7, 0xf0001015; SI-NEXT: s_mov_b32 s6, 01016; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v01017; SI-NEXT: v_mov_b32_e32 v1, 01018; SI-NEXT: s_waitcnt lgkmcnt(0)1019; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1020; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr641021; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1022; SI-NEXT: s_waitcnt vmcnt(0)1023; SI-NEXT: v_ashrrev_i32_e32 v4, 31, v31024; SI-NEXT: v_ashrrev_i32_e32 v3, 30, v31025; SI-NEXT: buffer_store_dwordx2 v[3:4], v[0:1], s[0:3], 0 addr641026; SI-NEXT: s_endpgm1027;1028; VI-LABEL: v_ashr_62_i64:1029; VI: ; %bb.0:1030; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241031; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v01032; VI-NEXT: s_waitcnt lgkmcnt(0)1033; VI-NEXT: v_mov_b32_e32 v1, s31034; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21035; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1036; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]1037; VI-NEXT: s_waitcnt vmcnt(0)1038; VI-NEXT: v_mov_b32_e32 v0, s11039; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v21040; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc1041; VI-NEXT: v_ashrrev_i32_e32 v5, 31, v11042; VI-NEXT: v_ashrrev_i32_e32 v4, 30, v11043; VI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]1044; VI-NEXT: s_endpgm1045;1046; EG-LABEL: v_ashr_62_i64:1047; EG: ; %bb.0:1048; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1049; EG-NEXT: TEX 0 @61050; EG-NEXT: ALU 6, @11, KC0[CB0:0-32], KC1[]1051; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11052; EG-NEXT: CF_END1053; EG-NEXT: PAD1054; EG-NEXT: Fetch clause starting at 6:1055; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #11056; EG-NEXT: ALU clause starting at 8:1057; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1058; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1059; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1060; EG-NEXT: ALU clause starting at 11:1061; EG-NEXT: ASHR * T0.Y, T0.X, literal.x,1062; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1063; EG-NEXT: ASHR T0.X, T0.X, literal.x,1064; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,1065; EG-NEXT: 30(4.203895e-44), 0(0.000000e+00)1066; EG-NEXT: LSHR * T1.X, PV.W, literal.x,1067; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1068 %tid = call i32 @llvm.amdgcn.workitem.id.x() #01069 %gep.in = getelementptr i64, ptr addrspace(1) %in, i32 %tid1070 %gep.out = getelementptr i64, ptr addrspace(1) %out, i32 %tid1071 %a = load i64, ptr addrspace(1) %gep.in1072 %result = ashr i64 %a, 621073 store i64 %result, ptr addrspace(1) %gep.out1074 ret void1075}1076 1077define amdgpu_kernel void @s_ashr_63_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {1078; SI-LABEL: s_ashr_63_i64:1079; SI: ; %bb.0:1080; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x131081; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x1d1082; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91083; SI-NEXT: s_mov_b32 s3, 0xf0001084; SI-NEXT: s_mov_b32 s2, -11085; SI-NEXT: s_waitcnt lgkmcnt(0)1086; SI-NEXT: s_ashr_i32 s5, s7, 311087; SI-NEXT: s_add_u32 s4, s5, s81088; SI-NEXT: s_addc_u32 s5, s5, s91089; SI-NEXT: v_mov_b32_e32 v0, s41090; SI-NEXT: v_mov_b32_e32 v1, s51091; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01092; SI-NEXT: s_endpgm1093;1094; VI-LABEL: s_ashr_63_i64:1095; VI: ; %bb.0:1096; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x4c1097; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x741098; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241099; VI-NEXT: s_mov_b32 s3, 0xf0001100; VI-NEXT: s_mov_b32 s2, -11101; VI-NEXT: s_waitcnt lgkmcnt(0)1102; VI-NEXT: s_ashr_i32 s5, s7, 311103; VI-NEXT: s_add_u32 s4, s5, s81104; VI-NEXT: s_addc_u32 s5, s5, s91105; VI-NEXT: v_mov_b32_e32 v0, s41106; VI-NEXT: v_mov_b32_e32 v1, s51107; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01108; VI-NEXT: s_endpgm1109;1110; EG-LABEL: s_ashr_63_i64:1111; EG: ; %bb.0:1112; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1113; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11114; EG-NEXT: CF_END1115; EG-NEXT: PAD1116; EG-NEXT: ALU clause starting at 4:1117; EG-NEXT: ASHR * T0.W, KC0[5].X, literal.x,1118; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1119; EG-NEXT: ADD_INT T1.W, PV.W, KC0[7].Z,1120; EG-NEXT: ADDC_UINT * T2.W, PV.W, KC0[7].Y,1121; EG-NEXT: ADD_INT * T0.Y, PV.W, PS,1122; EG-NEXT: ADD_INT T0.X, T0.W, KC0[7].Y,1123; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1124; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1125 %result = ashr i64 %a, 631126 %add = add i64 %result, %b1127 store i64 %add, ptr addrspace(1) %out1128 ret void1129}1130 1131define amdgpu_kernel void @v_ashr_63_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {1132; SI-LABEL: v_ashr_63_i64:1133; SI: ; %bb.0:1134; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91135; SI-NEXT: s_mov_b32 s7, 0xf0001136; SI-NEXT: s_mov_b32 s6, 01137; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v01138; SI-NEXT: v_mov_b32_e32 v1, 01139; SI-NEXT: s_waitcnt lgkmcnt(0)1140; SI-NEXT: s_mov_b64 s[4:5], s[2:3]1141; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr641142; SI-NEXT: s_mov_b64 s[2:3], s[6:7]1143; SI-NEXT: s_waitcnt vmcnt(0)1144; SI-NEXT: v_ashrrev_i32_e32 v2, 31, v31145; SI-NEXT: v_mov_b32_e32 v3, v21146; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr641147; SI-NEXT: s_endpgm1148;1149; VI-LABEL: v_ashr_63_i64:1150; VI: ; %bb.0:1151; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241152; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v01153; VI-NEXT: s_waitcnt lgkmcnt(0)1154; VI-NEXT: v_mov_b32_e32 v1, s31155; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v21156; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1157; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]1158; VI-NEXT: s_waitcnt vmcnt(0)1159; VI-NEXT: v_mov_b32_e32 v0, s11160; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v21161; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v0, vcc1162; VI-NEXT: v_ashrrev_i32_e32 v0, 31, v11163; VI-NEXT: v_mov_b32_e32 v1, v01164; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1165; VI-NEXT: s_endpgm1166;1167; EG-LABEL: v_ashr_63_i64:1168; EG: ; %bb.0:1169; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]1170; EG-NEXT: TEX 0 @61171; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]1172; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11173; EG-NEXT: CF_END1174; EG-NEXT: PAD1175; EG-NEXT: Fetch clause starting at 6:1176; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #11177; EG-NEXT: ALU clause starting at 8:1178; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1179; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1180; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,1181; EG-NEXT: ALU clause starting at 11:1182; EG-NEXT: ASHR T0.X, T0.X, literal.x,1183; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,1184; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1185; EG-NEXT: LSHR T1.X, PV.W, literal.x,1186; EG-NEXT: MOV * T0.Y, PV.X,1187; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1188 %tid = call i32 @llvm.amdgcn.workitem.id.x() #01189 %gep.in = getelementptr i64, ptr addrspace(1) %in, i32 %tid1190 %gep.out = getelementptr i64, ptr addrspace(1) %out, i32 %tid1191 %a = load i64, ptr addrspace(1) %gep.in1192 %result = ashr i64 %a, 631193 store i64 %result, ptr addrspace(1) %gep.out1194 ret void1195}1196 1197attributes #0 = { nounwind readnone }1198