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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52;; Test reduction of:3;;4;; DST = lshr i64 X, Y5;;6;; where Y is in the range [63-32] to:7;;8;; DST = [srl i32 X, (Y & 0x1F), 0]9 10; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s11 12;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;13; Test range with metadata14;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;15 16define i64 @srl_metadata(i64 %arg0, ptr %arg1.ptr) {17; CHECK-LABEL: srl_metadata:18; CHECK: ; %bb.0:19; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)20; CHECK-NEXT: flat_load_dword v0, v[2:3]21; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)22; CHECK-NEXT: v_lshrrev_b32_e32 v0, v0, v123; CHECK-NEXT: v_mov_b32_e32 v1, 024; CHECK-NEXT: s_setpc_b64 s[30:31]25 %shift.amt = load i64, ptr %arg1.ptr, !range !0, !noundef !{}26 %srl = lshr i64 %arg0, %shift.amt27 ret i64 %srl28}29 30define amdgpu_ps i64 @srl_metadata_sgpr_return(i64 inreg %arg0, ptr addrspace(1) inreg %arg1.ptr) {31; CHECK-LABEL: srl_metadata_sgpr_return:32; CHECK: ; %bb.0:33; CHECK-NEXT: s_load_dword s0, s[2:3], 0x034; CHECK-NEXT: s_waitcnt lgkmcnt(0)35; CHECK-NEXT: s_lshr_b32 s0, s1, s036; CHECK-NEXT: s_mov_b32 s1, 037; CHECK-NEXT: ; return to shader part epilog38 %shift.amt = load i64, ptr addrspace(1) %arg1.ptr, !range !0, !noundef !{}39 %srl = lshr i64 %arg0, %shift.amt40 ret i64 %srl41}42 43; Exact attribute does not inhibit reduction44define i64 @srl_exact_metadata(i64 %arg0, ptr %arg1.ptr) {45; CHECK-LABEL: srl_exact_metadata:46; CHECK: ; %bb.0:47; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; CHECK-NEXT: flat_load_dword v0, v[2:3]49; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)50; CHECK-NEXT: v_lshrrev_b32_e32 v0, v0, v151; CHECK-NEXT: v_mov_b32_e32 v1, 052; CHECK-NEXT: s_setpc_b64 s[30:31]53 %shift.amt = load i64, ptr %arg1.ptr, !range !0, !noundef !{}54 %srl = lshr exact i64 %arg0, %shift.amt55 ret i64 %srl56}57 58define i64 @srl_metadata_two_ranges(i64 %arg0, ptr %arg1.ptr) {59; CHECK-LABEL: srl_metadata_two_ranges:60; CHECK: ; %bb.0:61; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)62; CHECK-NEXT: flat_load_dword v0, v[2:3]63; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)64; CHECK-NEXT: v_lshrrev_b32_e32 v0, v0, v165; CHECK-NEXT: v_mov_b32_e32 v1, 066; CHECK-NEXT: s_setpc_b64 s[30:31]67 %shift.amt = load i64, ptr %arg1.ptr, !range !1, !noundef !{}68 %srl = lshr i64 %arg0, %shift.amt69 ret i64 %srl70}71 72; Known minimum is too low. Reduction must not be done.73define i64 @srl_metadata_out_of_range(i64 %arg0, ptr %arg1.ptr) {74; CHECK-LABEL: srl_metadata_out_of_range:75; CHECK: ; %bb.0:76; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)77; CHECK-NEXT: flat_load_dword v2, v[2:3]78; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)79; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]80; CHECK-NEXT: s_setpc_b64 s[30:31]81 %shift.amt = load i64, ptr %arg1.ptr, !range !2, !noundef !{}82 %srl = lshr i64 %arg0, %shift.amt83 ret i64 %srl84}85 86; Bounds cannot be truncated to i32 when load is narrowed to i32.87; Reduction must not be done.88; Bounds were chosen so that if bounds were truncated to i32 the89; known minimum would be 32 and the srl would be erroneously reduced.90define i64 @srl_metadata_cant_be_narrowed_to_i32(i64 %arg0, ptr %arg1.ptr) {91; CHECK-LABEL: srl_metadata_cant_be_narrowed_to_i32:92; CHECK: ; %bb.0:93; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)94; CHECK-NEXT: flat_load_dword v2, v[2:3]95; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)96; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]97; CHECK-NEXT: s_setpc_b64 s[30:31]98 %shift.amt = load i64, ptr %arg1.ptr, !range !3, !noundef !{}99 %srl = lshr i64 %arg0, %shift.amt100 ret i64 %srl101}102 103define <2 x i64> @srl_v2_metadata(<2 x i64> %arg0, ptr %arg1.ptr) {104; CHECK-LABEL: srl_v2_metadata:105; CHECK: ; %bb.0:106; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)107; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[4:5]108; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)109; CHECK-NEXT: v_lshrrev_b32_e32 v0, v4, v1110; CHECK-NEXT: v_lshrrev_b32_e32 v2, v6, v3111; CHECK-NEXT: v_mov_b32_e32 v1, 0112; CHECK-NEXT: v_mov_b32_e32 v3, 0113; CHECK-NEXT: s_setpc_b64 s[30:31]114 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}115 %srl = lshr <2 x i64> %arg0, %shift.amt116 ret <2 x i64> %srl117}118 119; Exact attribute does not inhibit reduction120define <2 x i64> @srl_exact_v2_metadata(<2 x i64> %arg0, ptr %arg1.ptr) {121; CHECK-LABEL: srl_exact_v2_metadata:122; CHECK: ; %bb.0:123; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)124; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[4:5]125; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)126; CHECK-NEXT: v_lshrrev_b32_e32 v0, v4, v1127; CHECK-NEXT: v_lshrrev_b32_e32 v2, v6, v3128; CHECK-NEXT: v_mov_b32_e32 v1, 0129; CHECK-NEXT: v_mov_b32_e32 v3, 0130; CHECK-NEXT: s_setpc_b64 s[30:31]131 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}132 %srl = lshr exact <2 x i64> %arg0, %shift.amt133 ret <2 x i64> %srl134}135 136define <3 x i64> @srl_v3_metadata(<3 x i64> %arg0, ptr %arg1.ptr) {137; CHECK-LABEL: srl_v3_metadata:138; CHECK: ; %bb.0:139; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)140; CHECK-NEXT: flat_load_dword v0, v[6:7] offset:16141; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[6:7]142; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)143; CHECK-NEXT: v_lshrrev_b32_e32 v4, v0, v5144; CHECK-NEXT: v_lshrrev_b32_e32 v0, v8, v1145; CHECK-NEXT: v_lshrrev_b32_e32 v2, v10, v3146; CHECK-NEXT: v_mov_b32_e32 v1, 0147; CHECK-NEXT: v_mov_b32_e32 v3, 0148; CHECK-NEXT: v_mov_b32_e32 v5, 0149; CHECK-NEXT: s_setpc_b64 s[30:31]150 %shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}151 %srl = lshr <3 x i64> %arg0, %shift.amt152 ret <3 x i64> %srl153}154 155define <4 x i64> @srl_v4_metadata(<4 x i64> %arg0, ptr %arg1.ptr) {156; CHECK-LABEL: srl_v4_metadata:157; CHECK: ; %bb.0:158; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)159; CHECK-NEXT: flat_load_dwordx4 v[10:13], v[8:9]160; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)161; CHECK-NEXT: flat_load_dwordx4 v[13:16], v[8:9] offset:16162; CHECK-NEXT: ; kill: killed $vgpr8 killed $vgpr9163; CHECK-NEXT: v_lshrrev_b32_e32 v0, v10, v1164; CHECK-NEXT: v_lshrrev_b32_e32 v2, v12, v3165; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)166; CHECK-NEXT: v_lshrrev_b32_e32 v4, v13, v5167; CHECK-NEXT: v_lshrrev_b32_e32 v6, v15, v7168; CHECK-NEXT: v_mov_b32_e32 v1, 0169; CHECK-NEXT: v_mov_b32_e32 v3, 0170; CHECK-NEXT: v_mov_b32_e32 v5, 0171; CHECK-NEXT: v_mov_b32_e32 v7, 0172; CHECK-NEXT: s_setpc_b64 s[30:31]173 %shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !0, !noundef !{}174 %srl = lshr <4 x i64> %arg0, %shift.amt175 ret <4 x i64> %srl176}177 178!0 = !{i64 32, i64 64}179!1 = !{i64 32, i64 38, i64 42, i64 48}180!2 = !{i64 31, i64 38, i64 42, i64 48}181!3 = !{i64 32, i64 38, i64 2147483680, i64 2147483681}182 183;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;184; Test range with an "or X, 16"185;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;186 187; These cases must not be reduced because the known minimum, 16, is not in range.188 189define i64 @srl_or16(i64 %arg0, i64 %shift_amt) {190; CHECK-LABEL: srl_or16:191; CHECK: ; %bb.0:192; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)193; CHECK-NEXT: v_or_b32_e32 v2, 16, v2194; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]195; CHECK-NEXT: s_setpc_b64 s[30:31]196 %or = or i64 %shift_amt, 16197 %srl = lshr i64 %arg0, %or198 ret i64 %srl199}200 201define <2 x i64> @srl_v2_or16(<2 x i64> %arg0, <2 x i64> %shift_amt) {202; CHECK-LABEL: srl_v2_or16:203; CHECK: ; %bb.0:204; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)205; CHECK-NEXT: v_or_b32_e32 v5, 16, v6206; CHECK-NEXT: v_or_b32_e32 v4, 16, v4207; CHECK-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]208; CHECK-NEXT: v_lshrrev_b64 v[2:3], v5, v[2:3]209; CHECK-NEXT: s_setpc_b64 s[30:31]210 %or = or <2 x i64> %shift_amt, splat (i64 16)211 %srl = lshr <2 x i64> %arg0, %or212 ret <2 x i64> %srl213}214 215define <3 x i64> @srl_v3_or16(<3 x i64> %arg0, <3 x i64> %shift_amt) {216; CHECK-LABEL: srl_v3_or16:217; CHECK: ; %bb.0:218; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)219; CHECK-NEXT: v_or_b32_e32 v7, 16, v10220; CHECK-NEXT: v_or_b32_e32 v8, 16, v8221; CHECK-NEXT: v_or_b32_e32 v6, 16, v6222; CHECK-NEXT: v_lshrrev_b64 v[0:1], v6, v[0:1]223; CHECK-NEXT: v_lshrrev_b64 v[2:3], v8, v[2:3]224; CHECK-NEXT: v_lshrrev_b64 v[4:5], v7, v[4:5]225; CHECK-NEXT: s_setpc_b64 s[30:31]226 %or = or <3 x i64> %shift_amt, splat (i64 16)227 %srl = lshr <3 x i64> %arg0, %or228 ret <3 x i64> %srl229}230 231define <4 x i64> @srl_v4_or16(<4 x i64> %arg0, <4 x i64> %shift_amt) {232; CHECK-LABEL: srl_v4_or16:233; CHECK: ; %bb.0:234; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)235; CHECK-NEXT: v_or_b32_e32 v9, 16, v14236; CHECK-NEXT: v_or_b32_e32 v11, 16, v12237; CHECK-NEXT: v_or_b32_e32 v10, 16, v10238; CHECK-NEXT: v_or_b32_e32 v8, 16, v8239; CHECK-NEXT: v_lshrrev_b64 v[0:1], v8, v[0:1]240; CHECK-NEXT: v_lshrrev_b64 v[2:3], v10, v[2:3]241; CHECK-NEXT: v_lshrrev_b64 v[4:5], v11, v[4:5]242; CHECK-NEXT: v_lshrrev_b64 v[6:7], v9, v[6:7]243; CHECK-NEXT: s_setpc_b64 s[30:31]244 %or = or <4 x i64> %shift_amt, splat (i64 16)245 %srl = lshr <4 x i64> %arg0, %or246 ret <4 x i64> %srl247}248 249; test SGPR250 251define i64 @srl_or16_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {252; CHECK-LABEL: srl_or16_sgpr:253; CHECK: ; %bb.0:254; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)255; CHECK-NEXT: s_or_b32 s4, s18, 16256; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4257; CHECK-NEXT: v_mov_b32_e32 v0, s4258; CHECK-NEXT: v_mov_b32_e32 v1, s5259; CHECK-NEXT: s_setpc_b64 s[30:31]260 %or = or i64 %shift_amt, 16261 %srl = lshr i64 %arg0, %or262 ret i64 %srl263}264 265define amdgpu_ps i64 @srl_or16_sgpr_return(i64 inreg %arg0, i64 inreg %shift_amt) {266; CHECK-LABEL: srl_or16_sgpr_return:267; CHECK: ; %bb.0:268; CHECK-NEXT: s_or_b32 s2, s2, 16269; CHECK-NEXT: s_lshr_b64 s[0:1], s[0:1], s2270; CHECK-NEXT: ; return to shader part epilog271 %or = or i64 %shift_amt, 16272 %srl = lshr i64 %arg0, %or273 ret i64 %srl274}275 276define <2 x i64> @srl_v2_or16_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {277; CHECK-LABEL: srl_v2_or16_sgpr:278; CHECK: ; %bb.0:279; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)280; CHECK-NEXT: s_or_b32 s6, s22, 16281; CHECK-NEXT: s_or_b32 s4, s20, 16282; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4283; CHECK-NEXT: s_lshr_b64 s[6:7], s[18:19], s6284; CHECK-NEXT: v_mov_b32_e32 v0, s4285; CHECK-NEXT: v_mov_b32_e32 v1, s5286; CHECK-NEXT: v_mov_b32_e32 v2, s6287; CHECK-NEXT: v_mov_b32_e32 v3, s7288; CHECK-NEXT: s_setpc_b64 s[30:31]289 %or = or <2 x i64> %shift_amt, splat (i64 16)290 %srl = lshr <2 x i64> %arg0, %or291 ret <2 x i64> %srl292}293 294define <3 x i64> @srl_v3_or16_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {295; CHECK-LABEL: srl_v3_or16_sgpr:296; CHECK: ; %bb.0:297; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)298; CHECK-NEXT: s_or_b32 s8, s26, 16299; CHECK-NEXT: s_or_b32 s6, s24, 16300; CHECK-NEXT: s_or_b32 s4, s22, 16301; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4302; CHECK-NEXT: s_lshr_b64 s[6:7], s[18:19], s6303; CHECK-NEXT: s_lshr_b64 s[8:9], s[20:21], s8304; CHECK-NEXT: v_mov_b32_e32 v0, s4305; CHECK-NEXT: v_mov_b32_e32 v1, s5306; CHECK-NEXT: v_mov_b32_e32 v2, s6307; CHECK-NEXT: v_mov_b32_e32 v3, s7308; CHECK-NEXT: v_mov_b32_e32 v4, s8309; CHECK-NEXT: v_mov_b32_e32 v5, s9310; CHECK-NEXT: s_setpc_b64 s[30:31]311 %or = or <3 x i64> %shift_amt, splat (i64 16)312 %srl = lshr <3 x i64> %arg0, %or313 ret <3 x i64> %srl314}315 316define <4 x i64> @srl_v4_or16_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {317; CHECK-LABEL: srl_v4_or16_sgpr:318; CHECK: ; %bb.0:319; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)320; CHECK-NEXT: v_or_b32_e32 v0, 16, v0321; CHECK-NEXT: s_or_b32 s8, s28, 16322; CHECK-NEXT: s_or_b32 s6, s26, 16323; CHECK-NEXT: s_or_b32 s4, s24, 16324; CHECK-NEXT: s_lshr_b64 s[4:5], s[16:17], s4325; CHECK-NEXT: s_lshr_b64 s[6:7], s[18:19], s6326; CHECK-NEXT: s_lshr_b64 s[8:9], s[20:21], s8327; CHECK-NEXT: v_lshrrev_b64 v[6:7], v0, s[22:23]328; CHECK-NEXT: v_mov_b32_e32 v0, s4329; CHECK-NEXT: v_mov_b32_e32 v1, s5330; CHECK-NEXT: v_mov_b32_e32 v2, s6331; CHECK-NEXT: v_mov_b32_e32 v3, s7332; CHECK-NEXT: v_mov_b32_e32 v4, s8333; CHECK-NEXT: v_mov_b32_e32 v5, s9334; CHECK-NEXT: s_setpc_b64 s[30:31]335 %or = or <4 x i64> %shift_amt, splat (i64 16)336 %srl = lshr <4 x i64> %arg0, %or337 ret <4 x i64> %srl338}339 340;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;341; Test range with an "or X, 32"342;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;343 344; These cases are reduced because computeKnownBits() can calculate a minimum of 32345; based on the OR with 32.346 347define i64 @srl_or32(i64 %arg0, i64 %shift_amt) {348; CHECK-LABEL: srl_or32:349; CHECK: ; %bb.0:350; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)351; CHECK-NEXT: v_lshrrev_b32_e32 v0, v2, v1352; CHECK-NEXT: v_mov_b32_e32 v1, 0353; CHECK-NEXT: s_setpc_b64 s[30:31]354 %or = or i64 %shift_amt, 32355 %srl = lshr i64 %arg0, %or356 ret i64 %srl357}358 359define <2 x i64> @srl_v2_or32(<2 x i64> %arg0, <2 x i64> %shift_amt) {360; CHECK-LABEL: srl_v2_or32:361; CHECK: ; %bb.0:362; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)363; CHECK-NEXT: v_lshrrev_b32_e32 v0, v4, v1364; CHECK-NEXT: v_lshrrev_b32_e32 v2, v6, v3365; CHECK-NEXT: v_mov_b32_e32 v1, 0366; CHECK-NEXT: v_mov_b32_e32 v3, 0367; CHECK-NEXT: s_setpc_b64 s[30:31]368 %or = or <2 x i64> %shift_amt, splat (i64 32)369 %srl = lshr <2 x i64> %arg0, %or370 ret <2 x i64> %srl371}372 373define <3 x i64> @srl_v3_or32(<3 x i64> %arg0, <3 x i64> %shift_amt) {374; CHECK-LABEL: srl_v3_or32:375; CHECK: ; %bb.0:376; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)377; CHECK-NEXT: v_lshrrev_b32_e32 v0, v6, v1378; CHECK-NEXT: v_lshrrev_b32_e32 v2, v8, v3379; CHECK-NEXT: v_lshrrev_b32_e32 v4, v10, v5380; CHECK-NEXT: v_mov_b32_e32 v1, 0381; CHECK-NEXT: v_mov_b32_e32 v3, 0382; CHECK-NEXT: v_mov_b32_e32 v5, 0383; CHECK-NEXT: s_setpc_b64 s[30:31]384 %or = or <3 x i64> %shift_amt, splat (i64 32)385 %srl = lshr <3 x i64> %arg0, %or386 ret <3 x i64> %srl387}388 389define <4 x i64> @srl_v4_or32(<4 x i64> %arg0, <4 x i64> %shift_amt) {390; CHECK-LABEL: srl_v4_or32:391; CHECK: ; %bb.0:392; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)393; CHECK-NEXT: v_lshrrev_b32_e32 v0, v8, v1394; CHECK-NEXT: v_lshrrev_b32_e32 v2, v10, v3395; CHECK-NEXT: v_lshrrev_b32_e32 v4, v12, v5396; CHECK-NEXT: v_lshrrev_b32_e32 v6, v14, v7397; CHECK-NEXT: v_mov_b32_e32 v1, 0398; CHECK-NEXT: v_mov_b32_e32 v3, 0399; CHECK-NEXT: v_mov_b32_e32 v5, 0400; CHECK-NEXT: v_mov_b32_e32 v7, 0401; CHECK-NEXT: s_setpc_b64 s[30:31]402 %or = or <4 x i64> %shift_amt, splat (i64 32)403 %srl = lshr <4 x i64> %arg0, %or404 ret <4 x i64> %srl405}406 407; test SGPR408 409define i64 @srl_or32_sgpr(i64 inreg %arg0, i64 inreg %shift_amt) {410; CHECK-LABEL: srl_or32_sgpr:411; CHECK: ; %bb.0:412; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)413; CHECK-NEXT: s_lshr_b32 s4, s17, s18414; CHECK-NEXT: v_mov_b32_e32 v0, s4415; CHECK-NEXT: v_mov_b32_e32 v1, 0416; CHECK-NEXT: s_setpc_b64 s[30:31]417 %or = or i64 %shift_amt, 32418 %srl = lshr i64 %arg0, %or419 ret i64 %srl420}421 422define amdgpu_ps i64 @srl_or32_sgpr_return(i64 inreg %arg0, i64 inreg %shift_amt) {423; CHECK-LABEL: srl_or32_sgpr_return:424; CHECK: ; %bb.0:425; CHECK-NEXT: s_lshr_b32 s0, s1, s2426; CHECK-NEXT: s_mov_b32 s1, 0427; CHECK-NEXT: ; return to shader part epilog428 %or = or i64 %shift_amt, 32429 %srl = lshr i64 %arg0, %or430 ret i64 %srl431}432 433define <2 x i64> @srl_v2_or32_sgpr(<2 x i64> inreg %arg0, <2 x i64> inreg %shift_amt) {434; CHECK-LABEL: srl_v2_or32_sgpr:435; CHECK: ; %bb.0:436; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)437; CHECK-NEXT: s_lshr_b32 s4, s17, s20438; CHECK-NEXT: s_lshr_b32 s5, s19, s22439; CHECK-NEXT: v_mov_b32_e32 v0, s4440; CHECK-NEXT: v_mov_b32_e32 v1, 0441; CHECK-NEXT: v_mov_b32_e32 v2, s5442; CHECK-NEXT: v_mov_b32_e32 v3, 0443; CHECK-NEXT: s_setpc_b64 s[30:31]444 %or = or <2 x i64> %shift_amt, splat (i64 32)445 %srl = lshr <2 x i64> %arg0, %or446 ret <2 x i64> %srl447}448 449define <3 x i64> @srl_v3_or32_sgpr(<3 x i64> inreg %arg0, <3 x i64> inreg %shift_amt) {450; CHECK-LABEL: srl_v3_or32_sgpr:451; CHECK: ; %bb.0:452; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)453; CHECK-NEXT: s_lshr_b32 s4, s17, s22454; CHECK-NEXT: s_lshr_b32 s5, s19, s24455; CHECK-NEXT: s_lshr_b32 s6, s21, s26456; CHECK-NEXT: v_mov_b32_e32 v0, s4457; CHECK-NEXT: v_mov_b32_e32 v1, 0458; CHECK-NEXT: v_mov_b32_e32 v2, s5459; CHECK-NEXT: v_mov_b32_e32 v3, 0460; CHECK-NEXT: v_mov_b32_e32 v4, s6461; CHECK-NEXT: v_mov_b32_e32 v5, 0462; CHECK-NEXT: s_setpc_b64 s[30:31]463 %or = or <3 x i64> %shift_amt, splat (i64 32)464 %srl = lshr <3 x i64> %arg0, %or465 ret <3 x i64> %srl466}467 468define <4 x i64> @srl_v4_or32_sgpr(<4 x i64> inreg %arg0, <4 x i64> inreg %shift_amt) {469; CHECK-LABEL: srl_v4_or32_sgpr:470; CHECK: ; %bb.0:471; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)472; CHECK-NEXT: s_lshr_b32 s4, s17, s24473; CHECK-NEXT: s_lshr_b32 s5, s19, s26474; CHECK-NEXT: s_lshr_b32 s6, s21, s28475; CHECK-NEXT: v_lshrrev_b32_e64 v6, v0, s23476; CHECK-NEXT: v_mov_b32_e32 v0, s4477; CHECK-NEXT: v_mov_b32_e32 v1, 0478; CHECK-NEXT: v_mov_b32_e32 v2, s5479; CHECK-NEXT: v_mov_b32_e32 v3, 0480; CHECK-NEXT: v_mov_b32_e32 v4, s6481; CHECK-NEXT: v_mov_b32_e32 v5, 0482; CHECK-NEXT: v_mov_b32_e32 v7, 0483; CHECK-NEXT: s_setpc_b64 s[30:31]484 %or = or <4 x i64> %shift_amt, splat (i64 32)485 %srl = lshr <4 x i64> %arg0, %or486 ret <4 x i64> %srl487}488 489;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;490; Test range from max/min491;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;492 493; FIXME: This case should be reduced too, but computeKnownBits() cannot494; determine the range. Match current results for now.495 496define i64 @srl_maxmin(i64 %arg0, i64 noundef %arg1) {497; CHECK-LABEL: srl_maxmin:498; CHECK: ; %bb.0:499; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)500; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[2:3]501; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc502; CHECK-NEXT: v_cndmask_b32_e32 v2, 32, v2, vcc503; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[2:3]504; CHECK-NEXT: v_cndmask_b32_e32 v2, 63, v2, vcc505; CHECK-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]506; CHECK-NEXT: s_setpc_b64 s[30:31]507 %max = call i64 @llvm.umax.i64(i64 %arg1, i64 32)508 %min = call i64 @llvm.umin.i64(i64 %max, i64 63)509 %srl = lshr i64 %arg0, %min510 ret i64 %srl511}512 513define <2 x i64> @srl_v2_maxmin(<2 x i64> %arg0, <2 x i64> noundef %arg1) {514; CHECK-LABEL: srl_v2_maxmin:515; CHECK: ; %bb.0:516; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)517; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[4:5]518; CHECK-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc519; CHECK-NEXT: v_cndmask_b32_e32 v4, 32, v4, vcc520; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]521; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc522; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc523; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]524; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc525; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[4:5]526; CHECK-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]527; CHECK-NEXT: v_cndmask_b32_e32 v4, 63, v4, vcc528; CHECK-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]529; CHECK-NEXT: s_setpc_b64 s[30:31]530 %max = call <2 x i64> @llvm.umax.i64(<2 x i64> %arg1, <2 x i64> splat (i64 32))531 %min = call <2 x i64> @llvm.umin.i64(<2 x i64> %max, <2 x i64> splat (i64 63))532 %srl = lshr <2 x i64> %arg0, %min533 ret <2 x i64> %srl534}535 536define <3 x i64> @srl_v3_maxmin(<3 x i64> %arg0, <3 x i64> noundef %arg1) {537; CHECK-LABEL: srl_v3_maxmin:538; CHECK: ; %bb.0:539; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)540; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[6:7]541; CHECK-NEXT: v_cndmask_b32_e32 v7, 0, v7, vcc542; CHECK-NEXT: v_cndmask_b32_e32 v6, 32, v6, vcc543; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]544; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc545; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc546; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]547; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc548; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc549; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]550; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc551; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]552; CHECK-NEXT: v_lshrrev_b64 v[4:5], v10, v[4:5]553; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc554; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[6:7]555; CHECK-NEXT: v_lshrrev_b64 v[2:3], v8, v[2:3]556; CHECK-NEXT: v_cndmask_b32_e32 v6, 63, v6, vcc557; CHECK-NEXT: v_lshrrev_b64 v[0:1], v6, v[0:1]558; CHECK-NEXT: s_setpc_b64 s[30:31]559 %max = call <3 x i64> @llvm.umax.i64(<3 x i64> %arg1, <3 x i64> splat (i64 32))560 %min = call <3 x i64> @llvm.umin.i64(<3 x i64> %max, <3 x i64> splat (i64 63))561 %srl = lshr <3 x i64> %arg0, %min562 ret <3 x i64> %srl563}564 565define <4 x i64> @srl_v4_maxmin(<4 x i64> %arg0, <4 x i64> noundef %arg1) {566; CHECK-LABEL: srl_v4_maxmin:567; CHECK: ; %bb.0:568; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)569; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[8:9]570; CHECK-NEXT: v_cndmask_b32_e32 v9, 0, v9, vcc571; CHECK-NEXT: v_cndmask_b32_e32 v8, 32, v8, vcc572; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[10:11]573; CHECK-NEXT: v_cndmask_b32_e32 v11, 0, v11, vcc574; CHECK-NEXT: v_cndmask_b32_e32 v10, 32, v10, vcc575; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[12:13]576; CHECK-NEXT: v_cndmask_b32_e32 v13, 0, v13, vcc577; CHECK-NEXT: v_cndmask_b32_e32 v12, 32, v12, vcc578; CHECK-NEXT: v_cmp_lt_u64_e32 vcc, 32, v[14:15]579; CHECK-NEXT: v_cndmask_b32_e32 v15, 0, v15, vcc580; CHECK-NEXT: v_cndmask_b32_e32 v14, 32, v14, vcc581; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[14:15]582; CHECK-NEXT: v_cndmask_b32_e32 v14, 63, v14, vcc583; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[12:13]584; CHECK-NEXT: v_lshrrev_b64 v[6:7], v14, v[6:7]585; CHECK-NEXT: v_cndmask_b32_e32 v12, 63, v12, vcc586; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[10:11]587; CHECK-NEXT: v_lshrrev_b64 v[4:5], v12, v[4:5]588; CHECK-NEXT: v_cndmask_b32_e32 v10, 63, v10, vcc589; CHECK-NEXT: v_cmp_gt_u64_e32 vcc, 63, v[8:9]590; CHECK-NEXT: v_lshrrev_b64 v[2:3], v10, v[2:3]591; CHECK-NEXT: v_cndmask_b32_e32 v8, 63, v8, vcc592; CHECK-NEXT: v_lshrrev_b64 v[0:1], v8, v[0:1]593; CHECK-NEXT: s_setpc_b64 s[30:31]594 %max = call <4 x i64> @llvm.umax.i64(<4 x i64> %arg1, <4 x i64> splat (i64 32))595 %min = call <4 x i64> @llvm.umin.i64(<4 x i64> %max, <4 x i64> splat (i64 63))596 %srl = lshr <4 x i64> %arg0, %min597 ret <4 x i64> %srl598}599