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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s8 9define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {10; GFX6-LABEL: v_ssubsat_i8:11; GFX6: ; %bb.0:12; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 814; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 815; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v116; GFX6-NEXT: s_movk_i32 s4, 0xff8017; GFX6-NEXT: v_mov_b32_e32 v1, 0x7f18; GFX6-NEXT: v_med3_i32 v0, v0, s4, v119; GFX6-NEXT: s_setpc_b64 s[30:31]20;21; GFX8-LABEL: v_ssubsat_i8:22; GFX8: ; %bb.0:23; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)24; GFX8-NEXT: v_sub_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_025; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v026; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v027; GFX8-NEXT: s_setpc_b64 s[30:31]28;29; GFX9-LABEL: v_ssubsat_i8:30; GFX9: ; %bb.0:31; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v133; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v034; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp35; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v036; GFX9-NEXT: s_setpc_b64 s[30:31]37;38; GFX10-LABEL: v_ssubsat_i8:39; GFX10: ; %bb.0:40; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GFX10-NEXT: v_lshlrev_b16 v1, 8, v142; GFX10-NEXT: v_lshlrev_b16 v0, 8, v043; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp44; GFX10-NEXT: v_ashrrev_i16 v0, 8, v045; GFX10-NEXT: s_setpc_b64 s[30:31]46;47; GFX11-TRUE16-LABEL: v_ssubsat_i8:48; GFX11-TRUE16: ; %bb.0:49; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l51; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l52; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, v0.l, v0.h clamp53; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v0.l54; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]55;56; GFX11-FAKE16-LABEL: v_ssubsat_i8:57; GFX11-FAKE16: ; %bb.0:58; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)59; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v160; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 8, v061; GFX11-FAKE16-NEXT: v_sub_nc_i16 v0, v0, v1 clamp62; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, 8, v063; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]64 %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)65 ret i8 %result66}67 68define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {69; GFX6-LABEL: v_ssubsat_i16:70; GFX6: ; %bb.0:71; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 1673; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1674; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v175; GFX6-NEXT: s_movk_i32 s4, 0x800076; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fff77; GFX6-NEXT: v_med3_i32 v0, v0, s4, v178; GFX6-NEXT: s_setpc_b64 s[30:31]79;80; GFX8-LABEL: v_ssubsat_i16:81; GFX8: ; %bb.0:82; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v184; GFX8-NEXT: v_sub_u16_e32 v1, v0, v185; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v086; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v187; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v088; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]89; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc90; GFX8-NEXT: s_setpc_b64 s[30:31]91;92; GFX9-LABEL: v_ssubsat_i16:93; GFX9: ; %bb.0:94; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp96; GFX9-NEXT: s_setpc_b64 s[30:31]97;98; GFX10-LABEL: v_ssubsat_i16:99; GFX10: ; %bb.0:100; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)101; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp102; GFX10-NEXT: s_setpc_b64 s[30:31]103;104; GFX11-TRUE16-LABEL: v_ssubsat_i16:105; GFX11-TRUE16: ; %bb.0:106; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)107; GFX11-TRUE16-NEXT: v_sub_nc_i16 v0.l, v0.l, v1.l clamp108; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]109;110; GFX11-FAKE16-LABEL: v_ssubsat_i16:111; GFX11-FAKE16: ; %bb.0:112; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; GFX11-FAKE16-NEXT: v_sub_nc_i16 v0, v0, v1 clamp114; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]115 %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)116 ret i16 %result117}118 119define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) {120; GFX6-LABEL: v_ssubsat_i32:121; GFX6: ; %bb.0:122; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)123; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1124; GFX6-NEXT: v_sub_i32_e64 v1, s[4:5], v0, v1125; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0126; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v1127; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]128; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5]129; GFX6-NEXT: s_setpc_b64 s[30:31]130;131; GFX8-LABEL: v_ssubsat_i32:132; GFX8: ; %bb.0:133; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)134; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1135; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v0, v1136; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0137; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v1138; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]139; GFX8-NEXT: v_cndmask_b32_e64 v0, v1, -v0, s[4:5]140; GFX8-NEXT: s_setpc_b64 s[30:31]141;142; GFX9-LABEL: v_ssubsat_i32:143; GFX9: ; %bb.0:144; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp146; GFX9-NEXT: s_setpc_b64 s[30:31]147;148; GFX10PLUS-LABEL: v_ssubsat_i32:149; GFX10PLUS: ; %bb.0:150; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v1 clamp152; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]153 %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)154 ret i32 %result155}156 157define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {158; GFX6-LABEL: v_ssubsat_v2i16:159; GFX6: ; %bb.0:160; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)161; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16162; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16163; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16164; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16165; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3166; GFX6-NEXT: s_movk_i32 s4, 0x8000167; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fff168; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2169; GFX6-NEXT: v_med3_i32 v1, v1, s4, v3170; GFX6-NEXT: v_med3_i32 v0, v0, s4, v3171; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v1172; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0173; GFX6-NEXT: v_or_b32_e32 v0, v0, v4174; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1175; GFX6-NEXT: s_setpc_b64 s[30:31]176;177; GFX8-LABEL: v_ssubsat_v2i16:178; GFX8: ; %bb.0:179; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)180; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1181; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0182; GFX8-NEXT: v_sub_u16_e32 v4, v3, v2183; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3184; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2185; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v4186; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2187; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc188; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc189; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1190; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1191; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0192; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1193; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0194; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]195; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2196; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc197; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD198; GFX8-NEXT: s_setpc_b64 s[30:31]199;200; GFX9-LABEL: v_ssubsat_v2i16:201; GFX9: ; %bb.0:202; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)203; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp204; GFX9-NEXT: s_setpc_b64 s[30:31]205;206; GFX10PLUS-LABEL: v_ssubsat_v2i16:207; GFX10PLUS: ; %bb.0:208; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v1 clamp210; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]211 %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)212 ret <2 x i16> %result213}214 215define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {216; GFX6-LABEL: v_ssubsat_v3i16:217; GFX6: ; %bb.0:218; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)219; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16220; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16221; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16222; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16223; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16224; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16225; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4226; GFX6-NEXT: s_movk_i32 s4, 0x8000227; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fff228; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3229; GFX6-NEXT: v_med3_i32 v1, v1, s4, v4230; GFX6-NEXT: v_med3_i32 v0, v0, s4, v4231; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5232; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1233; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0234; GFX6-NEXT: v_med3_i32 v3, v2, s4, v4235; GFX6-NEXT: v_or_b32_e32 v0, v0, v1236; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3237; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16238; GFX6-NEXT: s_setpc_b64 s[30:31]239;240; GFX8-LABEL: v_ssubsat_v3i16:241; GFX8: ; %bb.0:242; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)243; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2244; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0245; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4246; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5247; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4248; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6249; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4250; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc251; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc252; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3253; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3254; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1255; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3256; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1257; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]258; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc259; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2260; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2261; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0262; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2263; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0264; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]265; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc266; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4267; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD268; GFX8-NEXT: s_setpc_b64 s[30:31]269;270; GFX9-LABEL: v_ssubsat_v3i16:271; GFX9: ; %bb.0:272; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)273; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp274; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp275; GFX9-NEXT: s_setpc_b64 s[30:31]276;277; GFX10PLUS-LABEL: v_ssubsat_v3i16:278; GFX10PLUS: ; %bb.0:279; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)280; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v2 clamp281; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v3 clamp282; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]283 %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)284 ret <3 x i16> %result285}286 287define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {288; GFX6-LABEL: v_ssubsat_v4i16:289; GFX6: ; %bb.0:290; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)291; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16292; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16293; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16294; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16295; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5296; GFX6-NEXT: s_movk_i32 s4, 0x8000297; GFX6-NEXT: v_mov_b32_e32 v5, 0x7fff298; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4299; GFX6-NEXT: v_med3_i32 v1, v1, s4, v5300; GFX6-NEXT: v_med3_i32 v0, v0, s4, v5301; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16302; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16303; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16304; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16305; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1306; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0307; GFX6-NEXT: v_or_b32_e32 v0, v0, v1308; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v3, v7309; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6310; GFX6-NEXT: v_med3_i32 v1, v1, s4, v5311; GFX6-NEXT: v_med3_i32 v2, v2, s4, v5312; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1313; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2314; GFX6-NEXT: v_or_b32_e32 v1, v2, v1315; GFX6-NEXT: s_setpc_b64 s[30:31]316;317; GFX8-LABEL: v_ssubsat_v4i16:318; GFX8: ; %bb.0:319; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)320; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2321; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0322; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4323; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5324; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4325; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6326; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4327; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc328; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc329; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2330; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2331; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0332; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2333; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0334; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]335; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4336; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc337; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD338; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3339; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1340; GFX8-NEXT: v_sub_u16_e32 v5, v4, v2341; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4342; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2343; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v5344; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2345; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc346; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc347; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3348; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3349; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1350; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3351; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1352; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]353; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2354; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc355; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD356; GFX8-NEXT: s_setpc_b64 s[30:31]357;358; GFX9-LABEL: v_ssubsat_v4i16:359; GFX9: ; %bb.0:360; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)361; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp362; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp363; GFX9-NEXT: s_setpc_b64 s[30:31]364;365; GFX10PLUS-LABEL: v_ssubsat_v4i16:366; GFX10PLUS: ; %bb.0:367; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v2 clamp369; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v3 clamp370; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]371 %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)372 %cast = bitcast <4 x i16> %result to <2 x float>373 ret <2 x float> %cast374}375 376define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {377; GFX6-LABEL: v_ssubsat_v2i32:378; GFX6: ; %bb.0:379; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)380; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2381; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v0, v2382; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0383; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2384; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]385; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5]386; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3387; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3388; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1389; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2390; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]391; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5]392; GFX6-NEXT: s_setpc_b64 s[30:31]393;394; GFX8-LABEL: v_ssubsat_v2i32:395; GFX8: ; %bb.0:396; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)397; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2398; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v0, v2399; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0400; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2401; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]402; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -v0, s[4:5]403; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v1, v3404; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3405; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1406; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2407; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]408; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, -v1, s[4:5]409; GFX8-NEXT: s_setpc_b64 s[30:31]410;411; GFX9-LABEL: v_ssubsat_v2i32:412; GFX9: ; %bb.0:413; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)414; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp415; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp416; GFX9-NEXT: s_setpc_b64 s[30:31]417;418; GFX10PLUS-LABEL: v_ssubsat_v2i32:419; GFX10PLUS: ; %bb.0:420; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)421; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v2 clamp422; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v3 clamp423; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]424 %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)425 ret <2 x i32> %result426}427 428define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {429; GFX6-LABEL: v_ssubsat_v3i32:430; GFX6: ; %bb.0:431; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3433; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v3434; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0435; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3436; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]437; GFX6-NEXT: v_cndmask_b32_e64 v0, v3, -v0, s[4:5]438; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v4439; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4440; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1441; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v3442; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]443; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -v1, s[4:5]444; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v2, v5445; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5446; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2447; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v3448; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]449; GFX6-NEXT: v_cndmask_b32_e64 v2, v3, -v2, s[4:5]450; GFX6-NEXT: s_setpc_b64 s[30:31]451;452; GFX8-LABEL: v_ssubsat_v3i32:453; GFX8: ; %bb.0:454; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)455; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3456; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v0, v3457; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0458; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3459; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]460; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, -v0, s[4:5]461; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v1, v4462; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4463; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1464; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v3465; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]466; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, -v1, s[4:5]467; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v2, v5468; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5469; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2470; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v3471; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]472; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, -v2, s[4:5]473; GFX8-NEXT: s_setpc_b64 s[30:31]474;475; GFX9-LABEL: v_ssubsat_v3i32:476; GFX9: ; %bb.0:477; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)478; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp479; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp480; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp481; GFX9-NEXT: s_setpc_b64 s[30:31]482;483; GFX10PLUS-LABEL: v_ssubsat_v3i32:484; GFX10PLUS: ; %bb.0:485; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)486; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v3 clamp487; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v4 clamp488; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v5 clamp489; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]490 %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)491 ret <3 x i32> %result492}493 494define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {495; GFX6-LABEL: v_ssubsat_v4i32:496; GFX6: ; %bb.0:497; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)498; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4499; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v0, v4500; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0501; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v4502; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]503; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, -v0, s[4:5]504; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v1, v5505; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5506; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1507; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v4508; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]509; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, -v1, s[4:5]510; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v2, v6511; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6512; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2513; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v4514; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]515; GFX6-NEXT: v_cndmask_b32_e64 v2, v4, -v2, s[4:5]516; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v7517; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7518; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3519; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v4520; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]521; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, -v3, s[4:5]522; GFX6-NEXT: s_setpc_b64 s[30:31]523;524; GFX8-LABEL: v_ssubsat_v4i32:525; GFX8: ; %bb.0:526; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)527; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4528; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v0, v4529; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0530; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v4531; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]532; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, -v0, s[4:5]533; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v1, v5534; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5535; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1536; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v4537; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]538; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, -v1, s[4:5]539; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v2, v6540; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6541; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2542; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v4543; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]544; GFX8-NEXT: v_cndmask_b32_e64 v2, v4, -v2, s[4:5]545; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v7546; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7547; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3548; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v4549; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]550; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, -v3, s[4:5]551; GFX8-NEXT: s_setpc_b64 s[30:31]552;553; GFX9-LABEL: v_ssubsat_v4i32:554; GFX9: ; %bb.0:555; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)556; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp557; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp558; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp559; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp560; GFX9-NEXT: s_setpc_b64 s[30:31]561;562; GFX10PLUS-LABEL: v_ssubsat_v4i32:563; GFX10PLUS: ; %bb.0:564; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v4 clamp566; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v5 clamp567; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v6 clamp568; GFX10PLUS-NEXT: v_sub_nc_i32 v3, v3, v7 clamp569; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]570 %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)571 ret <4 x i32> %result572}573 574define <8 x i32> @v_ssubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) {575; GFX6-LABEL: v_ssubsat_v8i32:576; GFX6: ; %bb.0:577; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)578; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8579; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v8580; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0581; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v8582; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]583; GFX6-NEXT: v_cndmask_b32_e64 v0, v8, -v0, s[4:5]584; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v1, v9585; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9586; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1587; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v8588; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]589; GFX6-NEXT: v_cndmask_b32_e64 v1, v8, -v1, s[4:5]590; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v2, v10591; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10592; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2593; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v8594; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]595; GFX6-NEXT: v_cndmask_b32_e64 v2, v8, -v2, s[4:5]596; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v3, v11597; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11598; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3599; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v8600; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]601; GFX6-NEXT: v_cndmask_b32_e64 v3, v8, -v3, s[4:5]602; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v4, v12603; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12604; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4605; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v8606; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]607; GFX6-NEXT: v_cndmask_b32_e64 v4, v8, -v4, s[4:5]608; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v13609; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13610; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5611; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v8612; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]613; GFX6-NEXT: v_cndmask_b32_e64 v5, v8, -v5, s[4:5]614; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v14615; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14616; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6617; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v8618; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]619; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, -v6, s[4:5]620; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v15621; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15622; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7623; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v8624; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]625; GFX6-NEXT: v_cndmask_b32_e64 v7, v8, -v7, s[4:5]626; GFX6-NEXT: s_setpc_b64 s[30:31]627;628; GFX8-LABEL: v_ssubsat_v8i32:629; GFX8: ; %bb.0:630; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)631; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8632; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v0, v8633; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0634; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v8635; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]636; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, -v0, s[4:5]637; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v1, v9638; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9639; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1640; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v8641; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]642; GFX8-NEXT: v_cndmask_b32_e64 v1, v8, -v1, s[4:5]643; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v2, v10644; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10645; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2646; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v8647; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]648; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, -v2, s[4:5]649; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v3, v11650; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11651; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3652; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v8653; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]654; GFX8-NEXT: v_cndmask_b32_e64 v3, v8, -v3, s[4:5]655; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v4, v12656; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12657; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4658; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v8659; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]660; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, -v4, s[4:5]661; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v5, v13662; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13663; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5664; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v8665; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]666; GFX8-NEXT: v_cndmask_b32_e64 v5, v8, -v5, s[4:5]667; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v6, v14668; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14669; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6670; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v8671; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]672; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, -v6, s[4:5]673; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v7, v15674; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15675; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7676; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v8677; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]678; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, -v7, s[4:5]679; GFX8-NEXT: s_setpc_b64 s[30:31]680;681; GFX9-LABEL: v_ssubsat_v8i32:682; GFX9: ; %bb.0:683; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)684; GFX9-NEXT: v_sub_i32 v0, v0, v8 clamp685; GFX9-NEXT: v_sub_i32 v1, v1, v9 clamp686; GFX9-NEXT: v_sub_i32 v2, v2, v10 clamp687; GFX9-NEXT: v_sub_i32 v3, v3, v11 clamp688; GFX9-NEXT: v_sub_i32 v4, v4, v12 clamp689; GFX9-NEXT: v_sub_i32 v5, v5, v13 clamp690; GFX9-NEXT: v_sub_i32 v6, v6, v14 clamp691; GFX9-NEXT: v_sub_i32 v7, v7, v15 clamp692; GFX9-NEXT: s_setpc_b64 s[30:31]693;694; GFX10PLUS-LABEL: v_ssubsat_v8i32:695; GFX10PLUS: ; %bb.0:696; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)697; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v8 clamp698; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v9 clamp699; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v10 clamp700; GFX10PLUS-NEXT: v_sub_nc_i32 v3, v3, v11 clamp701; GFX10PLUS-NEXT: v_sub_nc_i32 v4, v4, v12 clamp702; GFX10PLUS-NEXT: v_sub_nc_i32 v5, v5, v13 clamp703; GFX10PLUS-NEXT: v_sub_nc_i32 v6, v6, v14 clamp704; GFX10PLUS-NEXT: v_sub_nc_i32 v7, v7, v15 clamp705; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]706 %result = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs)707 ret <8 x i32> %result708}709 710define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {711; GFX6-LABEL: v_ssubsat_v16i32:712; GFX6: ; %bb.0:713; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)714; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16715; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v0, v16716; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0717; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v16718; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]719; GFX6-NEXT: v_cndmask_b32_e64 v0, v16, -v0, s[4:5]720; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v1, v17721; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17722; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1723; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v16724; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]725; GFX6-NEXT: v_cndmask_b32_e64 v1, v16, -v1, s[4:5]726; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v2, v18727; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18728; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2729; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v16730; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]731; GFX6-NEXT: v_cndmask_b32_e64 v2, v16, -v2, s[4:5]732; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v3, v19733; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19734; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3735; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v16736; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]737; GFX6-NEXT: v_cndmask_b32_e64 v3, v16, -v3, s[4:5]738; GFX6-NEXT: buffer_load_dword v16, off, s[0:3], s32739; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v4, v20740; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20741; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v4742; GFX6-NEXT: v_ashrrev_i32_e32 v4, 31, v17743; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]744; GFX6-NEXT: v_cndmask_b32_e64 v4, v17, -v4, s[4:5]745; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v5, v21746; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21747; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5748; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v17749; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]750; GFX6-NEXT: v_cndmask_b32_e64 v5, v17, -v5, s[4:5]751; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v6, v22752; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22753; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6754; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v17755; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]756; GFX6-NEXT: v_cndmask_b32_e64 v6, v17, -v6, s[4:5]757; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v7, v23758; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23759; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7760; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v17761; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]762; GFX6-NEXT: v_cndmask_b32_e64 v7, v17, -v7, s[4:5]763; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v8, v24764; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24765; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8766; GFX6-NEXT: v_ashrrev_i32_e32 v8, 31, v17767; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]768; GFX6-NEXT: v_cndmask_b32_e64 v8, v17, -v8, s[4:5]769; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v9, v25770; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25771; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9772; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v17773; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]774; GFX6-NEXT: v_cndmask_b32_e64 v9, v17, -v9, s[4:5]775; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v10, v26776; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26777; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10778; GFX6-NEXT: v_ashrrev_i32_e32 v10, 31, v17779; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]780; GFX6-NEXT: v_cndmask_b32_e64 v10, v17, -v10, s[4:5]781; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v11, v27782; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27783; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11784; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v17785; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]786; GFX6-NEXT: v_cndmask_b32_e64 v11, v17, -v11, s[4:5]787; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v12, v28788; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28789; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12790; GFX6-NEXT: v_ashrrev_i32_e32 v12, 31, v17791; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]792; GFX6-NEXT: v_cndmask_b32_e64 v12, v17, -v12, s[4:5]793; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v13, v29794; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29795; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13796; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v17797; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]798; GFX6-NEXT: v_cndmask_b32_e64 v13, v17, -v13, s[4:5]799; GFX6-NEXT: v_sub_i32_e64 v17, s[4:5], v14, v30800; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30801; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14802; GFX6-NEXT: v_ashrrev_i32_e32 v14, 31, v17803; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]804; GFX6-NEXT: v_cndmask_b32_e64 v14, v17, -v14, s[4:5]805; GFX6-NEXT: s_waitcnt vmcnt(0)806; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16807; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v15, v16808; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15809; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v16810; GFX6-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]811; GFX6-NEXT: v_cndmask_b32_e64 v15, v16, -v15, s[4:5]812; GFX6-NEXT: s_setpc_b64 s[30:31]813;814; GFX8-LABEL: v_ssubsat_v16i32:815; GFX8: ; %bb.0:816; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)817; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16818; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v0, v16819; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0820; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v16821; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]822; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, -v0, s[4:5]823; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v1, v17824; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17825; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1826; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v16827; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]828; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, -v1, s[4:5]829; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v2, v18830; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18831; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2832; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v16833; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]834; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, -v2, s[4:5]835; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v3, v19836; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19837; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3838; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v16839; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]840; GFX8-NEXT: v_cndmask_b32_e64 v3, v16, -v3, s[4:5]841; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32842; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v4, v20843; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20844; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v4845; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v17846; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]847; GFX8-NEXT: v_cndmask_b32_e64 v4, v17, -v4, s[4:5]848; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v5, v21849; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21850; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v5851; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v17852; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]853; GFX8-NEXT: v_cndmask_b32_e64 v5, v17, -v5, s[4:5]854; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v6, v22855; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22856; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v6857; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v17858; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]859; GFX8-NEXT: v_cndmask_b32_e64 v6, v17, -v6, s[4:5]860; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v7, v23861; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23862; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v7863; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v17864; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]865; GFX8-NEXT: v_cndmask_b32_e64 v7, v17, -v7, s[4:5]866; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v8, v24867; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24868; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v8869; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v17870; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]871; GFX8-NEXT: v_cndmask_b32_e64 v8, v17, -v8, s[4:5]872; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v9, v25873; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25874; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v9875; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v17876; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]877; GFX8-NEXT: v_cndmask_b32_e64 v9, v17, -v9, s[4:5]878; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v10, v26879; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26880; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v10881; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v17882; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]883; GFX8-NEXT: v_cndmask_b32_e64 v10, v17, -v10, s[4:5]884; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v11, v27885; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27886; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v11887; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v17888; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]889; GFX8-NEXT: v_cndmask_b32_e64 v11, v17, -v11, s[4:5]890; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v12, v28891; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28892; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v12893; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v17894; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]895; GFX8-NEXT: v_cndmask_b32_e64 v12, v17, -v12, s[4:5]896; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v13, v29897; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29898; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v13899; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v17900; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]901; GFX8-NEXT: v_cndmask_b32_e64 v13, v17, -v13, s[4:5]902; GFX8-NEXT: v_sub_u32_e64 v17, s[4:5], v14, v30903; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30904; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v17, v14905; GFX8-NEXT: v_ashrrev_i32_e32 v14, 31, v17906; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]907; GFX8-NEXT: v_cndmask_b32_e64 v14, v17, -v14, s[4:5]908; GFX8-NEXT: s_waitcnt vmcnt(0)909; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16910; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v15, v16911; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15912; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v16913; GFX8-NEXT: s_xor_b64 s[4:5], vcc, s[4:5]914; GFX8-NEXT: v_cndmask_b32_e64 v15, v16, -v15, s[4:5]915; GFX8-NEXT: s_setpc_b64 s[30:31]916;917; GFX9-LABEL: v_ssubsat_v16i32:918; GFX9: ; %bb.0:919; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)920; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp921; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32922; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp923; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp924; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp925; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp926; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp927; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp928; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp929; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp930; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp931; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp932; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp933; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp934; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp935; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp936; GFX9-NEXT: s_waitcnt vmcnt(0)937; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp938; GFX9-NEXT: s_setpc_b64 s[30:31]939;940; GFX10-LABEL: v_ssubsat_v16i32:941; GFX10: ; %bb.0:942; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)943; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32944; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp945; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp946; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp947; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp948; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp949; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp950; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp951; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp952; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp953; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp954; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp955; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp956; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp957; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp958; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp959; GFX10-NEXT: s_waitcnt vmcnt(0)960; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp961; GFX10-NEXT: s_setpc_b64 s[30:31]962;963; GFX11-LABEL: v_ssubsat_v16i32:964; GFX11: ; %bb.0:965; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)966; GFX11-NEXT: scratch_load_b32 v31, off, s32967; GFX11-NEXT: v_sub_nc_i32 v0, v0, v16 clamp968; GFX11-NEXT: v_sub_nc_i32 v1, v1, v17 clamp969; GFX11-NEXT: v_sub_nc_i32 v2, v2, v18 clamp970; GFX11-NEXT: v_sub_nc_i32 v3, v3, v19 clamp971; GFX11-NEXT: v_sub_nc_i32 v4, v4, v20 clamp972; GFX11-NEXT: v_sub_nc_i32 v5, v5, v21 clamp973; GFX11-NEXT: v_sub_nc_i32 v6, v6, v22 clamp974; GFX11-NEXT: v_sub_nc_i32 v7, v7, v23 clamp975; GFX11-NEXT: v_sub_nc_i32 v8, v8, v24 clamp976; GFX11-NEXT: v_sub_nc_i32 v9, v9, v25 clamp977; GFX11-NEXT: v_sub_nc_i32 v10, v10, v26 clamp978; GFX11-NEXT: v_sub_nc_i32 v11, v11, v27 clamp979; GFX11-NEXT: v_sub_nc_i32 v12, v12, v28 clamp980; GFX11-NEXT: v_sub_nc_i32 v13, v13, v29 clamp981; GFX11-NEXT: v_sub_nc_i32 v14, v14, v30 clamp982; GFX11-NEXT: s_waitcnt vmcnt(0)983; GFX11-NEXT: v_sub_nc_i32 v15, v15, v31 clamp984; GFX11-NEXT: s_setpc_b64 s[30:31]985 %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)986 ret <16 x i32> %result987}988 989 990define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {991; GFX6-LABEL: v_ssubsat_i64:992; GFX6: ; %bb.0:993; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)994; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v2995; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc996; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]997; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]998; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v5999; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc1000; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc1001; GFX6-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc1002; GFX6-NEXT: s_setpc_b64 s[30:31]1003;1004; GFX8-LABEL: v_ssubsat_i64:1005; GFX8: ; %bb.0:1006; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1007; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v21008; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc1009; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]1010; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]1011; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v51012; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc1013; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc1014; GFX8-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc1015; GFX8-NEXT: s_setpc_b64 s[30:31]1016;1017; GFX9-LABEL: v_ssubsat_i64:1018; GFX9: ; %bb.0:1019; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1020; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v21021; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc1022; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]1023; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]1024; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v51025; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc1026; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc1027; GFX9-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc1028; GFX9-NEXT: s_setpc_b64 s[30:31]1029;1030; GFX10-LABEL: v_ssubsat_i64:1031; GFX10: ; %bb.0:1032; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1033; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v21034; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo1035; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3]1036; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]1037; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v51038; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo1039; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo1040; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo1041; GFX10-NEXT: s_setpc_b64 s[30:31]1042;1043; GFX11-LABEL: v_ssubsat_i64:1044; GFX11: ; %bb.0:1045; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1046; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v21047; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, v1, v3, vcc_lo1048; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[2:3]1049; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]1050; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v51051; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo1052; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo1053; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, -v1, vcc_lo1054; GFX11-NEXT: s_setpc_b64 s[30:31]1055 %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)1056 ret i64 %result1057}1058 1059declare i8 @llvm.ssub.sat.i8(i8, i8) #01060declare i16 @llvm.ssub.sat.i16(i16, i16) #01061declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) #01062declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #01063declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) #01064declare i32 @llvm.ssub.sat.i32(i32, i32) #01065declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) #01066declare <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32>, <3 x i32>) #01067declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) #01068declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>) #01069declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) #01070declare i64 @llvm.ssub.sat.i64(i64, i64) #01071 1072attributes #0 = { nounwind readnone speculatable willreturn }1073