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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck -check-prefix=MUBUF %s3; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -mattr=+enable-flat-scratch | FileCheck -check-prefix=FLATSCR %s4; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=MUBUF11 %s5; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+enable-flat-scratch | FileCheck -check-prefix=FLATSCR11 %s6 7; During instruction selection, we use immediate const zero for soffset in8; MUBUF stack accesses and let eliminateFrameIndex to fix up this field to use9; the correct frame register whenever required.10define amdgpu_kernel void @kernel_background_evaluate(ptr addrspace(5) %kg, ptr addrspace(1) %input, ptr addrspace(1) %output, i32 %i) {11; MUBUF-LABEL: kernel_background_evaluate:12; MUBUF: ; %bb.0: ; %entry13; MUBUF-NEXT: s_load_dword s0, s[4:5], 0x2414; MUBUF-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD015; MUBUF-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD116; MUBUF-NEXT: s_mov_b32 s38, -117; MUBUF-NEXT: s_mov_b32 s39, 0x31c1600018; MUBUF-NEXT: s_add_u32 s36, s36, s1119; MUBUF-NEXT: s_addc_u32 s37, s37, 020; MUBUF-NEXT: v_mov_b32_e32 v1, 0x200021; MUBUF-NEXT: v_mov_b32_e32 v2, 0x400022; MUBUF-NEXT: v_mov_b32_e32 v3, 023; MUBUF-NEXT: v_mov_b32_e32 v4, 0x40000024; MUBUF-NEXT: s_getpc_b64 s[4:5]25; MUBUF-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+426; MUBUF-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+1227; MUBUF-NEXT: s_mov_b32 s32, 0xc000028; MUBUF-NEXT: s_waitcnt lgkmcnt(0)29; MUBUF-NEXT: v_mov_b32_e32 v0, s030; MUBUF-NEXT: s_mov_b64 s[0:1], s[36:37]31; MUBUF-NEXT: s_mov_b64 s[2:3], s[38:39]32; MUBUF-NEXT: s_swappc_b64 s[30:31], s[4:5]33; MUBUF-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v034; MUBUF-NEXT: s_and_saveexec_b32 s0, vcc_lo35; MUBUF-NEXT: s_cbranch_execz .LBB0_236; MUBUF-NEXT: ; %bb.1: ; %if.then4.i37; MUBUF-NEXT: v_mov_b32_e32 v0, 0x400438; MUBUF-NEXT: s_mov_b32 s0, 0x41c64e6d39; MUBUF-NEXT: s_clause 0x140; MUBUF-NEXT: buffer_load_dword v1, v0, s[36:39], 0 offen41; MUBUF-NEXT: buffer_load_dword v2, v0, s[36:39], 0 offen offset:442; MUBUF-NEXT: s_waitcnt vmcnt(0)43; MUBUF-NEXT: v_add_nc_u32_e32 v0, v2, v144; MUBUF-NEXT: v_mad_u64_u32 v[0:1], s0, v0, s0, 0x303945; MUBUF-NEXT: buffer_store_dword v0, v0, s[36:39], 0 offen46; MUBUF-NEXT: .LBB0_2: ; %shader_eval_surface.exit47; MUBUF-NEXT: s_endpgm48;49; FLATSCR-LABEL: kernel_background_evaluate:50; FLATSCR: ; %bb.0: ; %entry51; FLATSCR-NEXT: s_add_u32 s8, s8, s1352; FLATSCR-NEXT: s_movk_i32 s32, 0x600053; FLATSCR-NEXT: s_addc_u32 s9, s9, 054; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s855; FLATSCR-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s956; FLATSCR-NEXT: s_load_dword s2, s[4:5], 0x2457; FLATSCR-NEXT: v_mov_b32_e32 v1, 0x200058; FLATSCR-NEXT: v_mov_b32_e32 v2, 0x400059; FLATSCR-NEXT: v_mov_b32_e32 v3, 060; FLATSCR-NEXT: v_mov_b32_e32 v4, 0x40000061; FLATSCR-NEXT: s_getpc_b64 s[0:1]62; FLATSCR-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+463; FLATSCR-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+1264; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)65; FLATSCR-NEXT: v_mov_b32_e32 v0, s266; FLATSCR-NEXT: s_swappc_b64 s[30:31], s[0:1]67; FLATSCR-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v068; FLATSCR-NEXT: s_and_saveexec_b32 s0, vcc_lo69; FLATSCR-NEXT: s_cbranch_execz .LBB0_270; FLATSCR-NEXT: ; %bb.1: ; %if.then4.i71; FLATSCR-NEXT: s_movk_i32 s0, 0x400072; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 offset:473; FLATSCR-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)74; FLATSCR-NEXT: s_mov_b32 s0, 0x41c64e6d75; FLATSCR-NEXT: s_waitcnt vmcnt(0)76; FLATSCR-NEXT: v_add_nc_u32_e32 v0, v1, v077; FLATSCR-NEXT: v_mad_u64_u32 v[0:1], s0, v0, s0, 0x303978; FLATSCR-NEXT: scratch_store_dword off, v0, s079; FLATSCR-NEXT: .LBB0_2: ; %shader_eval_surface.exit80; FLATSCR-NEXT: s_endpgm81;82; MUBUF11-LABEL: kernel_background_evaluate:83; MUBUF11: ; %bb.0: ; %entry84; MUBUF11-NEXT: s_load_b32 s2, s[4:5], 0x2485; MUBUF11-NEXT: v_mov_b32_e32 v1, 0x200086; MUBUF11-NEXT: v_dual_mov_b32 v2, 0x4000 :: v_dual_mov_b32 v3, 087; MUBUF11-NEXT: v_mov_b32_e32 v4, 0x40000088; MUBUF11-NEXT: s_getpc_b64 s[0:1]89; MUBUF11-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+490; MUBUF11-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+1291; MUBUF11-NEXT: s_movk_i32 s32, 0x600092; MUBUF11-NEXT: s_waitcnt lgkmcnt(0)93; MUBUF11-NEXT: v_mov_b32_e32 v0, s294; MUBUF11-NEXT: s_swappc_b64 s[30:31], s[0:1]95; MUBUF11-NEXT: s_mov_b32 s0, exec_lo96; MUBUF11-NEXT: v_cmpx_ne_u32_e32 0, v097; MUBUF11-NEXT: s_cbranch_execz .LBB0_298; MUBUF11-NEXT: ; %bb.1: ; %if.then4.i99; MUBUF11-NEXT: s_movk_i32 s0, 0x4000100; MUBUF11-NEXT: scratch_load_b64 v[0:1], off, s0 offset:4101; MUBUF11-NEXT: s_mov_b32 s0, 0x41c64e6d102; MUBUF11-NEXT: s_waitcnt vmcnt(0)103; MUBUF11-NEXT: v_add_nc_u32_e32 v2, v1, v0104; MUBUF11-NEXT: v_mad_u64_u32 v[0:1], null, v2, s0, 0x3039105; MUBUF11-NEXT: scratch_store_b32 off, v0, s0106; MUBUF11-NEXT: .LBB0_2: ; %shader_eval_surface.exit107; MUBUF11-NEXT: s_endpgm108;109; FLATSCR11-LABEL: kernel_background_evaluate:110; FLATSCR11: ; %bb.0: ; %entry111; FLATSCR11-NEXT: s_load_b32 s2, s[4:5], 0x24112; FLATSCR11-NEXT: v_mov_b32_e32 v1, 0x2000113; FLATSCR11-NEXT: v_dual_mov_b32 v2, 0x4000 :: v_dual_mov_b32 v3, 0114; FLATSCR11-NEXT: v_mov_b32_e32 v4, 0x400000115; FLATSCR11-NEXT: s_getpc_b64 s[0:1]116; FLATSCR11-NEXT: s_add_u32 s0, s0, svm_eval_nodes@rel32@lo+4117; FLATSCR11-NEXT: s_addc_u32 s1, s1, svm_eval_nodes@rel32@hi+12118; FLATSCR11-NEXT: s_movk_i32 s32, 0x6000119; FLATSCR11-NEXT: s_waitcnt lgkmcnt(0)120; FLATSCR11-NEXT: v_mov_b32_e32 v0, s2121; FLATSCR11-NEXT: s_swappc_b64 s[30:31], s[0:1]122; FLATSCR11-NEXT: s_mov_b32 s0, exec_lo123; FLATSCR11-NEXT: v_cmpx_ne_u32_e32 0, v0124; FLATSCR11-NEXT: s_cbranch_execz .LBB0_2125; FLATSCR11-NEXT: ; %bb.1: ; %if.then4.i126; FLATSCR11-NEXT: s_movk_i32 s0, 0x4000127; FLATSCR11-NEXT: scratch_load_b64 v[0:1], off, s0 offset:4128; FLATSCR11-NEXT: s_mov_b32 s0, 0x41c64e6d129; FLATSCR11-NEXT: s_waitcnt vmcnt(0)130; FLATSCR11-NEXT: v_add_nc_u32_e32 v2, v1, v0131; FLATSCR11-NEXT: v_mad_u64_u32 v[0:1], null, v2, s0, 0x3039132; FLATSCR11-NEXT: scratch_store_b32 off, v0, s0133; FLATSCR11-NEXT: .LBB0_2: ; %shader_eval_surface.exit134; FLATSCR11-NEXT: s_endpgm135entry:136 %sd = alloca < 1339 x i32>, align 8192, addrspace(5)137 %state = alloca <4 x i32>, align 16, addrspace(5)138 %rslt = call i32 @svm_eval_nodes(ptr addrspace(5) %kg, ptr addrspace(5) %sd, ptr addrspace(5) %state, i32 0, i32 4194304)139 %cmp = icmp eq i32 %rslt, 0140 br i1 %cmp, label %shader_eval_surface.exit, label %if.then4.i141 142if.then4.i: ; preds = %entry143 %rng_hash.i.i = getelementptr inbounds < 4 x i32>, ptr addrspace(5) %state, i32 0, i32 1144 %tmp0 = load i32, ptr addrspace(5) %rng_hash.i.i, align 4145 %rng_offset.i.i = getelementptr inbounds <4 x i32>, ptr addrspace(5) %state, i32 0, i32 2146 %tmp1 = load i32, ptr addrspace(5) %rng_offset.i.i, align 4147 %add.i.i = add i32 %tmp1, %tmp0148 %add1.i.i = add i32 %add.i.i, 0149 %mul.i.i.i.i = mul i32 %add1.i.i, 1103515245150 %add.i.i.i.i = add i32 %mul.i.i.i.i, 12345151 store i32 %add.i.i.i.i, ptr addrspace(5) poison, align 16152 br label %shader_eval_surface.exit153 154shader_eval_surface.exit: ; preds = %entry155 ret void156}157 158declare hidden i32 @svm_eval_nodes(ptr addrspace(5), ptr addrspace(5), ptr addrspace(5), i32, i32) local_unnamed_addr #0159 160attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }161