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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s3 4; Make sure the stack is never realigned for entry functions.5 6define amdgpu_kernel void @max_alignment_128() #0 {7; VI-LABEL: max_alignment_128:8; VI: ; %bb.0:9; VI-NEXT: s_add_u32 s0, s0, s1710; VI-NEXT: s_addc_u32 s1, s1, 011; VI-NEXT: v_mov_b32_e32 v0, 312; VI-NEXT: buffer_store_byte v0, off, s[0:3], 013; VI-NEXT: s_waitcnt vmcnt(0)14; VI-NEXT: v_mov_b32_e32 v0, 915; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:12816; VI-NEXT: s_waitcnt vmcnt(0)17; VI-NEXT: s_endpgm18; VI-NEXT: .section .rodata,"a"19; VI-NEXT: .p2align 620; VI-NEXT: .amdhsa_kernel max_alignment_12821; VI-NEXT: .amdhsa_group_segment_fixed_size 022; VI-NEXT: .amdhsa_private_segment_fixed_size 25623; VI-NEXT: .amdhsa_kernarg_size 5624; VI-NEXT: .amdhsa_user_sgpr_count 1425; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 126; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 127; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 128; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 129; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 130; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 131; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 032; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 133; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 134; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 135; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 136; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 037; VI-NEXT: .amdhsa_system_vgpr_workitem_id 238; VI-NEXT: .amdhsa_next_free_vgpr 139; VI-NEXT: .amdhsa_next_free_sgpr 1840; VI-NEXT: .amdhsa_reserve_vcc 041; VI-NEXT: .amdhsa_reserve_flat_scratch 042; VI-NEXT: .amdhsa_float_round_mode_32 043; VI-NEXT: .amdhsa_float_round_mode_16_64 044; VI-NEXT: .amdhsa_float_denorm_mode_32 345; VI-NEXT: .amdhsa_float_denorm_mode_16_64 346; VI-NEXT: .amdhsa_dx10_clamp 147; VI-NEXT: .amdhsa_ieee_mode 148; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 049; VI-NEXT: .amdhsa_exception_fp_denorm_src 050; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 051; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 052; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 053; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 054; VI-NEXT: .amdhsa_exception_int_div_zero 055; VI-NEXT: .end_amdhsa_kernel56; VI-NEXT: .text57;58; GFX9-LABEL: max_alignment_128:59; GFX9: ; %bb.0:60; GFX9-NEXT: s_add_u32 s0, s0, s1761; GFX9-NEXT: s_addc_u32 s1, s1, 062; GFX9-NEXT: v_mov_b32_e32 v0, 363; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], 064; GFX9-NEXT: s_waitcnt vmcnt(0)65; GFX9-NEXT: v_mov_b32_e32 v0, 966; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:12867; GFX9-NEXT: s_waitcnt vmcnt(0)68; GFX9-NEXT: s_endpgm69; GFX9-NEXT: .section .rodata,"a"70; GFX9-NEXT: .p2align 671; GFX9-NEXT: .amdhsa_kernel max_alignment_12872; GFX9-NEXT: .amdhsa_group_segment_fixed_size 073; GFX9-NEXT: .amdhsa_private_segment_fixed_size 25674; GFX9-NEXT: .amdhsa_kernarg_size 5675; GFX9-NEXT: .amdhsa_user_sgpr_count 1476; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 177; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 178; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 179; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 180; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 181; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 182; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 083; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 184; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 185; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 186; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 187; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 088; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 289; GFX9-NEXT: .amdhsa_next_free_vgpr 190; GFX9-NEXT: .amdhsa_next_free_sgpr 1891; GFX9-NEXT: .amdhsa_reserve_vcc 092; GFX9-NEXT: .amdhsa_reserve_flat_scratch 093; GFX9-NEXT: .amdhsa_reserve_xnack_mask 194; GFX9-NEXT: .amdhsa_float_round_mode_32 095; GFX9-NEXT: .amdhsa_float_round_mode_16_64 096; GFX9-NEXT: .amdhsa_float_denorm_mode_32 397; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 398; GFX9-NEXT: .amdhsa_dx10_clamp 199; GFX9-NEXT: .amdhsa_ieee_mode 1100; GFX9-NEXT: .amdhsa_fp16_overflow 0101; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0102; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0103; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0104; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0105; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0106; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0107; GFX9-NEXT: .amdhsa_exception_int_div_zero 0108; GFX9-NEXT: .end_amdhsa_kernel109; GFX9-NEXT: .text110 %clutter = alloca i8, addrspace(5) ; Force non-zero offset for next alloca111 store volatile i8 3, ptr addrspace(5) %clutter112 %alloca.align = alloca i32, align 128, addrspace(5)113 store volatile i32 9, ptr addrspace(5) %alloca.align, align 128114 ret void115}116 117define amdgpu_kernel void @stackrealign_attr() #1 {118; VI-LABEL: stackrealign_attr:119; VI: ; %bb.0:120; VI-NEXT: s_add_u32 s0, s0, s17121; VI-NEXT: s_addc_u32 s1, s1, 0122; VI-NEXT: v_mov_b32_e32 v0, 3123; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0124; VI-NEXT: s_waitcnt vmcnt(0)125; VI-NEXT: v_mov_b32_e32 v0, 9126; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4127; VI-NEXT: s_waitcnt vmcnt(0)128; VI-NEXT: s_endpgm129; VI-NEXT: .section .rodata,"a"130; VI-NEXT: .p2align 6131; VI-NEXT: .amdhsa_kernel stackrealign_attr132; VI-NEXT: .amdhsa_group_segment_fixed_size 0133; VI-NEXT: .amdhsa_private_segment_fixed_size 12134; VI-NEXT: .amdhsa_kernarg_size 56135; VI-NEXT: .amdhsa_user_sgpr_count 14136; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1137; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1138; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 1139; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1140; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 1141; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1142; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0143; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1144; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1145; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1146; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1147; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0148; VI-NEXT: .amdhsa_system_vgpr_workitem_id 2149; VI-NEXT: .amdhsa_next_free_vgpr 1150; VI-NEXT: .amdhsa_next_free_sgpr 18151; VI-NEXT: .amdhsa_reserve_vcc 0152; VI-NEXT: .amdhsa_reserve_flat_scratch 0153; VI-NEXT: .amdhsa_float_round_mode_32 0154; VI-NEXT: .amdhsa_float_round_mode_16_64 0155; VI-NEXT: .amdhsa_float_denorm_mode_32 3156; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3157; VI-NEXT: .amdhsa_dx10_clamp 1158; VI-NEXT: .amdhsa_ieee_mode 1159; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0160; VI-NEXT: .amdhsa_exception_fp_denorm_src 0161; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0162; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0163; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0164; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0165; VI-NEXT: .amdhsa_exception_int_div_zero 0166; VI-NEXT: .end_amdhsa_kernel167; VI-NEXT: .text168;169; GFX9-LABEL: stackrealign_attr:170; GFX9: ; %bb.0:171; GFX9-NEXT: s_add_u32 s0, s0, s17172; GFX9-NEXT: s_addc_u32 s1, s1, 0173; GFX9-NEXT: v_mov_b32_e32 v0, 3174; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], 0175; GFX9-NEXT: s_waitcnt vmcnt(0)176; GFX9-NEXT: v_mov_b32_e32 v0, 9177; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4178; GFX9-NEXT: s_waitcnt vmcnt(0)179; GFX9-NEXT: s_endpgm180; GFX9-NEXT: .section .rodata,"a"181; GFX9-NEXT: .p2align 6182; GFX9-NEXT: .amdhsa_kernel stackrealign_attr183; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0184; GFX9-NEXT: .amdhsa_private_segment_fixed_size 12185; GFX9-NEXT: .amdhsa_kernarg_size 56186; GFX9-NEXT: .amdhsa_user_sgpr_count 14187; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1188; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1189; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 1190; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1191; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 1192; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1193; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0194; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1195; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1196; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1197; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1198; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0199; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 2200; GFX9-NEXT: .amdhsa_next_free_vgpr 1201; GFX9-NEXT: .amdhsa_next_free_sgpr 18202; GFX9-NEXT: .amdhsa_reserve_vcc 0203; GFX9-NEXT: .amdhsa_reserve_flat_scratch 0204; GFX9-NEXT: .amdhsa_reserve_xnack_mask 1205; GFX9-NEXT: .amdhsa_float_round_mode_32 0206; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0207; GFX9-NEXT: .amdhsa_float_denorm_mode_32 3208; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3209; GFX9-NEXT: .amdhsa_dx10_clamp 1210; GFX9-NEXT: .amdhsa_ieee_mode 1211; GFX9-NEXT: .amdhsa_fp16_overflow 0212; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0213; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0214; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0215; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0216; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0217; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0218; GFX9-NEXT: .amdhsa_exception_int_div_zero 0219; GFX9-NEXT: .end_amdhsa_kernel220; GFX9-NEXT: .text221 %clutter = alloca i8, addrspace(5) ; Force non-zero offset for next alloca222 store volatile i8 3, ptr addrspace(5) %clutter223 %alloca.align = alloca i32, align 4, addrspace(5)224 store volatile i32 9, ptr addrspace(5) %alloca.align, align 4225 ret void226}227 228define amdgpu_kernel void @alignstack_attr() #2 {229; VI-LABEL: alignstack_attr:230; VI: ; %bb.0:231; VI-NEXT: s_add_u32 s0, s0, s17232; VI-NEXT: s_addc_u32 s1, s1, 0233; VI-NEXT: v_mov_b32_e32 v0, 3234; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0235; VI-NEXT: s_waitcnt vmcnt(0)236; VI-NEXT: v_mov_b32_e32 v0, 9237; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4238; VI-NEXT: s_waitcnt vmcnt(0)239; VI-NEXT: s_endpgm240; VI-NEXT: .section .rodata,"a"241; VI-NEXT: .p2align 6242; VI-NEXT: .amdhsa_kernel alignstack_attr243; VI-NEXT: .amdhsa_group_segment_fixed_size 0244; VI-NEXT: .amdhsa_private_segment_fixed_size 128245; VI-NEXT: .amdhsa_kernarg_size 56246; VI-NEXT: .amdhsa_user_sgpr_count 14247; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1248; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1249; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 1250; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1251; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 1252; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1253; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0254; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1255; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1256; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1257; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1258; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0259; VI-NEXT: .amdhsa_system_vgpr_workitem_id 2260; VI-NEXT: .amdhsa_next_free_vgpr 1261; VI-NEXT: .amdhsa_next_free_sgpr 18262; VI-NEXT: .amdhsa_reserve_vcc 0263; VI-NEXT: .amdhsa_reserve_flat_scratch 0264; VI-NEXT: .amdhsa_float_round_mode_32 0265; VI-NEXT: .amdhsa_float_round_mode_16_64 0266; VI-NEXT: .amdhsa_float_denorm_mode_32 3267; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3268; VI-NEXT: .amdhsa_dx10_clamp 1269; VI-NEXT: .amdhsa_ieee_mode 1270; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0271; VI-NEXT: .amdhsa_exception_fp_denorm_src 0272; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0273; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0274; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0275; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0276; VI-NEXT: .amdhsa_exception_int_div_zero 0277; VI-NEXT: .end_amdhsa_kernel278; VI-NEXT: .text279;280; GFX9-LABEL: alignstack_attr:281; GFX9: ; %bb.0:282; GFX9-NEXT: s_add_u32 s0, s0, s17283; GFX9-NEXT: s_addc_u32 s1, s1, 0284; GFX9-NEXT: v_mov_b32_e32 v0, 3285; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], 0286; GFX9-NEXT: s_waitcnt vmcnt(0)287; GFX9-NEXT: v_mov_b32_e32 v0, 9288; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4289; GFX9-NEXT: s_waitcnt vmcnt(0)290; GFX9-NEXT: s_endpgm291; GFX9-NEXT: .section .rodata,"a"292; GFX9-NEXT: .p2align 6293; GFX9-NEXT: .amdhsa_kernel alignstack_attr294; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0295; GFX9-NEXT: .amdhsa_private_segment_fixed_size 128296; GFX9-NEXT: .amdhsa_kernarg_size 56297; GFX9-NEXT: .amdhsa_user_sgpr_count 14298; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1299; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1300; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 1301; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1302; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 1303; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1304; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0305; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1306; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1307; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1308; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1309; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0310; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 2311; GFX9-NEXT: .amdhsa_next_free_vgpr 1312; GFX9-NEXT: .amdhsa_next_free_sgpr 18313; GFX9-NEXT: .amdhsa_reserve_vcc 0314; GFX9-NEXT: .amdhsa_reserve_flat_scratch 0315; GFX9-NEXT: .amdhsa_reserve_xnack_mask 1316; GFX9-NEXT: .amdhsa_float_round_mode_32 0317; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0318; GFX9-NEXT: .amdhsa_float_denorm_mode_32 3319; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3320; GFX9-NEXT: .amdhsa_dx10_clamp 1321; GFX9-NEXT: .amdhsa_ieee_mode 1322; GFX9-NEXT: .amdhsa_fp16_overflow 0323; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0324; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0325; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0326; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0327; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0328; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0329; GFX9-NEXT: .amdhsa_exception_int_div_zero 0330; GFX9-NEXT: .end_amdhsa_kernel331; GFX9-NEXT: .text332 %clutter = alloca i8, addrspace(5) ; Force non-zero offset for next alloca333 store volatile i8 3, ptr addrspace(5) %clutter334 %alloca.align = alloca i32, align 4, addrspace(5)335 store volatile i32 9, ptr addrspace(5) %alloca.align, align 4336 ret void337}338 339attributes #0 = { nounwind }340attributes #1 = { nounwind "stackrealign" }341attributes #2 = { nounwind alignstack=128 }342 343!llvm.module.flags = !{!0}344!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}345