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1# Note we are NOT using the normal register allocator pipeline. We are2# forcing allocating VGPRs and SGPRs at the same time.3# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -stress-regalloc=1 -run-pass=greedy,virtregrewriter,stack-slot-coloring -o - %s | FileCheck %s4 5---6 7# CHECK-LABEL: name: no_merge_sgpr_vgpr_spill_slot{{$}}8# CHECK: stack:9# CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,10# CHECK-NEXT: stack-id: sgpr-spill,11 12# CHECK: SI_SPILL_S32_SAVE killed renamable $sgpr5, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s32) into %stack.0, addrspace 5)13# CHECK: renamable $sgpr5 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s32) from %stack.0, addrspace 5)14 15name: no_merge_sgpr_vgpr_spill_slot16tracksRegLiveness: true17machineFunctionInfo:18 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr319 frameOffsetReg: $sgpr420 stackPtrOffsetReg: $sgpr3221body: |22 bb.0:23 %2:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, implicit $flat_scr, implicit $exec24 %0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, implicit $flat_scr, implicit $exec25 S_NOP 0, implicit %026 %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 027 %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 028 S_NOP 0, implicit %129...30