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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes=early-tailduplication -o - %s | FileCheck %s4 5---6name: stop_duplicate_cfg_intrinsic7tracksRegLiveness: true8body: |9 ; CHECK-LABEL: name: stop_duplicate_cfg_intrinsic10 ; CHECK: bb.0:11 ; CHECK-NEXT: successors: %bb.1(0x80000000)12 ; CHECK-NEXT: liveins: $vgpr013 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr015 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF16 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 017 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]18 ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec19 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: bb.1:21 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)22 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[S_MOV_B32_]], %bb.0, %6, %bb.324 ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec25 ; CHECK-NEXT: S_BRANCH %bb.326 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: bb.2:28 ; CHECK-NEXT: successors: %bb.3(0x80000000)29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec31 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 132 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]33 ; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[PHI]], [[COPY2]], 0, implicit $exec34 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: bb.3:36 ; CHECK-NEXT: successors: %bb.1(0x80000000)37 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[V_ADD_CO_U32_e64_]], %bb.2, [[PHI]], %bb.139 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 429496729540 ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 6144041 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub142 ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[DEF]], %subreg.sub0_sub1, [[REG_SEQUENCE]], %subreg.sub2_sub343 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET [[PHI1]], [[REG_SEQUENCE1]], 0, 0, 0, 0, implicit $exec44 ; CHECK-NEXT: S_BRANCH %bb.145 bb.1:46 liveins: $vgpr047 48 %0:vgpr_32 = COPY $vgpr049 %12:sreg_64 = IMPLICIT_DEF50 %4:sreg_32 = S_MOV_B32 051 %14:vgpr_32 = COPY %4:sreg_3252 %5:sreg_64_xexec = V_CMP_EQ_U32_e64 %0:vgpr_32, %14:vgpr_32, implicit $exec53 54 bb.2:55 %6:vgpr_32 = PHI %4:sreg_32, %bb.1, %11:vgpr_32, %bb.456 %8:sreg_64_xexec = SI_IF %5:sreg_64_xexec, %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec57 S_BRANCH %bb.458 59 bb.3:60 SI_END_CF %8:sreg_64_xexec, implicit-def $exec, implicit-def $scc, implicit $exec61 %13:sreg_32 = S_MOV_B32 162 %15:vgpr_32 = COPY %13:sreg_3263 %10:vgpr_32, dead %20:sreg_64_xexec = V_ADD_CO_U32_e64 %6:vgpr_32, %15:vgpr_32, 0, implicit $exec64 65 bb.4:66 %11:vgpr_32 = PHI %10:vgpr_32, %bb.3, %6:vgpr_32, %bb.267 %16:sreg_32 = S_MOV_B32 429496729568 %17:sreg_32 = S_MOV_B32 6144069 %18:sreg_64 = REG_SEQUENCE %16:sreg_32, %subreg.sub0, %17:sreg_32, %subreg.sub170 %19:sgpr_128 = REG_SEQUENCE %12:sreg_64, %subreg.sub0_sub1, %18:sreg_64, %subreg.sub2_sub371 BUFFER_STORE_DWORD_OFFSET %11:vgpr_32, %19:sgpr_128, 0, 0, 0, 0, implicit $exec72 S_BRANCH %bb.273 74...75