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1; RUN: llc -mtriple=amdgcn -mattr=+load-store-opt -enable-misched < %s | FileCheck %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+load-store-opt -enable-misched < %s | FileCheck %s3 4; This test is for a bug in the machine scheduler where stores without5; an underlying object would be moved across the barrier. In this6; test, the <2 x i8> store will be split into two i8 stores, so they7; won't have an underlying object.8 9; CHECK-LABEL: {{^}}test:10; CHECK: ds_write_b811; CHECK: ds_write_b812; CHECK: s_barrier13; CHECK: s_endpgm14; Function Attrs: nounwind15define amdgpu_kernel void @test(ptr addrspace(3) nocapture %arg, ptr addrspace(1) nocapture readonly %arg1, ptr addrspace(1) nocapture readonly %arg2, ptr addrspace(1) nocapture %arg3, i32 %arg4, i64 %tmp9) #0 {16bb:17 %tmp10 = getelementptr inbounds i32, ptr addrspace(1) %arg2, i64 %tmp918 %tmp13 = load i32, ptr addrspace(1) %tmp10, align 219 %tmp14 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp1320 %tmp15 = load <2 x i8>, ptr addrspace(3) %tmp14, align 121 %tmp16 = add i32 %tmp13, 122 %tmp17 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp1623 store <2 x i8> %tmp15, ptr addrspace(3) %tmp17, align 124 tail call void @llvm.amdgcn.s.barrier()25 %tmp25 = load i32, ptr addrspace(1) %tmp10, align 426 %tmp26 = sext i32 %tmp25 to i6427 %tmp27 = sext i32 %arg4 to i6428 %tmp28 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp25, i32 %arg429 %tmp29 = load i8, ptr addrspace(3) %tmp28, align 130 %tmp30 = getelementptr inbounds <2 x i8>, ptr addrspace(1) %arg3, i64 %tmp26, i64 %tmp2731 store i8 %tmp29, ptr addrspace(1) %tmp30, align 132 %tmp32 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp25, i32 033 %tmp33 = load i8, ptr addrspace(3) %tmp32, align 134 %tmp35 = getelementptr inbounds <2 x i8>, ptr addrspace(1) %arg3, i64 %tmp26, i64 035 store i8 %tmp33, ptr addrspace(1) %tmp35, align 136 ret void37}38 39; Function Attrs: convergent nounwind40declare void @llvm.amdgcn.s.barrier() #141 42attributes #0 = { nounwind }43attributes #1 = { convergent nounwind }44