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1; RUN: opt -S -mtriple=amdgcn-amd-amdhsa --amdgpu-annotate-uniform < %s | FileCheck -check-prefix=OPT %s2 3; "load vaddr" depends on the store, so we should not mark vaddr as amdgpu.noclobber.4 5; OPT-LABEL: @store_clobbers_load(6; OPT: %zero = load <4 x i32>, ptr addrspace(1) %input, align 16{{$}}7define amdgpu_kernel void @store_clobbers_load(ptr addrspace(1) %input, ptr addrspace(1) %out, i32 %index) {8entry:9 store i32 0, ptr addrspace(1) %input10 %zero = load <4 x i32>, ptr addrspace(1) %input, align 1611 %one = insertelement <4 x i32> %zero, i32 1, i32 112 %two = insertelement <4 x i32> %one, i32 2, i32 213 %three = insertelement <4 x i32> %two, i32 3, i32 314 store <4 x i32> %three, ptr addrspace(1) %input, align 1615 %rslt = extractelement <4 x i32> %three, i32 %index16 store i32 %rslt, ptr addrspace(1) %out, align 417 ret void18}19 20 21declare i32 @llvm.amdgcn.workitem.id.x()22@lds0 = addrspace(3) global [512 x i32] poison, align 423 24; To check that %arrayidx0 is not marked as amdgpu.noclobber.25 26; OPT-LABEL: @atomicrmw_clobbers_load(27; OPT: %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.028; OPT-NEXT: %val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst29 30define amdgpu_kernel void @atomicrmw_clobbers_load(ptr addrspace(1) %out0, ptr addrspace(1) %out1) {31 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #132 %idx.0 = add nsw i32 %tid.x, 233 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.034 %val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst35 %load = load i32, ptr addrspace(3) %arrayidx0, align 436 store i32 %val, ptr addrspace(1) %out0, align 437 store i32 %load, ptr addrspace(1) %out1, align 438 ret void39}40