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1; RUN: llc -mtriple=amdgcn-- -mcpu=verde < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=SIVI -check-prefix=VI -check-prefix=FUNC %s3; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=FUNC %s4; RUN: llc -mtriple=r600-- -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s5; RUN: llc -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s6 7; FUNC-LABEL: {{^}}store_i1:8; EG: MEM_RAT MSKOR9; EG-NOT: MEM_RAT MSKOR10 11; CM: MEM_RAT MSKOR12; CM-NOT: MEM_RAT MSKOR13 14; SIVI: buffer_store_byte15; GFX9: global_store_byte16define amdgpu_kernel void @store_i1(ptr addrspace(1) %out) {17entry:18 store i1 true, ptr addrspace(1) %out19 ret void20}21 22; i8 store23; FUNC-LABEL: {{^}}store_i8:24; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X25; EG-NOT: MEM_RAT MSKOR26 27; EG: VTX_READ_828; EG: AND_INT29; EG: AND_INT30; EG: LSHL31; EG: LSHL32; EG: LSHL33 34; SIVI: buffer_store_byte35; GFX9: global_store_byte36define amdgpu_kernel void @store_i8(ptr addrspace(1) %out, i8 %in) {37entry:38 store i8 %in, ptr addrspace(1) %out39 ret void40}41 42; i16 store43; FUNC-LABEL: {{^}}store_i16:44; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X45; EG-NOT: MEM_RAT MSKOR46 47; EG: VTX_READ_1648; EG: AND_INT49; EG: AND_INT50; EG: LSHL51; EG: LSHL52; EG: LSHL53 54 55; SIVI: buffer_store_short56; GFX9: global_store_short57define amdgpu_kernel void @store_i16(ptr addrspace(1) %out, i16 %in) {58entry:59 store i16 %in, ptr addrspace(1) %out60 ret void61}62 63; FUNC-LABEL: {{^}}store_i24:64; SIVI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1665; SIVI-DAG: buffer_store_byte66; SIVI-DAG: buffer_store_short67 68; GFX9-DAG: global_store_byte_d16_hi v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:269; GFX9-DAG: global_store_short70 71; EG: MEM_RAT MSKOR72; EG: MEM_RAT MSKOR73define amdgpu_kernel void @store_i24(ptr addrspace(1) %out, i24 %in) {74entry:75 store i24 %in, ptr addrspace(1) %out76 ret void77}78 79; FUNC-LABEL: {{^}}store_i25:80; GCN: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}}81; GCN: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]82; SIVI: buffer_store_dword [[VAND]]83; GFX9: global_store_dword v{{[0-9]+}}, [[VAND]], s84 85; EG: MEM_RAT_CACHELESS STORE_RAW86; EG-NOT: MEM_RAT87 88; CM: MEM_RAT_CACHELESS STORE_DWORD89; CM-NOT: MEM_RAT90define amdgpu_kernel void @store_i25(ptr addrspace(1) %out, i25 %in) {91entry:92 store i25 %in, ptr addrspace(1) %out93 ret void94}95 96; FUNC-LABEL: {{^}}store_v2i8:97; v2i8 is naturally 2B aligned98; EG: MEM_RAT MSKOR99; EG-NOT: MEM_RAT MSKOR100 101; CM: MEM_RAT MSKOR102; CM-NOT: MEM_RAT MSKOR103 104; SIVI: buffer_store_short105; GFX9: global_store_short106define amdgpu_kernel void @store_v2i8(ptr addrspace(1) %out, <2 x i32> %in) {107entry:108 %0 = trunc <2 x i32> %in to <2 x i8>109 store <2 x i8> %0, ptr addrspace(1) %out110 ret void111}112 113; FUNC-LABEL: {{^}}store_v2i8_unaligned:114; EG: MEM_RAT MSKOR115; EG: MEM_RAT MSKOR116; EG-NOT: MEM_RAT MSKOR117 118; CM: MEM_RAT MSKOR119; CM: MEM_RAT MSKOR120; CM-NOT: MEM_RAT MSKOR121 122; SI: buffer_store_byte123define amdgpu_kernel void @store_v2i8_unaligned(ptr addrspace(1) %out, <2 x i32> %in) {124entry:125 %0 = trunc <2 x i32> %in to <2 x i8>126 store <2 x i8> %0, ptr addrspace(1) %out, align 1127 ret void128}129 130 131; FUNC-LABEL: {{^}}store_v2i16:132; EG: MEM_RAT_CACHELESS STORE_RAW133 134; CM: MEM_RAT_CACHELESS STORE_DWORD135 136; SIVI: buffer_store_dword137; GFX9: global_store_dword138define amdgpu_kernel void @store_v2i16(ptr addrspace(1) %out, <2 x i32> %in) {139entry:140 %0 = trunc <2 x i32> %in to <2 x i16>141 store <2 x i16> %0, ptr addrspace(1) %out142 ret void143}144 145; FUNC-LABEL: {{^}}store_v2i16_unaligned:146; EG: MEM_RAT MSKOR147; EG: MEM_RAT MSKOR148; EG-NOT: MEM_RAT MSKOR149; EG-NOT: MEM_RAT_CACHELESS STORE_RAW150 151; CM: MEM_RAT MSKOR152; CM: MEM_RAT MSKOR153; CM-NOT: MEM_RAT MSKOR154; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD155 156; SIVI: buffer_store_short157; SIVI: buffer_store_short158 159; GFX9: global_store_short160; GFX9: global_store_short161define amdgpu_kernel void @store_v2i16_unaligned(ptr addrspace(1) %out, <2 x i32> %in) {162entry:163 %0 = trunc <2 x i32> %in to <2 x i16>164 store <2 x i16> %0, ptr addrspace(1) %out, align 2165 ret void166}167 168; FUNC-LABEL: {{^}}store_v4i8:169; EG: MEM_RAT_CACHELESS STORE_RAW170 171; CM: MEM_RAT_CACHELESS STORE_DWORD172 173; SIVI: buffer_store_dword174; GFX9: global_store_dword175define amdgpu_kernel void @store_v4i8(ptr addrspace(1) %out, <4 x i32> %in) {176entry:177 %0 = trunc <4 x i32> %in to <4 x i8>178 store <4 x i8> %0, ptr addrspace(1) %out179 ret void180}181 182; FUNC-LABEL: {{^}}store_v4i8_unaligned:183; EG: MEM_RAT MSKOR184; EG: MEM_RAT MSKOR185; EG: MEM_RAT MSKOR186; EG: MEM_RAT MSKOR187; EG-NOT: MEM_RAT MSKOR188; EG-NOT: MEM_RAT_CACHELESS STORE_RAW189 190; CM: MEM_RAT MSKOR191; CM: MEM_RAT MSKOR192; CM: MEM_RAT MSKOR193; CM: MEM_RAT MSKOR194; CM-NOT: MEM_RAT MSKOR195; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD196 197; SI: buffer_store_byte198; SI: buffer_store_byte199; SI: buffer_store_byte200; SI: buffer_store_byte201; SI-NOT: buffer_store_dword202define amdgpu_kernel void @store_v4i8_unaligned(ptr addrspace(1) %out, <4 x i32> %in) {203entry:204 %0 = trunc <4 x i32> %in to <4 x i8>205 store <4 x i8> %0, ptr addrspace(1) %out, align 1206 ret void207}208 209; FUNC-LABEL: {{^}}store_v4i8_halfaligned:210; EG: MEM_RAT MSKOR211; EG: MEM_RAT MSKOR212; EG-NOT: MEM_RAT MSKOR213; EG-NOT: MEM_RAT_CACHELESS STORE_RAW214 215; CM: MEM_RAT MSKOR216; CM: MEM_RAT MSKOR217; CM-NOT: MEM_RAT MSKOR218; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD219 220; SI: buffer_store_short221; SI: buffer_store_short222; SI-NOT: buffer_store_dword223define amdgpu_kernel void @store_v4i8_halfaligned(ptr addrspace(1) %out, <4 x i32> %in) {224entry:225 %0 = trunc <4 x i32> %in to <4 x i8>226 store <4 x i8> %0, ptr addrspace(1) %out, align 2227 ret void228}229 230; floating-point store231; FUNC-LABEL: {{^}}store_f32:232; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1233 234; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}235 236; SIVI: buffer_store_dword237; GFX9: global_store_dword238 239define amdgpu_kernel void @store_f32(ptr addrspace(1) %out, float %in) {240 store float %in, ptr addrspace(1) %out241 ret void242}243 244; FUNC-LABEL: {{^}}store_v4i16:245; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY246 247; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}248 249; SIVI: buffer_store_dwordx2250; GFX9: global_store_dwordx2251define amdgpu_kernel void @store_v4i16(ptr addrspace(1) %out, <4 x i32> %in) {252entry:253 %0 = trunc <4 x i32> %in to <4 x i16>254 store <4 x i16> %0, ptr addrspace(1) %out255 ret void256}257 258; vec2 floating-point stores259; FUNC-LABEL: {{^}}store_v2f32:260; EG: MEM_RAT_CACHELESS STORE_RAW261 262; CM: MEM_RAT_CACHELESS STORE_DWORD263 264; SIVI: buffer_store_dwordx2265; GFX9: global_store_dwordx2266 267define amdgpu_kernel void @store_v2f32(ptr addrspace(1) %out, float %a, float %b) {268entry:269 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0270 %1 = insertelement <2 x float> %0, float %b, i32 1271 store <2 x float> %1, ptr addrspace(1) %out272 ret void273}274 275; FUNC-LABEL: {{^}}store_v3i32:276; SI-DAG: buffer_store_dword v277; SI-DAG: buffer_store_dwordx2278 279; VI: buffer_store_dwordx3280 281; GFX9: global_store_dwordx3282 283; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}},284; EG-DAG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XY}}, {{T[0-9]+\.[XYZW]}},285define amdgpu_kernel void @store_v3i32(ptr addrspace(1) %out, <3 x i32> %a) nounwind {286 store <3 x i32> %a, ptr addrspace(1) %out, align 16287 ret void288}289 290; FUNC-LABEL: {{^}}store_v4i32:291; EG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XYZW}}292; EG-NOT: MEM_RAT_CACHELESS STORE_RAW293 294; CM: MEM_RAT_CACHELESS STORE_DWORD295; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD296 297; SIVI: buffer_store_dwordx4298; GFX9: global_store_dwordx4299define amdgpu_kernel void @store_v4i32(ptr addrspace(1) %out, <4 x i32> %in) {300entry:301 store <4 x i32> %in, ptr addrspace(1) %out302 ret void303}304 305; FUNC-LABEL: {{^}}store_v4i32_unaligned:306; EG: MEM_RAT_CACHELESS STORE_RAW {{T[0-9]+\.XYZW}}307; EG-NOT: MEM_RAT_CACHELESS STORE_RAW308 309; CM: MEM_RAT_CACHELESS STORE_DWORD310; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD311 312; SIVI: buffer_store_dwordx4313; GFX9: global_store_dwordx4314define amdgpu_kernel void @store_v4i32_unaligned(ptr addrspace(1) %out, <4 x i32> %in) {315entry:316 store <4 x i32> %in, ptr addrspace(1) %out, align 4317 ret void318}319 320; v4f32 store321; FUNC-LABEL: {{^}}store_v4f32:322; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1323; EG-NOT: MEM_RAT_CACHELESS STORE_RAW324 325; CM: MEM_RAT_CACHELESS STORE_DWORD326; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD327 328; SIVI: buffer_store_dwordx4329; GFX9: global_store_dwordx4330define amdgpu_kernel void @store_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {331 %1 = load <4 x float>, ptr addrspace(1) %in332 store <4 x float> %1, ptr addrspace(1) %out333 ret void334}335 336; FUNC-LABEL: {{^}}store_i64_i8:337; EG: MEM_RAT MSKOR338 339; CM: MEM_RAT MSKOR340 341; SIVI: buffer_store_byte342; GFX9: global_store_byte343define amdgpu_kernel void @store_i64_i8(ptr addrspace(1) %out, i64 %in) {344entry:345 %0 = trunc i64 %in to i8346 store i8 %0, ptr addrspace(1) %out347 ret void348}349 350; FUNC-LABEL: {{^}}store_i64_i16:351; EG: MEM_RAT MSKOR352; SIVI: buffer_store_short353; GFX9: global_store_short354define amdgpu_kernel void @store_i64_i16(ptr addrspace(1) %out, i64 %in) {355entry:356 %0 = trunc i64 %in to i16357 store i16 %0, ptr addrspace(1) %out358 ret void359}360 361; The stores in this function are combined by the optimizer to create a362; 64-bit store with 32-bit alignment. This is legal and the legalizer363; should not try to split the 64-bit store back into 2 32-bit stores.364 365; FUNC-LABEL: {{^}}vecload2:366; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XY, T[0-9]+\.X}}, 1367; EG-NOT: MEM_RAT_CACHELESS STORE_RAW368 369; CM: MEM_RAT_CACHELESS STORE_DWORD370; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD371 372; SIVI: buffer_store_dwordx2373; GFX9: global_store_dwordx2374define amdgpu_kernel void @vecload2(ptr addrspace(1) nocapture %out, ptr addrspace(4) nocapture %mem) #0 {375entry:376 %0 = load i32, ptr addrspace(4) %mem, align 4377 %arrayidx1.i = getelementptr inbounds i32, ptr addrspace(4) %mem, i64 1378 %1 = load i32, ptr addrspace(4) %arrayidx1.i, align 4379 store i32 %0, ptr addrspace(1) %out, align 4380 %arrayidx1 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 1381 store i32 %1, ptr addrspace(1) %arrayidx1, align 4382 ret void383}384 385; When i128 was a legal type this program generated cannot select errors:386 387; FUNC-LABEL: {{^}}"i128-const-store":388; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 1389 390; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}, T{{[0-9]+}}.X391 392; SIVI: buffer_store_dwordx4393; GFX9: global_store_dwordx4394define amdgpu_kernel void @i128-const-store(ptr addrspace(1) %out) {395entry:396 store i32 1, ptr addrspace(1) %out, align 4397 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 1398 store i32 1, ptr addrspace(1) %arrayidx2, align 4399 %arrayidx4 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 2400 store i32 2, ptr addrspace(1) %arrayidx4, align 4401 %arrayidx6 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 3402 store i32 2, ptr addrspace(1) %arrayidx6, align 4403 ret void404}405 406attributes #0 = { nounwind }407