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1; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s3; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s4; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s5 6; FUNC-LABEL: {{^}}store_i1:7; EG: MOVA_INT8; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,9; EG: MOVA_INT10; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,11 12; CM: MOVA_INT13; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,14; CM: MOVA_INT15; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,16 17; SI: buffer_store_byte18define amdgpu_kernel void @store_i1(ptr addrspace(5) %out) {19entry:20 store i1 true, ptr addrspace(5) %out21 ret void22}23 24; i8 store25; FUNC-LABEL: {{^}}store_i8:26; EG: LSHR * [[ADDRESS:T[0-9]\.[XYZW]]], KC0[2].Y, literal.x27; EG-NEXT: 228; EG: MOVA_INT * AR.x (MASKED)29; EG: MOV [[OLD:T[0-9]\.[XYZW]]], {{.*}}AR.x30 31; IG 0: Get the byte index and truncate the value32; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x33; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x34; EG-NEXT: 3(4.203895e-45)35 36 37; EG: LSHL * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], literal.x, PV.W38; EG-NEXT: 255(3.573311e-43)39 40; EG: NOT_INT41; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]]42; EG: OR_INT * [[RES:T[0-9]\.[XYZW]]]43; TODO: Is the reload necessary?44; EG: MOVA_INT * AR.x (MASKED), [[ADDRESS]]45; EG: MOV * T(0 + AR.x).X+, [[RES]]46 47; SI: buffer_store_byte48 49define amdgpu_kernel void @store_i8(ptr addrspace(5) %out, i8 %in) {50entry:51 store i8 %in, ptr addrspace(5) %out52 ret void53}54 55; i16 store56; FUNC-LABEL: {{^}}store_i16:57; EG: LSHR * [[ADDRESS:T[0-9]\.[XYZW]]], KC0[2].Y, literal.x58; EG-NEXT: 259; EG: MOVA_INT * AR.x (MASKED)60; EG: MOV [[OLD:T[0-9]\.[XYZW]]], {{.*}}AR.x61 62; EG: VTX_READ_1663 64; IG 0: Get the byte index and truncate the value65; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x66; EG: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x67; EG-NEXT: 3(4.203895e-45)68 69; EG: NOT_INT70; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]]71; EG: OR_INT * [[RES:T[0-9]\.[XYZW]]]72; TODO: Is the reload necessary?73; EG: MOVA_INT * AR.x (MASKED), [[ADDRESS]]74; EG: MOV * T(0 + AR.x).X+, [[RES]]75 76; SI: buffer_store_short77define amdgpu_kernel void @store_i16(ptr addrspace(5) %out, i16 %in) {78entry:79 store i16 %in, ptr addrspace(5) %out80 ret void81}82 83; FUNC-LABEL: {{^}}store_i24:84; SI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1685; SI-DAG: buffer_store_byte86; SI-DAG: buffer_store_short87 88; EG: MOVA_INT89; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,90; EG: MOVA_INT91; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,92; TODO: This load and store can be eliminated93; EG: MOVA_INT94; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,95; EG: MOVA_INT96; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,97 98; CM: MOVA_INT99; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,100; CM: MOVA_INT101; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,102; TODO: This load and store can be eliminated103; CM: MOVA_INT104; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,105; CM: MOVA_INT106; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,107define amdgpu_kernel void @store_i24(ptr addrspace(5) %out, i24 %in) {108entry:109 store i24 %in, ptr addrspace(5) %out110 ret void111}112 113; FUNC-LABEL: {{^}}store_i25:114; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}}115; SI: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]116; SI: buffer_store_dword [[VAND]]117 118; EG: MOVA_INT119; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,120; EG-NOT: MOVA_INT121 122; CM: MOVA_INT123; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,124; CM-NOT: MOVA_INT125define amdgpu_kernel void @store_i25(ptr addrspace(5) %out, i25 %in) {126entry:127 store i25 %in, ptr addrspace(5) %out128 ret void129}130 131; FUNC-LABEL: {{^}}store_v2i8:132; v2i8 is naturally 2B aligned, treat as i16133; EG: MOVA_INT134; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,135; EG: MOVA_INT136; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,137; EG-NOT: MOVA_INT138 139; CM: MOVA_INT140; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,141; CM: MOVA_INT142; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,143; CM-NOT: MOVA_INT144 145; SI: buffer_store_short146define amdgpu_kernel void @store_v2i8(ptr addrspace(5) %out, <2 x i32> %in) {147entry:148 %0 = trunc <2 x i32> %in to <2 x i8>149 store <2 x i8> %0, ptr addrspace(5) %out150 ret void151}152 153; FUNC-LABEL: {{^}}store_v2i8_unaligned:154; EG: MOVA_INT155; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,156; EG: MOVA_INT157; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,158; TODO: This load and store cannot be eliminated,159; they might be different locations160; EG: MOVA_INT161; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,162; EG: MOVA_INT163; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,164 165; CM: MOVA_INT166; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,167; CM: MOVA_INT168; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,169; TODO: This load and store cannot be eliminated,170; they might be different locations171; CM: MOVA_INT172; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,173; CM: MOVA_INT174; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,175 176; SI: buffer_store_byte177define amdgpu_kernel void @store_v2i8_unaligned(ptr addrspace(5) %out, <2 x i32> %in) {178entry:179 %0 = trunc <2 x i32> %in to <2 x i8>180 store <2 x i8> %0, ptr addrspace(5) %out, align 1181 ret void182}183 184 185; FUNC-LABEL: {{^}}store_v2i16:186; v2i8 is naturally 2B aligned, treat as i16187; EG: MOVA_INT188; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,189; EG-NOT: MOVA_INT190 191; CM: MOVA_INT192; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,193; CM-NOT: MOVA_INT194 195; SI: buffer_store_dword196define amdgpu_kernel void @store_v2i16(ptr addrspace(5) %out, <2 x i32> %in) {197entry:198 %0 = trunc <2 x i32> %in to <2 x i16>199 store <2 x i16> %0, ptr addrspace(5) %out200 ret void201}202 203; FUNC-LABEL: {{^}}store_v2i16_unaligned:204; EG: MOVA_INT205; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,206; EG: MOVA_INT207; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,208; TODO: This load and store cannot be eliminated,209; they might be different locations210; EG: MOVA_INT211; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,212; EG: MOVA_INT213; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,214 215; CM: MOVA_INT216; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,217; CM: MOVA_INT218; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,219; TODO: This load and store cannot be eliminated,220; they might be different locations221; CM: MOVA_INT222; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,223; CM: MOVA_INT224; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,225 226; SI: buffer_store_short227; SI: buffer_store_short228define amdgpu_kernel void @store_v2i16_unaligned(ptr addrspace(5) %out, <2 x i32> %in) {229entry:230 %0 = trunc <2 x i32> %in to <2 x i16>231 store <2 x i16> %0, ptr addrspace(5) %out, align 2232 ret void233}234 235; FUNC-LABEL: {{^}}store_v4i8:236; EG: MOVA_INT237; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,238; EG-NOT: MOVA_INT239 240; CM: MOVA_INT241; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,242; CM-NOT: MOVA_INT243 244; SI: buffer_store_dword245define amdgpu_kernel void @store_v4i8(ptr addrspace(5) %out, <4 x i32> %in) {246entry:247 %0 = trunc <4 x i32> %in to <4 x i8>248 store <4 x i8> %0, ptr addrspace(5) %out249 ret void250}251 252; FUNC-LABEL: {{^}}store_v4i8_unaligned:253; EG: MOVA_INT254; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,255; EG: MOVA_INT256; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,257; TODO: This load and store cannot be eliminated,258; they might be different locations259; EG: MOVA_INT260; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,261; EG: MOVA_INT262; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,263; TODO: This load and store cannot be eliminated,264; they might be different locations265; EG: MOVA_INT266; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,267; EG: MOVA_INT268; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,269; TODO: This load and store cannot be eliminated,270; they might be different locations271; EG: MOVA_INT272; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,273; EG: MOVA_INT274; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,275 276; CM: MOVA_INT277; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,278; CM: MOVA_INT279; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,280; TODO: This load and store cannot be eliminated,281; they might be different locations282; CM: MOVA_INT283; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,284; CM: MOVA_INT285; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,286; TODO: This load and store cannot be eliminated,287; they might be different locations288; CM: MOVA_INT289; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,290; CM: MOVA_INT291; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,292; TODO: This load and store cannot be eliminated,293; they might be different locations294; CM: MOVA_INT295; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,296; CM: MOVA_INT297; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,298 299; SI: buffer_store_byte300; SI: buffer_store_byte301; SI: buffer_store_byte302; SI: buffer_store_byte303; SI-NOT: buffer_store_dword304define amdgpu_kernel void @store_v4i8_unaligned(ptr addrspace(5) %out, <4 x i32> %in) {305entry:306 %0 = trunc <4 x i32> %in to <4 x i8>307 store <4 x i8> %0, ptr addrspace(5) %out, align 1308 ret void309}310 311; FUNC-LABEL: {{^}}store_v8i8_unaligned:312; EG: MOVA_INT313; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,314; EG: MOVA_INT315; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,316; TODO: This load and store cannot be eliminated,317; they might be different locations318; EG: MOVA_INT319; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,320; EG: MOVA_INT321; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,322; TODO: This load and store cannot be eliminated,323; they might be different locations324; EG: MOVA_INT325; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,326; EG: MOVA_INT327; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,328; TODO: This load and store cannot be eliminated,329; they might be different locations330; EG: MOVA_INT331; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,332; EG: MOVA_INT333; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,334; TODO: This load and store cannot be eliminated,335; they might be different locations336; EG: MOVA_INT337; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,338; EG: MOVA_INT339; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,340; TODO: This load and store cannot be eliminated,341; they might be different locations342; EG: MOVA_INT343; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,344; EG: MOVA_INT345; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,346; TODO: This load and store cannot be eliminated,347; they might be different locations348; EG: MOVA_INT349; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,350; EG: MOVA_INT351; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,352; TODO: This load and store cannot be eliminated,353; they might be different locations354; EG: MOVA_INT355; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,356; EG: MOVA_INT357; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,358 359; CM: MOVA_INT360; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,361; CM: MOVA_INT362; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,363; TODO: This load and store cannot be eliminated,364; they might be different locations365; CM: MOVA_INT366; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,367; CM: MOVA_INT368; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,369; TODO: This load and store cannot be eliminated,370; they might be different locations371; CM: MOVA_INT372; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,373; CM: MOVA_INT374; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,375; TODO: This load and store cannot be eliminated,376; they might be different locations377; CM: MOVA_INT378; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,379; CM: MOVA_INT380; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,381; TODO: This load and store cannot be eliminated,382; they might be different locations383; CM: MOVA_INT384; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,385; CM: MOVA_INT386; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,387; TODO: This load and store cannot be eliminated,388; they might be different locations389; CM: MOVA_INT390; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,391; CM: MOVA_INT392; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,393; TODO: This load and store cannot be eliminated,394; they might be different locations395; CM: MOVA_INT396; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,397; CM: MOVA_INT398; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,399; TODO: This load and store cannot be eliminated,400; they might be different locations401; CM: MOVA_INT402; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,403; CM: MOVA_INT404; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,405 406; SI: buffer_store_byte407; SI: buffer_store_byte408; SI: buffer_store_byte409; SI: buffer_store_byte410; SI: buffer_store_byte411; SI: buffer_store_byte412; SI: buffer_store_byte413; SI: buffer_store_byte414; SI-NOT: buffer_store_dword415define amdgpu_kernel void @store_v8i8_unaligned(ptr addrspace(5) %out, <8 x i32> %in) {416entry:417 %0 = trunc <8 x i32> %in to <8 x i8>418 store <8 x i8> %0, ptr addrspace(5) %out, align 1419 ret void420}421 422; FUNC-LABEL: {{^}}store_v4i8_halfaligned:423; EG: MOVA_INT424; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,425; EG: MOVA_INT426; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,427; TODO: This load and store cannot be eliminated,428; they might be different locations429; EG: MOVA_INT430; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,431; EG: MOVA_INT432; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,433 434; CM: MOVA_INT435; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,436; CM: MOVA_INT437; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,438; TODO: This load and store cannot be eliminated,439; they might be different locations440; CM: MOVA_INT441; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,442; CM: MOVA_INT443; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,444 445; SI: buffer_store_short446; SI: buffer_store_short447; SI-NOT: buffer_store_dword448define amdgpu_kernel void @store_v4i8_halfaligned(ptr addrspace(5) %out, <4 x i32> %in) {449entry:450 %0 = trunc <4 x i32> %in to <4 x i8>451 store <4 x i8> %0, ptr addrspace(5) %out, align 2452 ret void453}454 455; floating-point store456; FUNC-LABEL: {{^}}store_f32:457; EG: MOVA_INT458; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,459 460; CM: MOVA_INT461; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,462 463; SI: buffer_store_dword464 465define amdgpu_kernel void @store_f32(ptr addrspace(5) %out, float %in) {466 store float %in, ptr addrspace(5) %out467 ret void468}469 470; FUNC-LABEL: {{^}}store_v4i16:471; EG: MOVA_INT472; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,473; EG: MOVA_INT474; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,475 476; CM: MOVA_INT477; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,478; CM: MOVA_INT479; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,480 481;TODO: why not x2?482; XSI: buffer_store_dwordx2483; SI: buffer_store_dword484; SI: buffer_store_dword485define amdgpu_kernel void @store_v4i16(ptr addrspace(5) %out, <4 x i32> %in) {486entry:487 %0 = trunc <4 x i32> %in to <4 x i16>488 store <4 x i16> %0, ptr addrspace(5) %out489 ret void490}491 492; vec2 floating-point stores493; FUNC-LABEL: {{^}}store_v2f32:494; EG: MOVA_INT495; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,496; EG: MOVA_INT497; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,498 499; CM: MOVA_INT500; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,501; CM: MOVA_INT502; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,503 504;TODO: why not x2?505; XSI: buffer_store_dwordx2506; SI: buffer_store_dword507; SI: buffer_store_dword508 509define amdgpu_kernel void @store_v2f32(ptr addrspace(5) %out, float %a, float %b) {510entry:511 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0512 %1 = insertelement <2 x float> %0, float %b, i32 1513 store <2 x float> %1, ptr addrspace(5) %out514 ret void515}516 517; FUNC-LABEL: {{^}}store_v3i32:518; EG: MOVA_INT519; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,520; EG: MOVA_INT521; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,522; EG: MOVA_INT523; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,524 525; CM: MOVA_INT526; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,527; CM: MOVA_INT528; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,529; CM: MOVA_INT530; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,531 532;TODO: why not x2?533; XSI-DAG: buffer_store_dwordx2534; SI: buffer_store_dword535; SI: buffer_store_dword536; SI: buffer_store_dword537 538define amdgpu_kernel void @store_v3i32(ptr addrspace(5) %out, <3 x i32> %a) nounwind {539 store <3 x i32> %a, ptr addrspace(5) %out, align 16540 ret void541}542 543; FUNC-LABEL: {{^}}store_v4i32:544; EG: MOVA_INT545; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,546; EG: MOVA_INT547; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,548; EG: MOVA_INT549; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,550; EG: MOVA_INT551; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,552 553; CM: MOVA_INT554; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,555; CM: MOVA_INT556; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,557; CM: MOVA_INT558; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,559; CM: MOVA_INT560; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,561 562;TODO: why not x4?563; XSI: buffer_store_dwordx4564; SI: buffer_store_dword565; SI: buffer_store_dword566; SI: buffer_store_dword567; SI: buffer_store_dword568define amdgpu_kernel void @store_v4i32(ptr addrspace(5) %out, <4 x i32> %in) {569entry:570 store <4 x i32> %in, ptr addrspace(5) %out571 ret void572}573 574; FUNC-LABEL: {{^}}store_v4i32_unaligned:575; EG: MOVA_INT576; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,577; EG: MOVA_INT578; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,579; EG: MOVA_INT580; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,581; EG: MOVA_INT582; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,583 584; CM: MOVA_INT585; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,586; CM: MOVA_INT587; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,588; CM: MOVA_INT589; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,590; CM: MOVA_INT591; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,592 593;TODO: why not x4?594; XSI: buffer_store_dwordx4595; SI: buffer_store_dword596; SI: buffer_store_dword597; SI: buffer_store_dword598; SI: buffer_store_dword599define amdgpu_kernel void @store_v4i32_unaligned(ptr addrspace(5) %out, <4 x i32> %in) {600entry:601 store <4 x i32> %in, ptr addrspace(5) %out, align 4602 ret void603}604 605; v4f32 store606; FUNC-LABEL: {{^}}store_v4f32:607; EG: MOVA_INT608; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,609; EG: MOVA_INT610; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,611; EG: MOVA_INT612; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,613; EG: MOVA_INT614; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,615 616; CM: MOVA_INT617; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,618; CM: MOVA_INT619; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,620; CM: MOVA_INT621; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,622; CM: MOVA_INT623; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,624 625;TODO: why not x4?626; XSI: buffer_store_dwordx4627; SI: buffer_store_dword628; SI: buffer_store_dword629; SI: buffer_store_dword630; SI: buffer_store_dword631define amdgpu_kernel void @store_v4f32(ptr addrspace(5) %out, ptr addrspace(5) %in) {632 %1 = load <4 x float>, ptr addrspace(5) %in633 store <4 x float> %1, ptr addrspace(5) %out634 ret void635}636 637; FUNC-LABEL: {{^}}store_i64_i8:638; EG: MOVA_INT639; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,640; EG: MOVA_INT641; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,642 643; CM: MOVA_INT644; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,645; CM: MOVA_INT646; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,647 648; SI: buffer_store_byte649define amdgpu_kernel void @store_i64_i8(ptr addrspace(5) %out, i64 %in) {650entry:651 %0 = trunc i64 %in to i8652 store i8 %0, ptr addrspace(5) %out653 ret void654}655 656; FUNC-LABEL: {{^}}store_i64_i16:657; EG: MOVA_INT658; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,659; EG: MOVA_INT660; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,661 662; CM: MOVA_INT663; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,664; CM: MOVA_INT665; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,666 667; SI: buffer_store_short668define amdgpu_kernel void @store_i64_i16(ptr addrspace(5) %out, i64 %in) {669entry:670 %0 = trunc i64 %in to i16671 store i16 %0, ptr addrspace(5) %out672 ret void673}674 675; The stores in this function are combined by the optimizer to create a676; 64-bit store with 32-bit alignment. This is legal and the legalizer677; should not try to split the 64-bit store back into 2 32-bit stores.678 679; FUNC-LABEL: {{^}}vecload2:680; EG: MOVA_INT681; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,682; EG: MOVA_INT683; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,684 685; CM: MOVA_INT686; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,687; CM: MOVA_INT688; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,689 690;TODO: why not x2?691; XSI: buffer_store_dwordx2692; SI: buffer_store_dword693; SI: buffer_store_dword694define amdgpu_kernel void @vecload2(ptr addrspace(5) nocapture %out, ptr addrspace(4) nocapture %mem) #0 {695entry:696 %0 = load i32, ptr addrspace(4) %mem, align 4697 %arrayidx1.i = getelementptr inbounds i32, ptr addrspace(4) %mem, i64 1698 %1 = load i32, ptr addrspace(4) %arrayidx1.i, align 4699 store i32 %0, ptr addrspace(5) %out, align 4700 %arrayidx1 = getelementptr inbounds i32, ptr addrspace(5) %out, i64 1701 store i32 %1, ptr addrspace(5) %arrayidx1, align 4702 ret void703}704 705; When i128 was a legal type this program generated cannot select errors:706 707; FUNC-LABEL: {{^}}"i128-const-store":708; EG: MOVA_INT709; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,710; EG: MOVA_INT711; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,712; EG: MOVA_INT713; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,714; EG: MOVA_INT715; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,716 717; CM: MOVA_INT718; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,719; CM: MOVA_INT720; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,721; CM: MOVA_INT722; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,723; CM: MOVA_INT724; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,725 726;TODO: why not x4?727; XSI: buffer_store_dwordx4728; SI: buffer_store_dword729; SI: buffer_store_dword730; SI: buffer_store_dword731; SI: buffer_store_dword732define amdgpu_kernel void @i128-const-store(ptr addrspace(5) %out) {733entry:734 store i32 1, ptr addrspace(5) %out, align 4735 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(5) %out, i64 1736 store i32 1, ptr addrspace(5) %arrayidx2, align 4737 %arrayidx4 = getelementptr inbounds i32, ptr addrspace(5) %out, i64 2738 store i32 2, ptr addrspace(5) %arrayidx4, align 4739 %arrayidx6 = getelementptr inbounds i32, ptr addrspace(5) %out, i64 3740 store i32 2, ptr addrspace(5) %arrayidx6, align 4741 ret void742}743 744 745attributes #0 = { nounwind }746