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1; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 <%s | FileCheck -check-prefixes=GCN %s2;3; This test checks that we have the correct fold for zext(cc1) - zext(cc2).4;5; GCN-LABEL: sub_zext_zext:6; GCN: ds_read_b32 [[VAL:v[0-9]+]],7; GCN: v_cmp_lt_f32{{.*}} vcc, 0, [[VAL]]8; GCN: v_cndmask_{{.*}} [[ZEXTCC1:v[0-9]+]], 0, 1, vcc9; GCN: v_cmp_gt_f32{{.*}} vcc, 0, [[VAL]]10; GCN: v_subbrev{{.*}} {{v[0-9]+}}, vcc, 0, [[ZEXTCC1]], vcc11;12; Before the reversion that this test is attached to, the compiler commuted13; the operands to the sub and used different logic to select the addc/subc14; instruction:15; sub zext (setcc), x => addcarry 0, x, setcc16; sub sext (setcc), x => subcarry 0, x, setcc17;18; ... but that is bogus. I believe it is not possible to fold those commuted19; patterns into any form of addcarry or subcarry.20 21define amdgpu_cs float @sub_zext_zext() {22.entry:23 24 %t519 = load float, ptr addrspace(3) null25 26 %t524 = fcmp ogt float %t519, 0.000000e+0027 %t525 = fcmp olt float %t519, 0.000000e+0028 %t526 = zext i1 %t524 to i3229 %t527 = zext i1 %t525 to i3230 %t528 = sub nsw i32 %t526, %t52731 %t529 = sitofp i32 %t528 to float32 ret float %t52933}34 35