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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -amdgpu-codegenprepare-break-large-phis=0 -mcpu=tahiti -amdgpu-dce-in-ra=0 -o - %s | FileCheck %s3; Don't crash when the use of an undefined value is only detected by the4; register coalescer because it is hidden with subregister insert/extract.5target triple="amdgcn--"6 7; NOTE: breaking large PHIs is disabled here else this example is completely optimized out8; before reaching codegen.9 10define amdgpu_kernel void @foobar(float %a0, float %a1, ptr addrspace(1) %out) #1 {11; CHECK-LABEL: foobar:12; CHECK: ; %bb.0: ; %entry13; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x914; CHECK-NEXT: v_mbcnt_lo_u32_b32_e64 v0, -1, 015; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v016; CHECK-NEXT: s_mov_b32 s2, -117; CHECK-NEXT: s_waitcnt lgkmcnt(0)18; CHECK-NEXT: v_mov_b32_e32 v0, s419; CHECK-NEXT: v_mov_b32_e32 v1, s520; CHECK-NEXT: v_mov_b32_e32 v2, s621; CHECK-NEXT: v_mov_b32_e32 v3, s722; CHECK-NEXT: s_and_saveexec_b64 s[6:7], vcc23; CHECK-NEXT: ; %bb.1: ; %ift24; CHECK-NEXT: s_mov_b32 s4, s525; CHECK-NEXT: v_mov_b32_e32 v0, s426; CHECK-NEXT: v_mov_b32_e32 v1, s527; CHECK-NEXT: v_mov_b32_e32 v2, s628; CHECK-NEXT: v_mov_b32_e32 v3, s729; CHECK-NEXT: ; %bb.2: ; %ife30; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]31; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb32; CHECK-NEXT: s_mov_b32 s3, 0xf00033; CHECK-NEXT: s_waitcnt lgkmcnt(0)34; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], 035; CHECK-NEXT: s_endpgm36 37; FIXME: The change related to the fact that38; DetectDeadLanes pass hit "Copy across incompatible class" SGPR -> VGPR in analysis39; and hence it cannot derive the fact that the vector element in the "ift" block is unused.40; Such a copies appear because the float4 vectors and their elements in the test are uniform41; but the PHI node in "ife" block is divergent because of the CF dependency (divergent branch in bb0)42entry:43 %v0 = insertelement <4 x float> poison, float %a0, i32 044 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #045 %cnd = icmp eq i32 %tid, 046 br i1 %cnd, label %ift, label %ife47 48ift:49 %v1 = insertelement <4 x float> poison, float %a1, i32 050 br label %ife51 52ife:53 %val = phi <4 x float> [ %v1, %ift ], [ %v0, %entry ]54 %v2 = extractelement <4 x float> %val, i32 155 store float %v2, ptr addrspace(1) %out, align 456 ret void57}58 59declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #060 61attributes #0 = { nounwind readnone }62attributes #1 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }63