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1# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-vgpr-index-mode -run-pass=greedy -stress-regalloc=16 -o - %s | FileCheck -check-prefixes=GCN %s2 3# An interval for a register that was partially defined was split, creating4# a new use (a COPY) which was reached by the undef point. In particular,5# there was a subrange of the new register which was reached by an "undef"6# point. When the code in extendSegmentsToUses verified value numbers between7# the new and the old live ranges, it did not account for this kind of a8# situation and asserted expecting the old value to exist. For a PHI node9# it is legal to have a missing predecessor value as long as the end of10# the predecessor is jointly dominated by the undefs.11#12# A simplified form of this can be illustrated as13#14# bb.1:15# %0:vreg_64 = IMPLICIT_DEF16# ...17# S_CBRANCH_SCC1 %bb.2, implicit $vcc18# S_BRANCH %bb.319#20# bb.2:21# ; predecessors: %bb.1, %bb.422# dead %1:vreg_64 = COPY %0:vreg_64 ; This is the point of the inserted split23# ...24# S_BRANCH %bb.525#26# bb.3:27# ; predecessors: %bb.128# undef %0.sub0:vreg_64 = COPY %123:sreg_32 ; undef point for %0.sub129# ...30# S_BRANCH %bb.431#32# bb.433# ; predecessors: %bb.434# ...35# S_BRANCH %bb.236#37# This test exposes this scenario which caused previously caused an assert38 39---40name: _amdgpu_ps_main41tracksRegLiveness: true42machineFunctionInfo:43 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr344 stackPtrOffsetReg: $sgpr3245liveins:46 - { reg: '$vgpr2', virtual-reg: '%0' }47 - { reg: '$vgpr3', virtual-reg: '%1' }48 - { reg: '$vgpr4', virtual-reg: '%2' }49body: |50 bb.0:51 successors: %bb.1(0x40000000), %bb.2(0x40000000)52 liveins: $vgpr2, $vgpr3, $vgpr453 %2:vgpr_32 = COPY $vgpr454 %1:vgpr_32 = COPY $vgpr355 %0:vgpr_32 = COPY $vgpr256 S_CBRANCH_SCC0 %bb.2, implicit undef $scc57 58 bb.1:59 successors: %bb.5(0x80000000)60 undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec61 %3.sub1:vreg_128 = COPY %3.sub062 %3.sub2:vreg_128 = COPY %3.sub063 S_BRANCH %bb.564 65 bb.2:66 successors: %bb.3(0x40000000), %bb.4(0x40000000)67 S_CBRANCH_SCC0 %bb.4, implicit undef $scc68 69 bb.3:70 successors: %bb.5(0x80000000)71 undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec72 %3.sub1:vreg_128 = COPY %3.sub073 S_BRANCH %bb.574 75 bb.4:76 successors: %bb.5(0x80000000)77 %3:vreg_128 = IMPLICIT_DEF78 79 bb.5:80 successors: %bb.6(0x40000000), %bb.22(0x40000000)81 %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec82 S_CBRANCH_SCC1 %bb.22, implicit undef $scc83 S_BRANCH %bb.684 85 bb.6:86 successors: %bb.8(0x40000000), %bb.11(0x40000000)87 %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec88 dead %6:vgpr_32 = V_MUL_F32_e32 0, undef %7:vgpr_32, implicit $mode, implicit $exec89 dead %8:vgpr_32 = V_MUL_F32_e32 0, %2, implicit $mode, implicit $exec90 undef %9.sub1:vreg_64 = V_MUL_F32_e32 0, %1, implicit $mode, implicit $exec91 undef %10.sub0:vreg_128 = V_MUL_F32_e32 0, %0, implicit $mode, implicit $exec92 undef %11.sub0:sgpr_256 = S_MOV_B32 093 %11.sub1:sgpr_256 = COPY %11.sub094 %11.sub2:sgpr_256 = COPY %11.sub095 %11.sub3:sgpr_256 = COPY %11.sub096 %11.sub4:sgpr_256 = COPY %11.sub097 %11.sub5:sgpr_256 = COPY %11.sub098 %11.sub6:sgpr_256 = COPY %11.sub099 %11.sub7:sgpr_256 = COPY %11.sub0100 %12:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %9, %11, undef %13:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from constant-pool, addrspace 4)101 %14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec102 %15:vreg_128 = IMPLICIT_DEF103 S_CBRANCH_SCC1 %bb.8, implicit undef $scc104 S_BRANCH %bb.11105 106 bb.7:107 successors: %bb.13(0x80000000)108 109 ; GCN-LABEL: bb.7:110 ; GCN: undef %{{.+}}.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec111 112 undef %15.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec113 %15.sub1:vreg_128 = COPY %15.sub0114 %15.sub2:vreg_128 = COPY %15.sub0115 %5:vgpr_32 = IMPLICIT_DEF116 S_BRANCH %bb.13117 118 bb.8:119 successors: %bb.9(0x40000000), %bb.10(0x40000000)120 S_CBRANCH_SCC0 %bb.10, implicit undef $scc121 122 bb.9:123 successors: %bb.12(0x80000000)124 125 ; GCN-LABEL: bb.9:126 ; GCN: undef %{{.+}}.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec127 128 undef %15.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec129 %15.sub1:vreg_128 = COPY %15.sub0130 %15.sub2:vreg_128 = COPY %15.sub0131 S_BRANCH %bb.12132 133 bb.10:134 successors: %bb.12(0x80000000)135 136 ; GCN-LABEL: bb.10:137 ; GCN: undef %{{.+}}.sub0:vreg_128 = V_MOV_B32_e32 2143289344, implicit $exec138 139 undef %15.sub0:vreg_128 = V_MOV_B32_e32 2143289344, implicit $exec140 %15.sub1:vreg_128 = COPY %15.sub0141 %15.sub2:vreg_128 = COPY %15.sub0142 S_BRANCH %bb.12143 144 bb.11:145 successors: %bb.7(0x40000000), %bb.13(0x40000000)146 %16:sreg_64 = V_CMP_NE_U32_e64 0, %14, implicit $exec147 %17:sreg_64 = S_AND_B64 $exec, %16, implicit-def dead $scc148 $vcc = COPY %17149 S_CBRANCH_VCCNZ %bb.7, implicit $vcc150 S_BRANCH %bb.13151 152 bb.12:153 successors: %bb.11(0x80000000)154 %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec155 %5:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec156 S_BRANCH %bb.11157 158 bb.13:159 successors: %bb.15(0x40000000), %bb.14(0x40000000)160 161 %18:vgpr_32 = V_MAD_F32_e64 0, %10.sub0, 0, target-flags(amdgpu-gotprel) 1073741824, 0, -1082130432, 0, 0, implicit $mode, implicit $exec162 %19:vgpr_32 = V_MAD_F32_e64 0, %12.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $mode, implicit $exec163 %20:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sgpr_128, 1040, 0 :: (dereferenceable invariant load (s128))164 %22:vgpr_32 = V_ADD_F32_e32 0, %19, implicit $mode, implicit $exec165 %23:vgpr_32 = V_MAD_F32_e64 0, %18, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec166 %24:vgpr_32 = COPY %20.sub3167 %25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $mode, implicit $exec168 %26:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sgpr_128, 1056, 0 :: (dereferenceable invariant load (s128))169 %28:vgpr_32 = V_MAD_F32_e64 0, %18, 0, %26.sub0, 0, 0, 0, 0, implicit $mode, implicit $exec170 %29:vgpr_32 = V_ADD_F32_e32 %28, %19, implicit $mode, implicit $exec171 %30:vgpr_32 = V_RCP_F32_e32 %29, implicit $mode, implicit $exec172 %25:vgpr_32 = V_MAC_F32_e32 0, %18, %25, implicit $mode, implicit $exec173 %31:vgpr_32 = V_MAD_F32_e64 0, target-flags(amdgpu-gotprel) 0, 0, %12.sub0, 0, %24, 0, 0, implicit $mode, implicit $exec174 %32:vgpr_32 = V_ADD_F32_e32 %25, %31, implicit $mode, implicit $exec175 %33:vgpr_32 = V_MUL_F32_e32 %22, %30, implicit $mode, implicit $exec176 %34:vgpr_32 = V_MUL_F32_e32 %23, %30, implicit $mode, implicit $exec177 %35:vgpr_32 = V_MUL_F32_e32 %32, %30, implicit $mode, implicit $exec178 %36:vgpr_32 = V_MUL_F32_e32 0, %34, implicit $mode, implicit $exec179 %36:vgpr_32 = V_MAC_F32_e32 0, %33, %36, implicit $mode, implicit $exec180 %37:vgpr_32 = V_MAD_F32_e64 0, %35, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec181 %38:sreg_64_xexec = V_CMP_NE_U32_e64 0, %5, implicit $exec182 %39:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %38, implicit $exec183 V_CMP_NE_U32_e32 1, %39, implicit-def $vcc, implicit $exec184 $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc185 %40:vgpr_32 = V_ADD_F32_e32 %36, %37, implicit $mode, implicit $exec186 S_CBRANCH_VCCZ %bb.15, implicit $vcc187 188 bb.14:189 successors: %bb.17(0x80000000)190 S_BRANCH %bb.17191 192 bb.15:193 successors: %bb.16(0x40000000), %bb.18(0x40000000)194 %41:vgpr_32 = V_MAD_F32_e64 0, %40, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec195 %42:sreg_64 = V_CMP_LE_F32_e64 0, 0, 0, %41, 0, implicit $mode, implicit $exec196 %43:sreg_64 = V_CMP_GE_F32_e64 0, 1065353216, 0, %41, 0, implicit $mode, implicit $exec197 %44:sreg_64 = S_AND_B64 %43, %43, implicit-def dead $scc198 %45:sreg_64 = S_AND_B64 %42, %42, implicit-def dead $scc199 %46:sreg_64 = S_AND_B64 %45, %44, implicit-def dead $scc200 %47:sreg_64 = COPY $exec, implicit-def $exec201 %48:sreg_64 = S_AND_B64 %47, %46, implicit-def dead $scc202 $exec = S_MOV_B64_term %48203 S_CBRANCH_EXECZ %bb.18, implicit $exec204 S_BRANCH %bb.16205 206 bb.16:207 successors: %bb.18(0x80000000)208 S_BRANCH %bb.18209 210 bb.17:211 successors: %bb.21(0x40000000), %bb.23(0x40000000)212 %49:sreg_64 = V_CMP_NE_U32_e64 0, %5, implicit $exec213 %50:sreg_64 = S_AND_B64 $exec, %49, implicit-def dead $scc214 %51:vreg_128 = IMPLICIT_DEF215 $vcc = COPY %50216 S_CBRANCH_VCCNZ %bb.21, implicit $vcc217 S_BRANCH %bb.23218 219 bb.18:220 successors: %bb.20(0x40000000), %bb.19(0x40000000)221 $exec = S_OR_B64 $exec, %47, implicit-def $scc222 %52:vgpr_32 = V_MAD_F32_e64 0, %3.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 1, %3.sub0, 0, 0, implicit $mode, implicit $exec223 %53:vgpr_32 = V_MUL_F32_e32 -2147483648, %3.sub1, implicit $mode, implicit $exec224 %53:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel32-hi) 1065353216, %3.sub2, %53, implicit $mode, implicit $exec225 %54:vgpr_32 = V_MUL_F32_e32 %53, %53, implicit $mode, implicit $exec226 %54:vgpr_32 = V_MAC_F32_e32 %52, %52, %54, implicit $mode, implicit $exec227 %55:vgpr_32 = V_SQRT_F32_e32 %54, implicit $mode, implicit $exec228 %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec229 %56:vgpr_32 = V_MOV_B32_e32 981668463, implicit $exec230 %57:sreg_64 = V_CMP_NGT_F32_e64 0, %55, 0, %56, 0, implicit $mode, implicit $exec231 %58:sreg_64 = S_AND_B64 $exec, %57, implicit-def dead $scc232 $vcc = COPY %58233 S_CBRANCH_VCCZ %bb.20, implicit $vcc234 235 bb.19:236 successors: %bb.17(0x80000000)237 S_BRANCH %bb.17238 239 bb.20:240 successors: %bb.17(0x80000000)241 S_BRANCH %bb.17242 243 bb.21:244 successors: %bb.23(0x80000000)245 %59:sreg_32 = S_MOV_B32 0246 undef %51.sub0:vreg_128 = COPY %59247 S_BRANCH %bb.23248 249 bb.22:250 successors: %bb.24(0x80000000)251 S_BRANCH %bb.24252 253 bb.23:254 successors: %bb.22(0x80000000)255 undef %60.sub1:vreg_64 = V_CVT_I32_F32_e32 %1, implicit $mode, implicit $exec256 %60.sub0:vreg_64 = V_CVT_I32_F32_e32 %0, implicit $mode, implicit $exec257 undef %61.sub0:sgpr_256 = S_MOV_B32 0258 %61.sub1:sgpr_256 = COPY %61.sub0259 %61.sub2:sgpr_256 = COPY %61.sub0260 %61.sub3:sgpr_256 = COPY %61.sub0261 %61.sub4:sgpr_256 = COPY %61.sub0262 %61.sub5:sgpr_256 = COPY %61.sub0263 %61.sub6:sgpr_256 = COPY %61.sub0264 %61.sub7:sgpr_256 = COPY %61.sub0265 %62:vgpr_32 = V_MOV_B32_e32 1033100696, implicit $exec266 %63:vgpr_32 = V_MUL_F32_e32 1060575065, %15.sub1, implicit $mode, implicit $exec267 %63:vgpr_32 = V_MAC_F32_e32 1046066128, %15.sub0, %63, implicit $mode, implicit $exec268 %64:vgpr_32 = IMAGE_LOAD_V1_V2 %60, %61, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from constant-pool, addrspace 4)269 %64:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel) 0, %51.sub0, %64, implicit $mode, implicit $exec270 %65:vgpr_32 = V_MUL_F32_e32 0, %64, implicit $mode, implicit $exec271 %66:vgpr_32 = V_MUL_F32_e32 0, %65, implicit $mode, implicit $exec272 %67:vgpr_32 = V_MAD_F32_e64 0, %66, 0, %62, 0, 0, 0, 0, implicit $mode, implicit $exec273 %63:vgpr_32 = V_MAC_F32_e32 %15.sub2, %62, %63, implicit $mode, implicit $exec274 %4:vgpr_32 = V_ADD_F32_e32 %63, %67, implicit $mode, implicit $exec275 S_BRANCH %bb.22276 277 bb.24:278 %68:vgpr_32 = V_MUL_F32_e32 0, %4, implicit $mode, implicit $exec279 %69:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, undef %70:vgpr_32, 0, %68, 0, 0, implicit $mode, implicit $exec280 EXP 0, undef %71:vgpr_32, %69, undef %72:vgpr_32, undef %73:vgpr_32, -1, -1, 15, implicit $exec281 S_ENDPGM 0282...283