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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s3 4# Deciding which lanes are killed needs to account for other defs in the5# instruction.6#7# addVRegDefDeps would encounter the %0.sub0 def and erase %0 from8# current vreg uses because it shared no lanes with %0.sub1 use on the9# nop. It then didn't see the lanemask when it reached the second10# subreg def, and failed to add the necessary dependency between the11# asm and S_NOP12 13---14name: no_live_subrange_at_use15tracksRegLiveness: true16machineFunctionInfo:17 isEntryFunction: true18body: |19 ; CHECK-LABEL: name: no_live_subrange_at_use20 ; CHECK: bb.0:21 ; CHECK-NEXT: successors: %bb.1(0x80000000)22 ; CHECK-NEXT: {{ $}}23 ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec24 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec25 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec26 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: bb.1:28 ; CHECK-NEXT: successors: %bb.1(0x80000000)29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)31 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def [[V_MOV_B32_e32_]], 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_]](tied-def 3)32 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]]33 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub0, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub134 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub135 ; CHECK-NEXT: $sgpr10 = S_MOV_B32 -136 ; CHECK-NEXT: S_BRANCH %bb.137 bb.0:38 undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec39 %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec40 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec41 42 bb.1:43 %2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)44 INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)45 INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %246 INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef %0.sub0, 1245194 /* regdef:VGPR_32 */, def %0.sub147 S_NOP 0, implicit %0.sub148 $sgpr10 = S_MOV_B32 -149 S_BRANCH %bb.150 51...52 53# Different operand order54---55name: no_live_subrange_at_use_swap56tracksRegLiveness: true57machineFunctionInfo:58 isEntryFunction: true59body: |60 ; CHECK-LABEL: name: no_live_subrange_at_use_swap61 ; CHECK: bb.0:62 ; CHECK-NEXT: successors: %bb.1(0x80000000)63 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec65 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec66 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec67 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: bb.1:69 ; CHECK-NEXT: successors: %bb.1(0x80000000)70 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)72 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def [[V_MOV_B32_e32_]], 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_]](tied-def 3)73 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[DS_READ_B32_gfx9_]]74 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub1, 1245194 /* regdef:VGPR_32 */, def undef [[V_MOV_B32_e32_]].sub075 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub176 ; CHECK-NEXT: $sgpr10 = S_MOV_B32 -177 ; CHECK-NEXT: S_BRANCH %bb.178 bb.0:79 undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec80 %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec81 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec82 83 bb.1:84 %2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)85 INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)86 INLINEASM &"", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, %287 INLINEASM &"", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %0.sub1, 1245194 /* regdef:VGPR_32 */, def undef %0.sub088 S_NOP 0, implicit %0.sub189 $sgpr10 = S_MOV_B32 -190 S_BRANCH %bb.191 92...93