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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stress-regalloc=4 -o - %s | FileCheck %s3 4; Make sure we can rematerialize split 64-bit constants (which5; MachineLICM hoisted out of the loop) and avoid spilling inside the6; loop.7;8; MachineLICM originally believed the constant materializes to be9; rematerializable, but the lowered REG_SEQUENCE uses they coalesece10; into were not. The InlineSpiller also did not recognize redundant11; spills inside the loop, so we would repeatedly reload the same12; values.13 14define amdgpu_kernel void @_Z6kernelILi4000ELi1EEvPd(ptr addrspace(1) %x.coerce) {15; CHECK-LABEL: _Z6kernelILi4000ELi1EEvPd:16; CHECK: ; %bb.0: ; %entry17; CHECK-NEXT: s_mov_b64 s[2:3], 0x10018; CHECK-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x019; CHECK-NEXT: s_mov_b64 s[0:1], 020; CHECK-NEXT: s_load_dword s0, s[0:1], 0x021; CHECK-NEXT: s_mov_b32 s2, 022; CHECK-NEXT: s_mov_b32 s4, 023; CHECK-NEXT: s_waitcnt lgkmcnt(0)24; CHECK-NEXT: v_mov_b32_e32 v0, s625; CHECK-NEXT: s_mov_b32 s1, 026; CHECK-NEXT: s_mov_b32 s3, 0x4026000027; CHECK-NEXT: s_mov_b32 s5, 0x4028000028; CHECK-NEXT: v_mov_b32_e32 v1, s729; CHECK-NEXT: .LBB0_1: ; %for.cond4.preheader30; CHECK-NEXT: ; =>This Inner Loop Header: Depth=131; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 032; CHECK-NEXT: s_mov_b32 s6, 033; CHECK-NEXT: s_mov_b32 s7, 0x4014000034; CHECK-NEXT: s_add_i32 s1, s1, s035; CHECK-NEXT: s_cmpk_lt_i32 s1, 0xa0036; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]37; CHECK-NEXT: s_mov_b32 s6, 038; CHECK-NEXT: s_mov_b32 s7, 0x4018000039; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]40; CHECK-NEXT: s_mov_b32 s6, 041; CHECK-NEXT: s_mov_b32 s7, 0x401c000042; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]43; CHECK-NEXT: s_mov_b32 s6, 044; CHECK-NEXT: s_mov_b32 s7, 0x4022000045; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]46; CHECK-NEXT: s_mov_b32 s6, 047; CHECK-NEXT: s_mov_b32 s7, 0x4024000048; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]49; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]50; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[4:5]51; CHECK-NEXT: s_cbranch_scc1 .LBB0_152; CHECK-NEXT: ; %bb.2: ; %for.cond.cleanup.loopexit53; CHECK-NEXT: v_mov_b32_e32 v2, 0x10054; CHECK-NEXT: v_mov_b32_e32 v3, 055; CHECK-NEXT: global_store_dwordx2 v[2:3], v[0:1], off56; CHECK-NEXT: s_endpgm57entry:58 %0 = load i32, ptr addrspace(4) null, align 459 %cmp6 = icmp slt i32 0, 256060 br i1 %cmp6, label %for.cond4.preheader, label %for.cond.cleanup61 62for.cond4.preheader: ; preds = %for.cond4.preheader, %entry63 %idx.07 = phi i32 [ %add13, %for.cond4.preheader ], [ 0, %entry ]64 %arrayidx.promoted = load double, ptr addrspace(1) inttoptr (i64 256 to ptr addrspace(1)), align 865 %add9 = fadd contract double %arrayidx.promoted, 0.000000e+0066 %add9.1 = fadd contract double %add9, 5.000000e+0067 %add9.2 = fadd contract double %add9.1, 6.000000e+0068 %add9.3 = fadd contract double %add9.2, 7.000000e+0069 %add9.4 = fadd contract double %add9.3, 9.000000e+0070 %add9.5 = fadd contract double %add9.4, 1.000000e+0171 %add9.6 = fadd contract double %add9.5, 1.100000e+0172 %add9.7 = fadd contract double %add9.6, 1.200000e+0173 store double %add9.7, ptr addrspace(1) inttoptr (i64 256 to ptr addrspace(1)), align 874 %add13 = add i32 %idx.07, %075 %cmp = icmp slt i32 %add13, 256076 br i1 %cmp, label %for.cond4.preheader, label %for.cond.cleanup77 78for.cond.cleanup: ; preds = %for.cond4.preheader, %entry79 ret void80}81 82declare i32 @llvm.amdgcn.workitem.id.x() #083declare i32 @llvm.amdgcn.workgroup.id.x() #084declare align 4 ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #085 86attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }87