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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s2define void @test(i1 %c0) #1 {3 ; Clean up the unreachable blocks introduced with LowerSwitch pass.4 ; This test ensures that, in the pass flow, UnreachableBlockElim pass5 ; follows the LowerSwitch. Otherwise, this testcase will crash6 ; immediately after the instruction selection due to the incomplete7 ; PHI node in an MBB whose incoming values were never codegenerated.8 ;9 ; GCN-LABEL: name: test10 ; GCN: bb.{{[0-9]+}}.entry:11 ; GCN: bb.{{[0-9]+}}.Flow1:12 ; GCN: bb.{{[0-9]+}}.entry.true.blk:13 ; GCN: bb.{{[0-9]+}}.entry.false.blk:14 ; GCN: bb.{{[0-9]+}}.switch.blk:15 16 ; GCN-NOT: bb.{{[0-9]+}}.preheader.blk17 ; GCN-NOT: bb.{{[0-9]+}}.pre.false.blk:18 ; GCN-NOT: bb.{{[0-9]+}}.unreach.blk:19 ; GCN-NOT: PHI20 21 ; GCN: bb.{{[0-9]+}}.Flow:22 ; GCN: bb.{{[0-9]+}}.UnifiedReturnBlock:23 entry:24 %idx = tail call i32 @llvm.amdgcn.workitem.id.x() #025 br i1 %c0, label %entry.true.blk, label %entry.false.blk26 27 entry.true.blk: ; preds = %entry28 %exit.cmp = icmp ult i32 %idx, 329 br i1 %exit.cmp, label %switch.blk, label %exit30 31 entry.false.blk: ; preds = %entry32 unreachable33 34 switch.blk: ; preds = %entry.true.blk35 switch i32 %idx, label %preheader.blk [36 i32 0, label %exit37 i32 1, label %exit38 i32 2, label %exit39 ]40 41 preheader.blk: ; preds = %switch.blk42 %pre.exit = icmp ult i32 %idx, 543 br i1 %pre.exit, label %unreach.blk, label %pre.false.blk44 45 pre.false.blk: ; preds = %preheader.blk46 %call.pre.false = tail call i32 @func(i32 %idx) #047 br label %unreach.blk48 49 unreach.blk: ; preds = %preheader.blk, %pre.false.blk50 %phi.val = phi i32 [ %call.pre.false, %pre.false.blk ], [ poison, %preheader.blk ]51 store i32 %phi.val, ptr poison52 unreachable53 54 exit: ; preds = %switch.blk55 ret void56}57 58declare i32 @llvm.amdgcn.workitem.id.x() #059declare i32 @func(i32)#060 61attributes #0 = { nounwind readnone }62attributes #1 = { nounwind }63