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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s3 4; The tail call target is known uniform, but will be in a VGPR, so we5; need readfirstlane to legalize it.6define void @tail_call_uniform_vgpr_value() {7; CHECK-LABEL: tail_call_uniform_vgpr_value:8; CHECK: ; %bb.0:9; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10; CHECK-NEXT: v_mov_b32_e32 v0, 011; CHECK-NEXT: ds_read_b64 v[0:1], v012; CHECK-NEXT: s_waitcnt lgkmcnt(0)13; CHECK-NEXT: v_readfirstlane_b32 s17, v114; CHECK-NEXT: v_readfirstlane_b32 s16, v015; CHECK-NEXT: s_setpc_b64 s[16:17]16 %fptr = load ptr, ptr addrspace(3) null, align 817 tail call void %fptr()18 ret void19}20 21@constant = external hidden addrspace(4) constant ptr22 23; readfirstlanes should fold out.24define void @tail_call_uniform_sgpr_value() {25; CHECK-LABEL: tail_call_uniform_sgpr_value:26; CHECK: ; %bb.0:27; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)28; CHECK-NEXT: s_getpc_b64 s[16:17]29; CHECK-NEXT: s_add_u32 s16, s16, constant@rel32@lo+430; CHECK-NEXT: s_addc_u32 s17, s17, constant@rel32@hi+1231; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x032; CHECK-NEXT: s_waitcnt lgkmcnt(0)33; CHECK-NEXT: s_setpc_b64 s[16:17]34 %fptr = load ptr, ptr addrspace(4) @constant, align 835 tail call void %fptr()36 ret void37}38