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1; RUN: llc -mtriple=amdgcn -disable-promote-alloca-to-vector < %s | FileCheck %s2 3declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #14 5declare i32 @llvm.amdgcn.workitem.id.x() #16 7; CI+ intrinsic8declare void @llvm.amdgcn.s.dcache.inv.vol() #09 10; VI+ intrinsic11declare void @llvm.amdgcn.s.dcache.wb() #012 13; CHECK-LABEL: {{^}}target_none:14; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x40015; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]]16; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6417define amdgpu_kernel void @target_none() #0 {18 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()19 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 102420 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep21 %id = call i32 @llvm.amdgcn.workitem.id.x()22 %id.ext = sext i32 %id to i6423 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext24 store i32 0, ptr addrspace(1) %gep25 ret void26}27 28; CHECK-LABEL: {{^}}target_tahiti:29; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x40030; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]]31; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6432define amdgpu_kernel void @target_tahiti() #1 {33 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()34 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 102435 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep36 %id = call i32 @llvm.amdgcn.workitem.id.x()37 %id.ext = sext i32 %id to i6438 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext39 store i32 0, ptr addrspace(1) %gep40 ret void41}42 43; CHECK-LABEL: {{^}}target_bonaire:44; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x10045; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6446; CHECK: s_dcache_inv_vol47define amdgpu_kernel void @target_bonaire() #3 {48 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()49 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 102450 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep51 %id = call i32 @llvm.amdgcn.workitem.id.x()52 %id.ext = sext i32 %id to i6453 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext54 store i32 0, ptr addrspace(1) %gep55 call void @llvm.amdgcn.s.dcache.inv.vol()56 ret void57}58 59; CHECK-LABEL: {{^}}target_fiji:60; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x40061; CHECK: flat_store_dword62; CHECK: s_dcache_wb{{$}}63define amdgpu_kernel void @target_fiji() #4 {64 %kernargs = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()65 %kernargs.gep = getelementptr inbounds i8, ptr addrspace(4) %kernargs, i64 102466 %ptr = load ptr addrspace(1), ptr addrspace(4) %kernargs.gep67 %id = call i32 @llvm.amdgcn.workitem.id.x()68 %id.ext = sext i32 %id to i6469 %gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 %id.ext70 store i32 0, ptr addrspace(1) %gep71 call void @llvm.amdgcn.s.dcache.wb()72 ret void73}74 75; CHECK-LABEL: {{^}}promote_alloca_enabled:76; CHECK: ds_read_b3277define amdgpu_kernel void @promote_alloca_enabled(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #5 {78entry:79 %stack = alloca [5 x i32], align 4, addrspace(5)80 %tmp = load i32, ptr addrspace(1) %in, align 481 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp82 %load = load i32, ptr addrspace(5) %arrayidx183 store i32 %load, ptr addrspace(1) %out84 ret void85}86 87; CHECK-LABEL: {{^}}promote_alloca_disabled:88; CHECK: SCRATCH_RSRC_DWORD089; CHECK: SCRATCH_RSRC_DWORD190; CHECK: ScratchSize: 2491define amdgpu_kernel void @promote_alloca_disabled(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in) #6 {92entry:93 %stack = alloca [5 x i32], align 4, addrspace(5)94 %tmp = load i32, ptr addrspace(1) %in, align 495 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp96 %load = load i32, ptr addrspace(5) %arrayidx197 store i32 %load, ptr addrspace(1) %out98 ret void99}100 101attributes #0 = { nounwind }102attributes #1 = { nounwind readnone }103attributes #2 = { nounwind "target-cpu"="tahiti" }104attributes #3 = { nounwind "target-cpu"="bonaire" }105attributes #4 = { nounwind "target-cpu"="fiji" }106attributes #5 = { nounwind "target-features"="+promote-alloca" "amdgpu-waves-per-eu"="1,3" "amdgpu-flat-work-group-size"="1,256" }107attributes #6 = { nounwind "target-features"="-promote-alloca" "amdgpu-waves-per-eu"="1,3" "amdgpu-flat-work-group-size"="1,256" }108