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1;RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s2 3;CHECK: TEX4;CHECK-NEXT: ALU5 6define amdgpu_vs void @test(<4 x float> inreg %reg0) {7 %1 = extractelement <4 x float> %reg0, i32 08 %2 = extractelement <4 x float> %reg0, i32 19 %3 = extractelement <4 x float> %reg0, i32 210 %4 = extractelement <4 x float> %reg0, i32 311 %5 = insertelement <4 x float> poison, float %1, i32 012 %6 = insertelement <4 x float> %5, float %2, i32 113 %7 = insertelement <4 x float> %6, float %3, i32 214 %8 = insertelement <4 x float> %7, float %4, i32 315 %9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)16 %10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)17 %11 = fadd <4 x float> %9, %1018 call void @llvm.r600.store.swizzle(<4 x float> %11, i32 0, i32 0)19 ret void20}21 22declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone23declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)24