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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -o - %s | FileCheck --check-prefix=GCN %s3 4define amdgpu_kernel void @test_should_convert_to_v_readfirstlane_b32(float %fval, i32 %arg1, i32 %arg2) {5; GCN-LABEL: test_should_convert_to_v_readfirstlane_b32:6; GCN: ; %bb.0: ; %entry7; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x08; GCN-NEXT: s_waitcnt lgkmcnt(0)9; GCN-NEXT: v_cvt_u32_f32_e32 v0, s010; GCN-NEXT: s_nop 011; GCN-NEXT: v_readfirstlane_b32 s0, v012; GCN-NEXT: s_lshl_b32 s0, s0, 1613; GCN-NEXT: s_or_b32 s5, s0, s114; GCN-NEXT: s_and_b32 s6, s5, s215; GCN-NEXT: s_lshr_b32 s4, s6, 216; GCN-NEXT: s_mov_b32 s7, s417; GCN-NEXT: v_mov_b32_e32 v0, s118; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 nt19; GCN-NEXT: s_endpgm20entry:21 %conv = fptoui float %fval to i3222 23 %shl = shl i32 %conv, 1624 %or = or i32 %shl, %arg125 %and = and i32 %or, %arg226 %shr = lshr i32 %and, 227 28 %sgpr128_0 = insertelement <4 x i32> poison, i32 %shr, i32 029 %sgpr128_1 = insertelement <4 x i32> %sgpr128_0, i32 %or, i32 130 %sgpr128_2 = insertelement <4 x i32> %sgpr128_1, i32 %and, i32 231 %sgpr128_3 = insertelement <4 x i32> %sgpr128_2, i32 %shr, i32 332 33 call void @llvm.amdgcn.raw.buffer.store.i32(i32 %arg1, <4 x i32> %sgpr128_3, i32 0, i32 0, i32 2)34 35 ret void36}37 38declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) #039 40attributes #0 = { nounwind }41