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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=VI %s4 5declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone6 7define amdgpu_kernel void @sextload_i1_to_i32_trunc_cmp_eq_0(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {8; SI-LABEL: sextload_i1_to_i32_trunc_cmp_eq_0:9; SI: ; %bb.0:10; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x911; SI-NEXT: s_mov_b32 s7, 0xf00012; SI-NEXT: s_mov_b32 s6, -113; SI-NEXT: s_mov_b32 s10, s614; SI-NEXT: s_mov_b32 s11, s715; SI-NEXT: s_waitcnt lgkmcnt(0)16; SI-NEXT: s_mov_b32 s8, s217; SI-NEXT: s_mov_b32 s9, s318; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 019; SI-NEXT: s_mov_b32 s4, s020; SI-NEXT: s_mov_b32 s5, s121; SI-NEXT: s_waitcnt vmcnt(0)22; SI-NEXT: v_and_b32_e32 v0, 1, v023; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v024; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc25; SI-NEXT: buffer_store_byte v0, off, s[4:7], 026; SI-NEXT: s_endpgm27;28; VI-LABEL: sextload_i1_to_i32_trunc_cmp_eq_0:29; VI: ; %bb.0:30; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2431; VI-NEXT: s_mov_b32 s7, 0xf00032; VI-NEXT: s_mov_b32 s6, -133; VI-NEXT: s_mov_b32 s10, s634; VI-NEXT: s_mov_b32 s11, s735; VI-NEXT: s_waitcnt lgkmcnt(0)36; VI-NEXT: s_mov_b32 s8, s237; VI-NEXT: s_mov_b32 s9, s338; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 039; VI-NEXT: s_mov_b32 s4, s040; VI-NEXT: s_mov_b32 s5, s141; VI-NEXT: s_waitcnt vmcnt(0)42; VI-NEXT: v_and_b32_e32 v0, 1, v043; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v044; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc45; VI-NEXT: buffer_store_byte v0, off, s[4:7], 046; VI-NEXT: s_endpgm47 %load = load i1, ptr addrspace(1) %in48 %ext = sext i1 %load to i3249 %cmp = icmp eq i32 %ext, 050 store i1 %cmp, ptr addrspace(1) %out51 ret void52}53 54; FIXME: The negate should be inverting the compare.55define amdgpu_kernel void @zextload_i1_to_i32_trunc_cmp_eq_0(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {56; SI-LABEL: zextload_i1_to_i32_trunc_cmp_eq_0:57; SI: ; %bb.0:58; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x959; SI-NEXT: s_mov_b32 s7, 0xf00060; SI-NEXT: s_mov_b32 s6, -161; SI-NEXT: s_mov_b32 s10, s662; SI-NEXT: s_mov_b32 s11, s763; SI-NEXT: s_waitcnt lgkmcnt(0)64; SI-NEXT: s_mov_b32 s8, s265; SI-NEXT: s_mov_b32 s9, s366; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 067; SI-NEXT: s_mov_b32 s4, s068; SI-NEXT: s_mov_b32 s5, s169; SI-NEXT: s_waitcnt vmcnt(0)70; SI-NEXT: v_and_b32_e32 v0, 1, v071; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v072; SI-NEXT: s_xor_b64 s[0:1], vcc, -173; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]74; SI-NEXT: buffer_store_byte v0, off, s[4:7], 075; SI-NEXT: s_endpgm76;77; VI-LABEL: zextload_i1_to_i32_trunc_cmp_eq_0:78; VI: ; %bb.0:79; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2480; VI-NEXT: s_mov_b32 s7, 0xf00081; VI-NEXT: s_mov_b32 s6, -182; VI-NEXT: s_mov_b32 s10, s683; VI-NEXT: s_mov_b32 s11, s784; VI-NEXT: s_waitcnt lgkmcnt(0)85; VI-NEXT: s_mov_b32 s8, s286; VI-NEXT: s_mov_b32 s9, s387; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 088; VI-NEXT: s_mov_b32 s4, s089; VI-NEXT: s_mov_b32 s5, s190; VI-NEXT: s_waitcnt vmcnt(0)91; VI-NEXT: v_and_b32_e32 v0, 1, v092; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v093; VI-NEXT: s_xor_b64 s[0:1], vcc, -194; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]95; VI-NEXT: buffer_store_byte v0, off, s[4:7], 096; VI-NEXT: s_endpgm97 %load = load i1, ptr addrspace(1) %in98 %ext = zext i1 %load to i3299 %cmp = icmp eq i32 %ext, 0100 store i1 %cmp, ptr addrspace(1) %out101 ret void102}103 104define amdgpu_kernel void @sextload_i1_to_i32_trunc_cmp_eq_1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {105; SI-LABEL: sextload_i1_to_i32_trunc_cmp_eq_1:106; SI: ; %bb.0:107; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9108; SI-NEXT: s_mov_b32 s3, 0xf000109; SI-NEXT: s_mov_b32 s2, -1110; SI-NEXT: v_mov_b32_e32 v0, 0111; SI-NEXT: s_waitcnt lgkmcnt(0)112; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0113; SI-NEXT: s_endpgm114;115; VI-LABEL: sextload_i1_to_i32_trunc_cmp_eq_1:116; VI: ; %bb.0:117; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24118; VI-NEXT: s_mov_b32 s3, 0xf000119; VI-NEXT: s_mov_b32 s2, -1120; VI-NEXT: v_mov_b32_e32 v0, 0121; VI-NEXT: s_waitcnt lgkmcnt(0)122; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0123; VI-NEXT: s_endpgm124 %load = load i1, ptr addrspace(1) %in125 %ext = sext i1 %load to i32126 %cmp = icmp eq i32 %ext, 1127 store i1 %cmp, ptr addrspace(1) %out128 ret void129}130 131define amdgpu_kernel void @zextload_i1_to_i32_trunc_cmp_eq_1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {132; SI-LABEL: zextload_i1_to_i32_trunc_cmp_eq_1:133; SI: ; %bb.0:134; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9135; SI-NEXT: s_mov_b32 s7, 0xf000136; SI-NEXT: s_mov_b32 s6, -1137; SI-NEXT: s_mov_b32 s10, s6138; SI-NEXT: s_mov_b32 s11, s7139; SI-NEXT: s_waitcnt lgkmcnt(0)140; SI-NEXT: s_mov_b32 s8, s2141; SI-NEXT: s_mov_b32 s9, s3142; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0143; SI-NEXT: s_mov_b32 s4, s0144; SI-NEXT: s_mov_b32 s5, s1145; SI-NEXT: s_waitcnt vmcnt(0)146; SI-NEXT: v_and_b32_e32 v0, 1, v0147; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0148; SI-NEXT: s_endpgm149;150; VI-LABEL: zextload_i1_to_i32_trunc_cmp_eq_1:151; VI: ; %bb.0:152; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24153; VI-NEXT: s_mov_b32 s7, 0xf000154; VI-NEXT: s_mov_b32 s6, -1155; VI-NEXT: s_mov_b32 s10, s6156; VI-NEXT: s_mov_b32 s11, s7157; VI-NEXT: s_waitcnt lgkmcnt(0)158; VI-NEXT: s_mov_b32 s8, s2159; VI-NEXT: s_mov_b32 s9, s3160; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0161; VI-NEXT: s_mov_b32 s4, s0162; VI-NEXT: s_mov_b32 s5, s1163; VI-NEXT: s_waitcnt vmcnt(0)164; VI-NEXT: v_and_b32_e32 v0, 1, v0165; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0166; VI-NEXT: s_endpgm167 %load = load i1, ptr addrspace(1) %in168 %ext = zext i1 %load to i32169 %cmp = icmp eq i32 %ext, 1170 store i1 %cmp, ptr addrspace(1) %out171 ret void172}173 174define amdgpu_kernel void @sextload_i1_to_i32_trunc_cmp_eq_neg1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {175; SI-LABEL: sextload_i1_to_i32_trunc_cmp_eq_neg1:176; SI: ; %bb.0:177; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9178; SI-NEXT: s_mov_b32 s7, 0xf000179; SI-NEXT: s_mov_b32 s6, -1180; SI-NEXT: s_mov_b32 s10, s6181; SI-NEXT: s_mov_b32 s11, s7182; SI-NEXT: s_waitcnt lgkmcnt(0)183; SI-NEXT: s_mov_b32 s8, s2184; SI-NEXT: s_mov_b32 s9, s3185; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0186; SI-NEXT: s_mov_b32 s4, s0187; SI-NEXT: s_mov_b32 s5, s1188; SI-NEXT: s_waitcnt vmcnt(0)189; SI-NEXT: v_and_b32_e32 v0, 1, v0190; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0191; SI-NEXT: s_endpgm192;193; VI-LABEL: sextload_i1_to_i32_trunc_cmp_eq_neg1:194; VI: ; %bb.0:195; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24196; VI-NEXT: s_mov_b32 s7, 0xf000197; VI-NEXT: s_mov_b32 s6, -1198; VI-NEXT: s_mov_b32 s10, s6199; VI-NEXT: s_mov_b32 s11, s7200; VI-NEXT: s_waitcnt lgkmcnt(0)201; VI-NEXT: s_mov_b32 s8, s2202; VI-NEXT: s_mov_b32 s9, s3203; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0204; VI-NEXT: s_mov_b32 s4, s0205; VI-NEXT: s_mov_b32 s5, s1206; VI-NEXT: s_waitcnt vmcnt(0)207; VI-NEXT: v_and_b32_e32 v0, 1, v0208; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0209; VI-NEXT: s_endpgm210 %load = load i1, ptr addrspace(1) %in211 %ext = sext i1 %load to i32212 %cmp = icmp eq i32 %ext, -1213 store i1 %cmp, ptr addrspace(1) %out214 ret void215}216 217define amdgpu_kernel void @zextload_i1_to_i32_trunc_cmp_eq_neg1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {218; SI-LABEL: zextload_i1_to_i32_trunc_cmp_eq_neg1:219; SI: ; %bb.0:220; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9221; SI-NEXT: s_mov_b32 s3, 0xf000222; SI-NEXT: s_mov_b32 s2, -1223; SI-NEXT: v_mov_b32_e32 v0, 0224; SI-NEXT: s_waitcnt lgkmcnt(0)225; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0226; SI-NEXT: s_endpgm227;228; VI-LABEL: zextload_i1_to_i32_trunc_cmp_eq_neg1:229; VI: ; %bb.0:230; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24231; VI-NEXT: s_mov_b32 s3, 0xf000232; VI-NEXT: s_mov_b32 s2, -1233; VI-NEXT: v_mov_b32_e32 v0, 0234; VI-NEXT: s_waitcnt lgkmcnt(0)235; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0236; VI-NEXT: s_endpgm237 %load = load i1, ptr addrspace(1) %in238 %ext = zext i1 %load to i32239 %cmp = icmp eq i32 %ext, -1240 store i1 %cmp, ptr addrspace(1) %out241 ret void242}243 244 245define amdgpu_kernel void @sextload_i1_to_i32_trunc_cmp_ne_0(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {246; SI-LABEL: sextload_i1_to_i32_trunc_cmp_ne_0:247; SI: ; %bb.0:248; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9249; SI-NEXT: s_mov_b32 s7, 0xf000250; SI-NEXT: s_mov_b32 s6, -1251; SI-NEXT: s_mov_b32 s10, s6252; SI-NEXT: s_mov_b32 s11, s7253; SI-NEXT: s_waitcnt lgkmcnt(0)254; SI-NEXT: s_mov_b32 s8, s2255; SI-NEXT: s_mov_b32 s9, s3256; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0257; SI-NEXT: s_mov_b32 s4, s0258; SI-NEXT: s_mov_b32 s5, s1259; SI-NEXT: s_waitcnt vmcnt(0)260; SI-NEXT: v_and_b32_e32 v0, 1, v0261; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0262; SI-NEXT: s_endpgm263;264; VI-LABEL: sextload_i1_to_i32_trunc_cmp_ne_0:265; VI: ; %bb.0:266; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24267; VI-NEXT: s_mov_b32 s7, 0xf000268; VI-NEXT: s_mov_b32 s6, -1269; VI-NEXT: s_mov_b32 s10, s6270; VI-NEXT: s_mov_b32 s11, s7271; VI-NEXT: s_waitcnt lgkmcnt(0)272; VI-NEXT: s_mov_b32 s8, s2273; VI-NEXT: s_mov_b32 s9, s3274; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0275; VI-NEXT: s_mov_b32 s4, s0276; VI-NEXT: s_mov_b32 s5, s1277; VI-NEXT: s_waitcnt vmcnt(0)278; VI-NEXT: v_and_b32_e32 v0, 1, v0279; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0280; VI-NEXT: s_endpgm281 %load = load i1, ptr addrspace(1) %in282 %ext = sext i1 %load to i32283 %cmp = icmp ne i32 %ext, 0284 store i1 %cmp, ptr addrspace(1) %out285 ret void286}287 288define amdgpu_kernel void @zextload_i1_to_i32_trunc_cmp_ne_0(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {289; SI-LABEL: zextload_i1_to_i32_trunc_cmp_ne_0:290; SI: ; %bb.0:291; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9292; SI-NEXT: s_mov_b32 s7, 0xf000293; SI-NEXT: s_mov_b32 s6, -1294; SI-NEXT: s_mov_b32 s10, s6295; SI-NEXT: s_mov_b32 s11, s7296; SI-NEXT: s_waitcnt lgkmcnt(0)297; SI-NEXT: s_mov_b32 s8, s2298; SI-NEXT: s_mov_b32 s9, s3299; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0300; SI-NEXT: s_mov_b32 s4, s0301; SI-NEXT: s_mov_b32 s5, s1302; SI-NEXT: s_waitcnt vmcnt(0)303; SI-NEXT: v_and_b32_e32 v0, 1, v0304; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0305; SI-NEXT: s_endpgm306;307; VI-LABEL: zextload_i1_to_i32_trunc_cmp_ne_0:308; VI: ; %bb.0:309; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24310; VI-NEXT: s_mov_b32 s7, 0xf000311; VI-NEXT: s_mov_b32 s6, -1312; VI-NEXT: s_mov_b32 s10, s6313; VI-NEXT: s_mov_b32 s11, s7314; VI-NEXT: s_waitcnt lgkmcnt(0)315; VI-NEXT: s_mov_b32 s8, s2316; VI-NEXT: s_mov_b32 s9, s3317; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0318; VI-NEXT: s_mov_b32 s4, s0319; VI-NEXT: s_mov_b32 s5, s1320; VI-NEXT: s_waitcnt vmcnt(0)321; VI-NEXT: v_and_b32_e32 v0, 1, v0322; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0323; VI-NEXT: s_endpgm324 %load = load i1, ptr addrspace(1) %in325 %ext = zext i1 %load to i32326 %cmp = icmp ne i32 %ext, 0327 store i1 %cmp, ptr addrspace(1) %out328 ret void329}330 331define amdgpu_kernel void @sextload_i1_to_i32_trunc_cmp_ne_1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {332; SI-LABEL: sextload_i1_to_i32_trunc_cmp_ne_1:333; SI: ; %bb.0:334; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9335; SI-NEXT: s_mov_b32 s3, 0xf000336; SI-NEXT: s_mov_b32 s2, -1337; SI-NEXT: v_mov_b32_e32 v0, 1338; SI-NEXT: s_waitcnt lgkmcnt(0)339; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0340; SI-NEXT: s_endpgm341;342; VI-LABEL: sextload_i1_to_i32_trunc_cmp_ne_1:343; VI: ; %bb.0:344; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24345; VI-NEXT: s_mov_b32 s3, 0xf000346; VI-NEXT: s_mov_b32 s2, -1347; VI-NEXT: v_mov_b32_e32 v0, 1348; VI-NEXT: s_waitcnt lgkmcnt(0)349; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0350; VI-NEXT: s_endpgm351 %load = load i1, ptr addrspace(1) %in352 %ext = sext i1 %load to i32353 %cmp = icmp ne i32 %ext, 1354 store i1 %cmp, ptr addrspace(1) %out355 ret void356}357 358define amdgpu_kernel void @zextload_i1_to_i32_trunc_cmp_ne_1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {359; SI-LABEL: zextload_i1_to_i32_trunc_cmp_ne_1:360; SI: ; %bb.0:361; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9362; SI-NEXT: s_mov_b32 s7, 0xf000363; SI-NEXT: s_mov_b32 s6, -1364; SI-NEXT: s_mov_b32 s10, s6365; SI-NEXT: s_mov_b32 s11, s7366; SI-NEXT: s_waitcnt lgkmcnt(0)367; SI-NEXT: s_mov_b32 s8, s2368; SI-NEXT: s_mov_b32 s9, s3369; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0370; SI-NEXT: s_mov_b32 s4, s0371; SI-NEXT: s_mov_b32 s5, s1372; SI-NEXT: s_waitcnt vmcnt(0)373; SI-NEXT: v_and_b32_e32 v0, 1, v0374; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0375; SI-NEXT: s_xor_b64 s[0:1], vcc, -1376; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]377; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0378; SI-NEXT: s_endpgm379;380; VI-LABEL: zextload_i1_to_i32_trunc_cmp_ne_1:381; VI: ; %bb.0:382; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24383; VI-NEXT: s_mov_b32 s7, 0xf000384; VI-NEXT: s_mov_b32 s6, -1385; VI-NEXT: s_mov_b32 s10, s6386; VI-NEXT: s_mov_b32 s11, s7387; VI-NEXT: s_waitcnt lgkmcnt(0)388; VI-NEXT: s_mov_b32 s8, s2389; VI-NEXT: s_mov_b32 s9, s3390; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0391; VI-NEXT: s_mov_b32 s4, s0392; VI-NEXT: s_mov_b32 s5, s1393; VI-NEXT: s_waitcnt vmcnt(0)394; VI-NEXT: v_and_b32_e32 v0, 1, v0395; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0396; VI-NEXT: s_xor_b64 s[0:1], vcc, -1397; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]398; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0399; VI-NEXT: s_endpgm400 %load = load i1, ptr addrspace(1) %in401 %ext = zext i1 %load to i32402 %cmp = icmp ne i32 %ext, 1403 store i1 %cmp, ptr addrspace(1) %out404 ret void405}406 407; FIXME: This should be one compare.408define amdgpu_kernel void @sextload_i1_to_i32_trunc_cmp_ne_neg1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {409; SI-LABEL: sextload_i1_to_i32_trunc_cmp_ne_neg1:410; SI: ; %bb.0:411; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9412; SI-NEXT: s_mov_b32 s7, 0xf000413; SI-NEXT: s_mov_b32 s6, -1414; SI-NEXT: s_mov_b32 s10, s6415; SI-NEXT: s_mov_b32 s11, s7416; SI-NEXT: s_waitcnt lgkmcnt(0)417; SI-NEXT: s_mov_b32 s8, s2418; SI-NEXT: s_mov_b32 s9, s3419; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0420; SI-NEXT: s_mov_b32 s4, s0421; SI-NEXT: s_mov_b32 s5, s1422; SI-NEXT: s_waitcnt vmcnt(0)423; SI-NEXT: v_and_b32_e32 v0, 1, v0424; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0425; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc426; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0427; SI-NEXT: s_endpgm428;429; VI-LABEL: sextload_i1_to_i32_trunc_cmp_ne_neg1:430; VI: ; %bb.0:431; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24432; VI-NEXT: s_mov_b32 s7, 0xf000433; VI-NEXT: s_mov_b32 s6, -1434; VI-NEXT: s_mov_b32 s10, s6435; VI-NEXT: s_mov_b32 s11, s7436; VI-NEXT: s_waitcnt lgkmcnt(0)437; VI-NEXT: s_mov_b32 s8, s2438; VI-NEXT: s_mov_b32 s9, s3439; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0440; VI-NEXT: s_mov_b32 s4, s0441; VI-NEXT: s_mov_b32 s5, s1442; VI-NEXT: s_waitcnt vmcnt(0)443; VI-NEXT: v_and_b32_e32 v0, 1, v0444; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0445; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc446; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0447; VI-NEXT: s_endpgm448 %load = load i1, ptr addrspace(1) %in449 %ext = sext i1 %load to i32450 %cmp = icmp ne i32 %ext, -1451 store i1 %cmp, ptr addrspace(1) %out452 ret void453}454 455define amdgpu_kernel void @zextload_i1_to_i32_trunc_cmp_ne_neg1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {456; SI-LABEL: zextload_i1_to_i32_trunc_cmp_ne_neg1:457; SI: ; %bb.0:458; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9459; SI-NEXT: s_mov_b32 s3, 0xf000460; SI-NEXT: s_mov_b32 s2, -1461; SI-NEXT: v_mov_b32_e32 v0, 1462; SI-NEXT: s_waitcnt lgkmcnt(0)463; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0464; SI-NEXT: s_endpgm465;466; VI-LABEL: zextload_i1_to_i32_trunc_cmp_ne_neg1:467; VI: ; %bb.0:468; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24469; VI-NEXT: s_mov_b32 s3, 0xf000470; VI-NEXT: s_mov_b32 s2, -1471; VI-NEXT: v_mov_b32_e32 v0, 1472; VI-NEXT: s_waitcnt lgkmcnt(0)473; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0474; VI-NEXT: s_endpgm475 %load = load i1, ptr addrspace(1) %in476 %ext = zext i1 %load to i32477 %cmp = icmp ne i32 %ext, -1478 store i1 %cmp, ptr addrspace(1) %out479 ret void480}481 482; FIXME: Need to handle non-uniform case for function below (load without gep).483define amdgpu_kernel void @masked_load_i1_to_i32_trunc_cmp_ne_neg1(ptr addrspace(1) %out, ptr addrspace(1) %in) nounwind {484; SI-LABEL: masked_load_i1_to_i32_trunc_cmp_ne_neg1:485; SI: ; %bb.0:486; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9487; SI-NEXT: s_mov_b32 s7, 0xf000488; SI-NEXT: v_mov_b32_e32 v1, 0489; SI-NEXT: s_mov_b32 s10, 0490; SI-NEXT: s_mov_b32 s11, s7491; SI-NEXT: s_waitcnt lgkmcnt(0)492; SI-NEXT: s_mov_b64 s[8:9], s[2:3]493; SI-NEXT: buffer_load_sbyte v0, v[0:1], s[8:11], 0 addr64494; SI-NEXT: s_mov_b32 s6, -1495; SI-NEXT: s_mov_b32 s4, s0496; SI-NEXT: s_mov_b32 s5, s1497; SI-NEXT: s_waitcnt vmcnt(0)498; SI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0499; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc500; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0501; SI-NEXT: s_endpgm502;503; VI-LABEL: masked_load_i1_to_i32_trunc_cmp_ne_neg1:504; VI: ; %bb.0:505; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24506; VI-NEXT: s_waitcnt lgkmcnt(0)507; VI-NEXT: v_mov_b32_e32 v1, s3508; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0509; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc510; VI-NEXT: flat_load_sbyte v0, v[0:1]511; VI-NEXT: s_mov_b32 s3, 0xf000512; VI-NEXT: s_mov_b32 s2, -1513; VI-NEXT: s_waitcnt vmcnt(0)514; VI-NEXT: v_cmp_ne_u32_e32 vcc, -1, v0515; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc516; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0517; VI-NEXT: s_endpgm518 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()519 %in.ptr = getelementptr i8, ptr addrspace(1) %in, i32 %tid.x520 %load = load i8, ptr addrspace(1) %in.ptr521 %masked = and i8 %load, 255522 %ext = sext i8 %masked to i32523 %cmp = icmp ne i32 %ext, -1524 store i1 %cmp, ptr addrspace(1) %out525 ret void526}527