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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti | FileCheck %s -enable-var-scope -check-prefixes=GCN,SI3; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji | FileCheck %s -enable-var-scope -check-prefixes=GCN,VI4 5; Make sure high constant 0 isn't pointlessly materialized6define i16 @trunc_bitcast_i64_lshr_32_i16(i64 %bar) {7; GCN-LABEL: trunc_bitcast_i64_lshr_32_i16:8; GCN: ; %bb.0:9; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10; GCN-NEXT: v_mov_b32_e32 v0, v111; GCN-NEXT: s_setpc_b64 s[30:31]12 %srl = lshr i64 %bar, 3213 %trunc = trunc i64 %srl to i1614 ret i16 %trunc15}16 17define i32 @trunc_bitcast_i64_lshr_32_i32(i64 %bar) {18; GCN-LABEL: trunc_bitcast_i64_lshr_32_i32:19; GCN: ; %bb.0:20; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)21; GCN-NEXT: v_mov_b32_e32 v0, v122; GCN-NEXT: s_setpc_b64 s[30:31]23 %srl = lshr i64 %bar, 3224 %trunc = trunc i64 %srl to i3225 ret i32 %trunc26}27 28define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {29; SI-LABEL: trunc_bitcast_v2i32_to_i16:30; SI: ; %bb.0:31; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; SI-NEXT: s_mov_b32 s7, 0xf00033; SI-NEXT: s_mov_b32 s6, -134; SI-NEXT: buffer_load_dword v0, off, s[4:7], 035; SI-NEXT: s_waitcnt vmcnt(0)36; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v037; SI-NEXT: s_setpc_b64 s[30:31]38;39; VI-LABEL: trunc_bitcast_v2i32_to_i16:40; VI: ; %bb.0:41; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; VI-NEXT: flat_load_dword v0, v[0:1]43; VI-NEXT: s_waitcnt vmcnt(0)44; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v045; VI-NEXT: s_setpc_b64 s[30:31]46 %load0 = load i32, ptr addrspace(1) poison47 %load1 = load i32, ptr addrspace(1) null48 %insert.0 = insertelement <2 x i32> poison, i32 %load0, i32 049 %insert.1 = insertelement <2 x i32> %insert.0, i32 99, i32 150 %bc = bitcast <2 x i32> %insert.1 to i6451 %trunc = trunc i64 %bc to i1652 %add = add i16 %trunc, 453 ret i16 %add54}55 56; Make sure there's no crash if the source vector type is FP57define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {58; SI-LABEL: trunc_bitcast_v2f32_to_i16:59; SI: ; %bb.0:60; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)61; SI-NEXT: s_mov_b32 s7, 0xf00062; SI-NEXT: s_mov_b32 s6, -163; SI-NEXT: buffer_load_dword v0, off, s[4:7], 064; SI-NEXT: s_waitcnt vmcnt(0)65; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v066; SI-NEXT: s_setpc_b64 s[30:31]67;68; VI-LABEL: trunc_bitcast_v2f32_to_i16:69; VI: ; %bb.0:70; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)71; VI-NEXT: flat_load_dword v0, v[0:1]72; VI-NEXT: s_waitcnt vmcnt(0)73; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v074; VI-NEXT: s_setpc_b64 s[30:31]75 %load0 = load float, ptr addrspace(1) poison76 %load1 = load float, ptr addrspace(1) null77 %insert.0 = insertelement <2 x float> poison, float %load0, i32 078 %insert.1 = insertelement <2 x float> %insert.0, float 4.0, i32 179 %bc = bitcast <2 x float> %insert.1 to i6480 %trunc = trunc i64 %bc to i1681 %add = add i16 %trunc, 482 ret i16 %add83}84 85define amdgpu_kernel void @truncate_high_elt_extract_vector(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture readonly %arg1, ptr addrspace(1) nocapture %arg2) local_unnamed_addr {86; SI-LABEL: truncate_high_elt_extract_vector:87; SI: ; %bb.0: ; %bb88; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x989; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd90; SI-NEXT: s_mov_b32 s7, 0xf00091; SI-NEXT: s_mov_b32 s6, -192; SI-NEXT: s_waitcnt lgkmcnt(0)93; SI-NEXT: s_load_dword s0, s[0:1], 0x094; SI-NEXT: s_load_dword s1, s[2:3], 0x095; SI-NEXT: s_waitcnt lgkmcnt(0)96; SI-NEXT: s_sext_i32_i16 s0, s097; SI-NEXT: s_sext_i32_i16 s1, s198; SI-NEXT: s_mul_i32 s1, s1, s099; SI-NEXT: s_lshr_b32 s0, s1, 16100; SI-NEXT: v_mov_b32_e32 v0, s0101; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0102; SI-NEXT: s_endpgm103;104; VI-LABEL: truncate_high_elt_extract_vector:105; VI: ; %bb.0: ; %bb106; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24107; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34108; VI-NEXT: s_waitcnt lgkmcnt(0)109; VI-NEXT: s_load_dword s0, s[0:1], 0x0110; VI-NEXT: s_load_dword s1, s[2:3], 0x0111; VI-NEXT: v_mov_b32_e32 v0, s4112; VI-NEXT: v_mov_b32_e32 v1, s5113; VI-NEXT: s_waitcnt lgkmcnt(0)114; VI-NEXT: s_sext_i32_i16 s0, s0115; VI-NEXT: s_sext_i32_i16 s1, s1116; VI-NEXT: s_mul_i32 s1, s1, s0117; VI-NEXT: s_lshr_b32 s0, s1, 16118; VI-NEXT: v_mov_b32_e32 v2, s0119; VI-NEXT: flat_store_dword v[0:1], v2120; VI-NEXT: s_endpgm121bb:122 %tmp = getelementptr inbounds <2 x i16>, ptr addrspace(1) %arg, i64 0123 %tmp3 = load <2 x i16>, ptr addrspace(1) %tmp, align 4124 %tmp4 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %arg1, i64 0125 %tmp5 = load <2 x i16>, ptr addrspace(1) %tmp4, align 4126 %tmp6 = sext <2 x i16> %tmp3 to <2 x i32>127 %tmp7 = sext <2 x i16> %tmp5 to <2 x i32>128 %tmp8 = extractelement <2 x i32> %tmp6, i64 0129 %tmp9 = extractelement <2 x i32> %tmp7, i64 0130 %tmp10 = mul nsw i32 %tmp9, %tmp8131 %tmp11 = insertelement <2 x i32> poison, i32 %tmp10, i32 0132 %tmp12 = insertelement <2 x i32> %tmp11, i32 poison, i32 1133 %tmp13 = lshr <2 x i32> %tmp12, <i32 16, i32 16>134 %tmp14 = trunc <2 x i32> %tmp13 to <2 x i16>135 %tmp15 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %arg2, i64 0136 store <2 x i16> %tmp14, ptr addrspace(1) %tmp15, align 4137 ret void138}139 140define <2 x i16> @trunc_v2i64_arg_to_v2i16(<2 x i64> %arg0) #0 {141; SI-LABEL: trunc_v2i64_arg_to_v2i16:142; SI: ; %bb.0:143; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)144; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2145; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0146; SI-NEXT: v_or_b32_e32 v0, v0, v1147; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2148; SI-NEXT: s_setpc_b64 s[30:31]149;150; VI-LABEL: trunc_v2i64_arg_to_v2i16:151; VI: ; %bb.0:152; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)153; VI-NEXT: s_mov_b32 s4, 0x1000504154; VI-NEXT: v_perm_b32 v0, v0, v2, s4155; VI-NEXT: s_setpc_b64 s[30:31]156 %trunc = trunc <2 x i64> %arg0 to <2 x i16>157 ret <2 x i16> %trunc158}159 160; Test for regression where an unnecessary v_alignbit_b32 was inserted161; on the final result, due to losing the fact that the upper half of162; the lhs vector was undef.163define <2 x i16> @vector_trunc_high_bits_undef_lshr_lhs_alignbit_regression(i32 %arg0) {164; SI-LABEL: vector_trunc_high_bits_undef_lshr_lhs_alignbit_regression:165; SI: ; %bb.0:166; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)167; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0168; SI-NEXT: v_mov_b32_e32 v1, 0169; SI-NEXT: s_setpc_b64 s[30:31]170;171; VI-LABEL: vector_trunc_high_bits_undef_lshr_lhs_alignbit_regression:172; VI: ; %bb.0:173; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)174; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0175; VI-NEXT: s_setpc_b64 s[30:31]176 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0177 %lshr = lshr <2 x i32> %undef.hi.elt, splat (i32 16)178 %trunc = trunc <2 x i32> %lshr to <2 x i16>179 ret <2 x i16> %trunc180}181 182define <2 x i16> @vector_trunc_high_bits_undef_lshr_rhs_alignbit_regression(i32 %arg0) {183; SI-LABEL: vector_trunc_high_bits_undef_lshr_rhs_alignbit_regression:184; SI: ; %bb.0:185; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)186; SI-NEXT: v_lshr_b32_e32 v0, 16, v0187; SI-NEXT: v_mov_b32_e32 v1, 0188; SI-NEXT: s_setpc_b64 s[30:31]189;190; VI-LABEL: vector_trunc_high_bits_undef_lshr_rhs_alignbit_regression:191; VI: ; %bb.0:192; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)193; VI-NEXT: v_lshrrev_b32_e64 v0, v0, 16194; VI-NEXT: s_setpc_b64 s[30:31]195 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0196 %lshr = lshr <2 x i32> splat (i32 16), %undef.hi.elt197 %trunc = trunc <2 x i32> %lshr to <2 x i16>198 ret <2 x i16> %trunc199}200 201define <2 x i16> @vector_trunc_high_bits_undef_ashr_lhs_alignbit_regression(i32 %arg0) {202; SI-LABEL: vector_trunc_high_bits_undef_ashr_lhs_alignbit_regression:203; SI: ; %bb.0:204; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)205; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0206; SI-NEXT: v_mov_b32_e32 v1, 0207; SI-NEXT: s_setpc_b64 s[30:31]208;209; VI-LABEL: vector_trunc_high_bits_undef_ashr_lhs_alignbit_regression:210; VI: ; %bb.0:211; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)212; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0213; VI-NEXT: s_setpc_b64 s[30:31]214 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0215 %ashr = ashr <2 x i32> %undef.hi.elt, splat (i32 16)216 %trunc = trunc <2 x i32> %ashr to <2 x i16>217 ret <2 x i16> %trunc218}219 220define <2 x i16> @vector_trunc_high_bits_undef_ashr_rhs_alignbit_regression(i32 %arg0) {221; SI-LABEL: vector_trunc_high_bits_undef_ashr_rhs_alignbit_regression:222; SI: ; %bb.0:223; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)224; SI-NEXT: v_ashr_i32_e32 v0, -4, v0225; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0226; SI-NEXT: v_mov_b32_e32 v1, 0227; SI-NEXT: s_setpc_b64 s[30:31]228;229; VI-LABEL: vector_trunc_high_bits_undef_ashr_rhs_alignbit_regression:230; VI: ; %bb.0:231; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)232; VI-NEXT: v_ashrrev_i32_e64 v0, v0, -4233; VI-NEXT: s_setpc_b64 s[30:31]234 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0235 %lshr = ashr <2 x i32> splat (i32 -4), %undef.hi.elt236 %trunc = trunc <2 x i32> %lshr to <2 x i16>237 ret <2 x i16> %trunc238}239 240define <2 x i16> @vector_trunc_high_bits_undef_add_lhs_alignbit_regression(i32 %arg0) {241; SI-LABEL: vector_trunc_high_bits_undef_add_lhs_alignbit_regression:242; SI: ; %bb.0:243; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)244; SI-NEXT: v_add_i32_e32 v0, vcc, 16, v0245; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0246; SI-NEXT: v_mov_b32_e32 v1, 0247; SI-NEXT: s_setpc_b64 s[30:31]248;249; VI-LABEL: vector_trunc_high_bits_undef_add_lhs_alignbit_regression:250; VI: ; %bb.0:251; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)252; VI-NEXT: v_add_u32_e32 v0, vcc, 16, v0253; VI-NEXT: s_setpc_b64 s[30:31]254 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0255 %lshr = add <2 x i32> %undef.hi.elt, splat (i32 16)256 %trunc = trunc <2 x i32> %lshr to <2 x i16>257 ret <2 x i16> %trunc258}259 260define <2 x i16> @vector_trunc_high_bits_undef_shl_rhs_alignbit_regression(i32 %arg0) {261; SI-LABEL: vector_trunc_high_bits_undef_shl_rhs_alignbit_regression:262; SI: ; %bb.0:263; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)264; SI-NEXT: v_lshl_b32_e32 v0, 2, v0265; SI-NEXT: v_and_b32_e32 v0, 0xfffe, v0266; SI-NEXT: v_mov_b32_e32 v1, 0267; SI-NEXT: s_setpc_b64 s[30:31]268;269; VI-LABEL: vector_trunc_high_bits_undef_shl_rhs_alignbit_regression:270; VI: ; %bb.0:271; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)272; VI-NEXT: v_lshlrev_b32_e64 v0, v0, 2273; VI-NEXT: s_setpc_b64 s[30:31]274 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0275 %lshr = shl <2 x i32> splat (i32 2), %undef.hi.elt276 %trunc = trunc <2 x i32> %lshr to <2 x i16>277 ret <2 x i16> %trunc278}279 280define <2 x i16> @vector_trunc_high_bits_undef_sub_lhs_alignbit_regression(i32 %arg0) {281; SI-LABEL: vector_trunc_high_bits_undef_sub_lhs_alignbit_regression:282; SI: ; %bb.0:283; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)284; SI-NEXT: v_add_i32_e32 v0, vcc, -16, v0285; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0286; SI-NEXT: v_mov_b32_e32 v1, 0287; SI-NEXT: s_setpc_b64 s[30:31]288;289; VI-LABEL: vector_trunc_high_bits_undef_sub_lhs_alignbit_regression:290; VI: ; %bb.0:291; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)292; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0293; VI-NEXT: s_setpc_b64 s[30:31]294 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0295 %lshr = sub <2 x i32> %undef.hi.elt, splat (i32 16)296 %trunc = trunc <2 x i32> %lshr to <2 x i16>297 ret <2 x i16> %trunc298}299 300define <2 x i16> @vector_trunc_high_bits_undef_or_lhs_alignbit_regression(i32 %arg0) {301; SI-LABEL: vector_trunc_high_bits_undef_or_lhs_alignbit_regression:302; SI: ; %bb.0:303; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)304; SI-NEXT: v_or_b32_e32 v0, 0xffff0011, v0305; SI-NEXT: v_mov_b32_e32 v1, 0xffff306; SI-NEXT: s_setpc_b64 s[30:31]307;308; VI-LABEL: vector_trunc_high_bits_undef_or_lhs_alignbit_regression:309; VI: ; %bb.0:310; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)311; VI-NEXT: v_or_b32_e32 v0, 0xffff0011, v0312; VI-NEXT: s_setpc_b64 s[30:31]313 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0314 %lshr = or <2 x i32> %undef.hi.elt, splat (i32 17)315 %trunc = trunc <2 x i32> %lshr to <2 x i16>316 ret <2 x i16> %trunc317}318 319define <2 x i16> @vector_trunc_high_bits_undef_xor_lhs_alignbit_regression(i32 %arg0) {320; SI-LABEL: vector_trunc_high_bits_undef_xor_lhs_alignbit_regression:321; SI: ; %bb.0:322; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)323; SI-NEXT: v_xor_b32_e32 v0, 17, v0324; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0325; SI-NEXT: v_mov_b32_e32 v1, 0326; SI-NEXT: s_setpc_b64 s[30:31]327;328; VI-LABEL: vector_trunc_high_bits_undef_xor_lhs_alignbit_regression:329; VI: ; %bb.0:330; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)331; VI-NEXT: v_xor_b32_e32 v0, 17, v0332; VI-NEXT: s_setpc_b64 s[30:31]333 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0334 %lshr = xor <2 x i32> %undef.hi.elt, splat (i32 17)335 %trunc = trunc <2 x i32> %lshr to <2 x i16>336 ret <2 x i16> %trunc337}338 339define <2 x i16> @vector_trunc_high_bits_undef_shl_lhs_alignbit_regression(i32 %arg0) {340; SI-LABEL: vector_trunc_high_bits_undef_shl_lhs_alignbit_regression:341; SI: ; %bb.0:342; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)343; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0344; SI-NEXT: v_and_b32_e32 v0, 0xfffc, v0345; SI-NEXT: v_mov_b32_e32 v1, 0346; SI-NEXT: s_setpc_b64 s[30:31]347;348; VI-LABEL: vector_trunc_high_bits_undef_shl_lhs_alignbit_regression:349; VI: ; %bb.0:350; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)351; VI-NEXT: v_lshlrev_b16_e32 v0, 2, v0352; VI-NEXT: s_setpc_b64 s[30:31]353 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0354 %shl = shl <2 x i32> %undef.hi.elt, splat (i32 2)355 %trunc = trunc <2 x i32> %shl to <2 x i16>356 ret <2 x i16> %trunc357}358 359define <2 x i16> @vector_trunc_high_bits_undef_mul_lhs_alignbit_regression(i32 %arg0) {360; SI-LABEL: vector_trunc_high_bits_undef_mul_lhs_alignbit_regression:361; SI: ; %bb.0:362; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)363; SI-NEXT: v_mul_lo_u32 v0, v0, 18364; SI-NEXT: v_mov_b32_e32 v1, 0365; SI-NEXT: v_and_b32_e32 v0, 0xfffe, v0366; SI-NEXT: s_setpc_b64 s[30:31]367;368; VI-LABEL: vector_trunc_high_bits_undef_mul_lhs_alignbit_regression:369; VI: ; %bb.0:370; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)371; VI-NEXT: v_mul_lo_u32 v0, v0, 18372; VI-NEXT: v_and_b32_e32 v0, 0xfffe, v0373; VI-NEXT: s_setpc_b64 s[30:31]374 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0375 %lshr = mul <2 x i32> %undef.hi.elt, splat (i32 18)376 %trunc = trunc <2 x i32> %lshr to <2 x i16>377 ret <2 x i16> %trunc378}379 380define <2 x i16> @vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression(i32 %arg0) {381; SI-LABEL: vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression:382; SI: ; %bb.0:383; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)384; SI-NEXT: s_mov_b32 s4, 0x38e38e39385; SI-NEXT: v_mul_hi_i32 v0, v0, s4386; SI-NEXT: v_lshrrev_b32_e32 v1, 31, v0387; SI-NEXT: v_lshrrev_b32_e32 v0, 2, v0388; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1389; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0390; SI-NEXT: v_mov_b32_e32 v1, 0391; SI-NEXT: s_setpc_b64 s[30:31]392;393; VI-LABEL: vector_trunc_high_bits_undef_sdiv_lhs_alignbit_regression:394; VI: ; %bb.0:395; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)396; VI-NEXT: s_mov_b32 s4, 0x38e38e39397; VI-NEXT: v_mul_hi_i32 v0, v0, s4398; VI-NEXT: v_lshrrev_b32_e32 v1, 31, v0399; VI-NEXT: v_ashrrev_i32_e32 v0, 2, v0400; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1401; VI-NEXT: s_setpc_b64 s[30:31]402 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0403 %lshr = sdiv <2 x i32> %undef.hi.elt, splat (i32 18)404 %trunc = trunc <2 x i32> %lshr to <2 x i16>405 ret <2 x i16> %trunc406}407 408define <2 x i16> @vector_trunc_high_bits_undef_srem_lhs_alignbit_regression(i32 %arg0) {409; SI-LABEL: vector_trunc_high_bits_undef_srem_lhs_alignbit_regression:410; SI: ; %bb.0:411; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)412; SI-NEXT: s_mov_b32 s4, 0x38e38e39413; SI-NEXT: v_mul_hi_i32 v1, v0, s4414; SI-NEXT: v_lshrrev_b32_e32 v2, 31, v1415; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1416; SI-NEXT: v_add_i32_e32 v1, vcc, v1, v2417; SI-NEXT: v_mul_lo_u32 v1, v1, 18418; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1419; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0420; SI-NEXT: v_mov_b32_e32 v1, 0421; SI-NEXT: s_setpc_b64 s[30:31]422;423; VI-LABEL: vector_trunc_high_bits_undef_srem_lhs_alignbit_regression:424; VI: ; %bb.0:425; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; VI-NEXT: s_mov_b32 s4, 0x38e38e39427; VI-NEXT: v_mul_hi_i32 v1, v0, s4428; VI-NEXT: v_lshrrev_b32_e32 v2, 31, v1429; VI-NEXT: v_ashrrev_i32_e32 v1, 2, v1430; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2431; VI-NEXT: v_mul_lo_u32 v1, v1, 18432; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1433; VI-NEXT: s_setpc_b64 s[30:31]434 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0435 %lshr = srem <2 x i32> %undef.hi.elt, splat (i32 18)436 %trunc = trunc <2 x i32> %lshr to <2 x i16>437 ret <2 x i16> %trunc438}439 440 441define <2 x i16> @vector_trunc_high_bits_undef_udiv_lhs_alignbit_regression(i32 %arg0) {442; SI-LABEL: vector_trunc_high_bits_undef_udiv_lhs_alignbit_regression:443; SI: ; %bb.0:444; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)445; SI-NEXT: s_mov_b32 s4, 0x38e38e39446; SI-NEXT: v_mul_hi_u32 v0, v0, s4447; SI-NEXT: v_mov_b32_e32 v1, 0448; SI-NEXT: v_bfe_u32 v0, v0, 2, 16449; SI-NEXT: s_setpc_b64 s[30:31]450;451; VI-LABEL: vector_trunc_high_bits_undef_udiv_lhs_alignbit_regression:452; VI: ; %bb.0:453; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)454; VI-NEXT: s_mov_b32 s4, 0x38e38e39455; VI-NEXT: v_mul_hi_u32 v0, v0, s4456; VI-NEXT: v_lshrrev_b32_e32 v0, 2, v0457; VI-NEXT: s_setpc_b64 s[30:31]458 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0459 %lshr = udiv <2 x i32> %undef.hi.elt, splat (i32 18)460 %trunc = trunc <2 x i32> %lshr to <2 x i16>461 ret <2 x i16> %trunc462}463 464define <2 x i16> @vector_trunc_high_bits_undef_urem_lhs_alignbit_regression(i32 %arg0) {465; SI-LABEL: vector_trunc_high_bits_undef_urem_lhs_alignbit_regression:466; SI: ; %bb.0:467; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)468; SI-NEXT: s_mov_b32 s4, 0x38e38e39469; SI-NEXT: v_mul_hi_u32 v1, v0, s4470; SI-NEXT: v_lshrrev_b32_e32 v1, 2, v1471; SI-NEXT: v_mul_lo_u32 v1, v1, 18472; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1473; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0474; SI-NEXT: v_mov_b32_e32 v1, 0475; SI-NEXT: s_setpc_b64 s[30:31]476;477; VI-LABEL: vector_trunc_high_bits_undef_urem_lhs_alignbit_regression:478; VI: ; %bb.0:479; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)480; VI-NEXT: s_mov_b32 s4, 0x38e38e39481; VI-NEXT: v_mul_hi_u32 v1, v0, s4482; VI-NEXT: v_lshrrev_b32_e32 v1, 2, v1483; VI-NEXT: v_mul_lo_u32 v1, v1, 18484; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1485; VI-NEXT: s_setpc_b64 s[30:31]486 %undef.hi.elt = insertelement <2 x i32> poison, i32 %arg0, i32 0487 %lshr = urem <2 x i32> %undef.hi.elt, splat (i32 18)488 %trunc = trunc <2 x i32> %lshr to <2 x i16>489 ret <2 x i16> %trunc490}491