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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s4 5define amdgpu_kernel void @truncstore_arg_v16i32_to_v16i8(ptr addrspace(1) %out, <16 x i32> %in) {6; SI-LABEL: truncstore_arg_v16i32_to_v16i8:7; SI: ; %bb.0:8; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x199; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x910; SI-NEXT: s_mov_b32 s3, 0xf00011; SI-NEXT: s_mov_b32 s2, -112; SI-NEXT: s_waitcnt lgkmcnt(0)13; SI-NEXT: s_and_b32 s5, s22, 0xff14; SI-NEXT: s_lshl_b32 s4, s23, 2415; SI-NEXT: s_lshl_b32 s5, s5, 1616; SI-NEXT: s_or_b32 s4, s4, s517; SI-NEXT: s_lshl_b32 s5, s21, 818; SI-NEXT: s_and_b32 s6, s20, 0xff19; SI-NEXT: s_or_b32 s5, s6, s520; SI-NEXT: s_and_b32 s5, s5, 0xffff21; SI-NEXT: s_and_b32 s6, s18, 0xff22; SI-NEXT: s_or_b32 s4, s5, s423; SI-NEXT: s_lshl_b32 s5, s19, 2424; SI-NEXT: s_lshl_b32 s6, s6, 1625; SI-NEXT: s_or_b32 s5, s5, s626; SI-NEXT: s_lshl_b32 s6, s17, 827; SI-NEXT: s_and_b32 s7, s16, 0xff28; SI-NEXT: s_or_b32 s6, s7, s629; SI-NEXT: s_and_b32 s6, s6, 0xffff30; SI-NEXT: s_and_b32 s7, s14, 0xff31; SI-NEXT: s_or_b32 s5, s6, s532; SI-NEXT: s_lshl_b32 s6, s15, 2433; SI-NEXT: s_lshl_b32 s7, s7, 1634; SI-NEXT: s_or_b32 s6, s6, s735; SI-NEXT: s_lshl_b32 s7, s13, 836; SI-NEXT: s_and_b32 s12, s12, 0xff37; SI-NEXT: s_or_b32 s7, s12, s738; SI-NEXT: s_and_b32 s7, s7, 0xffff39; SI-NEXT: s_and_b32 s10, s10, 0xff40; SI-NEXT: s_lshl_b32 s9, s9, 841; SI-NEXT: s_and_b32 s8, s8, 0xff42; SI-NEXT: s_or_b32 s6, s7, s643; SI-NEXT: s_lshl_b32 s7, s11, 2444; SI-NEXT: s_lshl_b32 s10, s10, 1645; SI-NEXT: s_or_b32 s8, s8, s946; SI-NEXT: s_or_b32 s7, s7, s1047; SI-NEXT: s_and_b32 s8, s8, 0xffff48; SI-NEXT: s_or_b32 s7, s8, s749; SI-NEXT: v_mov_b32_e32 v0, s750; SI-NEXT: v_mov_b32_e32 v1, s651; SI-NEXT: v_mov_b32_e32 v2, s552; SI-NEXT: v_mov_b32_e32 v3, s453; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 054; SI-NEXT: s_endpgm55;56; VI-LABEL: truncstore_arg_v16i32_to_v16i8:57; VI: ; %bb.0:58; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x6459; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2460; VI-NEXT: s_waitcnt lgkmcnt(0)61; VI-NEXT: s_lshl_b32 s2, s23, 862; VI-NEXT: s_and_b32 s3, s22, 0xff63; VI-NEXT: s_lshl_b32 s4, s21, 864; VI-NEXT: s_and_b32 s5, s20, 0xff65; VI-NEXT: s_or_b32 s2, s3, s266; VI-NEXT: s_or_b32 s3, s5, s467; VI-NEXT: s_lshl_b32 s2, s2, 1668; VI-NEXT: s_and_b32 s3, s3, 0xffff69; VI-NEXT: s_or_b32 s2, s3, s270; VI-NEXT: s_lshl_b32 s3, s19, 871; VI-NEXT: s_and_b32 s4, s18, 0xff72; VI-NEXT: s_or_b32 s3, s4, s373; VI-NEXT: s_lshl_b32 s4, s17, 874; VI-NEXT: s_and_b32 s5, s16, 0xff75; VI-NEXT: s_or_b32 s4, s5, s476; VI-NEXT: s_lshl_b32 s3, s3, 1677; VI-NEXT: s_and_b32 s4, s4, 0xffff78; VI-NEXT: s_or_b32 s3, s4, s379; VI-NEXT: s_lshl_b32 s4, s15, 880; VI-NEXT: s_and_b32 s5, s14, 0xff81; VI-NEXT: s_or_b32 s4, s5, s482; VI-NEXT: s_lshl_b32 s5, s13, 883; VI-NEXT: s_and_b32 s6, s12, 0xff84; VI-NEXT: s_or_b32 s5, s6, s585; VI-NEXT: s_lshl_b32 s4, s4, 1686; VI-NEXT: s_and_b32 s5, s5, 0xffff87; VI-NEXT: s_or_b32 s4, s5, s488; VI-NEXT: s_lshl_b32 s5, s11, 889; VI-NEXT: s_and_b32 s6, s10, 0xff90; VI-NEXT: s_or_b32 s5, s6, s591; VI-NEXT: s_lshl_b32 s6, s9, 892; VI-NEXT: s_and_b32 s7, s8, 0xff93; VI-NEXT: s_or_b32 s6, s7, s694; VI-NEXT: s_lshl_b32 s5, s5, 1695; VI-NEXT: s_and_b32 s6, s6, 0xffff96; VI-NEXT: s_or_b32 s5, s6, s597; VI-NEXT: v_mov_b32_e32 v5, s198; VI-NEXT: v_mov_b32_e32 v0, s599; VI-NEXT: v_mov_b32_e32 v1, s4100; VI-NEXT: v_mov_b32_e32 v2, s3101; VI-NEXT: v_mov_b32_e32 v3, s2102; VI-NEXT: v_mov_b32_e32 v4, s0103; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]104; VI-NEXT: s_endpgm105 %trunc = trunc <16 x i32> %in to <16 x i8>106 store <16 x i8> %trunc, ptr addrspace(1) %out107 ret void108}109 110define amdgpu_kernel void @truncstore_arg_v16i64_to_v16i8(ptr addrspace(1) %out, <16 x i64> %in) {111; SI-LABEL: truncstore_arg_v16i64_to_v16i8:112; SI: ; %bb.0:113; SI-NEXT: s_load_dwordx16 s[16:31], s[4:5], 0x39114; SI-NEXT: s_load_dwordx2 s[36:37], s[4:5], 0x9115; SI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0x29116; SI-NEXT: s_mov_b32 s39, 0xf000117; SI-NEXT: s_mov_b32 s38, -1118; SI-NEXT: s_waitcnt lgkmcnt(0)119; SI-NEXT: s_and_b32 s3, s28, 0xff120; SI-NEXT: s_lshl_b32 s1, s30, 24121; SI-NEXT: s_lshl_b32 s3, s3, 16122; SI-NEXT: s_or_b32 s1, s1, s3123; SI-NEXT: s_lshl_b32 s3, s26, 8124; SI-NEXT: s_and_b32 s5, s24, 0xff125; SI-NEXT: s_or_b32 s3, s5, s3126; SI-NEXT: s_and_b32 s3, s3, 0xffff127; SI-NEXT: s_and_b32 s5, s20, 0xff128; SI-NEXT: s_or_b32 s1, s3, s1129; SI-NEXT: s_lshl_b32 s3, s22, 24130; SI-NEXT: s_lshl_b32 s5, s5, 16131; SI-NEXT: s_or_b32 s3, s3, s5132; SI-NEXT: s_lshl_b32 s5, s18, 8133; SI-NEXT: s_and_b32 s7, s16, 0xff134; SI-NEXT: s_or_b32 s5, s7, s5135; SI-NEXT: s_and_b32 s5, s5, 0xffff136; SI-NEXT: s_and_b32 s7, s12, 0xff137; SI-NEXT: s_or_b32 s3, s5, s3138; SI-NEXT: s_lshl_b32 s5, s14, 24139; SI-NEXT: s_lshl_b32 s7, s7, 16140; SI-NEXT: s_or_b32 s5, s5, s7141; SI-NEXT: s_lshl_b32 s7, s10, 8142; SI-NEXT: s_and_b32 s8, s8, 0xff143; SI-NEXT: s_and_b32 s4, s4, 0xff144; SI-NEXT: s_lshl_b32 s2, s2, 8145; SI-NEXT: s_and_b32 s0, s0, 0xff146; SI-NEXT: s_or_b32 s7, s8, s7147; SI-NEXT: s_lshl_b32 s6, s6, 24148; SI-NEXT: s_lshl_b32 s4, s4, 16149; SI-NEXT: s_or_b32 s0, s0, s2150; SI-NEXT: s_and_b32 s7, s7, 0xffff151; SI-NEXT: s_or_b32 s4, s6, s4152; SI-NEXT: s_and_b32 s0, s0, 0xffff153; SI-NEXT: s_or_b32 s5, s7, s5154; SI-NEXT: s_or_b32 s0, s0, s4155; SI-NEXT: v_mov_b32_e32 v0, s0156; SI-NEXT: v_mov_b32_e32 v1, s5157; SI-NEXT: v_mov_b32_e32 v2, s3158; SI-NEXT: v_mov_b32_e32 v3, s1159; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0160; SI-NEXT: s_endpgm161;162; VI-LABEL: truncstore_arg_v16i64_to_v16i8:163; VI: ; %bb.0:164; VI-NEXT: s_load_dwordx16 s[16:31], s[4:5], 0xe4165; VI-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24166; VI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0xa4167; VI-NEXT: s_waitcnt lgkmcnt(0)168; VI-NEXT: s_lshl_b32 s1, s30, 8169; VI-NEXT: s_and_b32 s3, s28, 0xff170; VI-NEXT: s_lshl_b32 s5, s26, 8171; VI-NEXT: s_or_b32 s1, s3, s1172; VI-NEXT: s_and_b32 s3, s24, 0xff173; VI-NEXT: s_or_b32 s3, s3, s5174; VI-NEXT: s_lshl_b32 s1, s1, 16175; VI-NEXT: s_and_b32 s3, s3, 0xffff176; VI-NEXT: s_or_b32 s1, s3, s1177; VI-NEXT: s_lshl_b32 s3, s22, 8178; VI-NEXT: s_and_b32 s5, s20, 0xff179; VI-NEXT: s_or_b32 s3, s5, s3180; VI-NEXT: s_lshl_b32 s5, s18, 8181; VI-NEXT: s_and_b32 s7, s16, 0xff182; VI-NEXT: s_or_b32 s5, s7, s5183; VI-NEXT: s_lshl_b32 s3, s3, 16184; VI-NEXT: s_and_b32 s5, s5, 0xffff185; VI-NEXT: s_or_b32 s3, s5, s3186; VI-NEXT: s_lshl_b32 s5, s14, 8187; VI-NEXT: s_and_b32 s7, s12, 0xff188; VI-NEXT: s_or_b32 s5, s7, s5189; VI-NEXT: s_lshl_b32 s7, s10, 8190; VI-NEXT: s_and_b32 s8, s8, 0xff191; VI-NEXT: s_lshl_b32 s6, s6, 8192; VI-NEXT: s_and_b32 s4, s4, 0xff193; VI-NEXT: s_lshl_b32 s2, s2, 8194; VI-NEXT: s_and_b32 s0, s0, 0xff195; VI-NEXT: s_or_b32 s7, s8, s7196; VI-NEXT: s_or_b32 s4, s4, s6197; VI-NEXT: s_or_b32 s0, s0, s2198; VI-NEXT: s_lshl_b32 s5, s5, 16199; VI-NEXT: s_and_b32 s7, s7, 0xffff200; VI-NEXT: s_lshl_b32 s4, s4, 16201; VI-NEXT: s_and_b32 s0, s0, 0xffff202; VI-NEXT: s_or_b32 s5, s7, s5203; VI-NEXT: s_or_b32 s0, s0, s4204; VI-NEXT: v_mov_b32_e32 v4, s34205; VI-NEXT: v_mov_b32_e32 v0, s0206; VI-NEXT: v_mov_b32_e32 v1, s5207; VI-NEXT: v_mov_b32_e32 v2, s3208; VI-NEXT: v_mov_b32_e32 v3, s1209; VI-NEXT: v_mov_b32_e32 v5, s35210; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]211; VI-NEXT: s_endpgm212 %trunc = trunc <16 x i64> %in to <16 x i8>213 store <16 x i8> %trunc, ptr addrspace(1) %out214 ret void215}216 217define void @truncstore_v5i32_to_v5i1(ptr addrspace(1) %out, <5 x i32> %val) {218; SI-LABEL: truncstore_v5i32_to_v5i1:219; SI: ; %bb.0:220; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)221; SI-NEXT: v_and_b32_e32 v3, 1, v3222; SI-NEXT: v_and_b32_e32 v2, 1, v2223; SI-NEXT: v_lshlrev_b32_e32 v3, 1, v3224; SI-NEXT: v_or_b32_e32 v2, v2, v3225; SI-NEXT: v_and_b32_e32 v3, 1, v4226; SI-NEXT: v_lshlrev_b32_e32 v3, 2, v3227; SI-NEXT: v_or_b32_e32 v2, v2, v3228; SI-NEXT: v_and_b32_e32 v3, 1, v5229; SI-NEXT: v_lshlrev_b32_e32 v3, 3, v3230; SI-NEXT: v_or_b32_e32 v2, v2, v3231; SI-NEXT: v_lshlrev_b32_e32 v3, 4, v6232; SI-NEXT: s_mov_b32 s6, 0233; SI-NEXT: v_or_b32_e32 v2, v2, v3234; SI-NEXT: s_mov_b32 s7, 0xf000235; SI-NEXT: s_mov_b32 s4, s6236; SI-NEXT: s_mov_b32 s5, s6237; SI-NEXT: v_and_b32_e32 v2, 31, v2238; SI-NEXT: buffer_store_byte v2, v[0:1], s[4:7], 0 addr64239; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)240; SI-NEXT: s_setpc_b64 s[30:31]241;242; VI-LABEL: truncstore_v5i32_to_v5i1:243; VI: ; %bb.0:244; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)245; VI-NEXT: v_and_b32_e32 v3, 1, v3246; VI-NEXT: v_and_b32_e32 v2, 1, v2247; VI-NEXT: v_lshlrev_b16_e32 v3, 1, v3248; VI-NEXT: v_or_b32_e32 v2, v2, v3249; VI-NEXT: v_and_b32_e32 v3, 1, v4250; VI-NEXT: v_lshlrev_b16_e32 v3, 2, v3251; VI-NEXT: v_or_b32_e32 v2, v2, v3252; VI-NEXT: v_and_b32_e32 v3, 1, v5253; VI-NEXT: v_lshlrev_b16_e32 v3, 3, v3254; VI-NEXT: v_or_b32_e32 v2, v2, v3255; VI-NEXT: v_lshlrev_b16_e32 v3, 4, v6256; VI-NEXT: v_or_b32_e32 v2, v2, v3257; VI-NEXT: v_and_b32_e32 v2, 31, v2258; VI-NEXT: flat_store_byte v[0:1], v2259; VI-NEXT: s_waitcnt vmcnt(0)260; VI-NEXT: s_setpc_b64 s[30:31]261 %trunc = trunc <5 x i32> %val to <5 x i1>262 store <5 x i1> %trunc, ptr addrspace(1) %out263 ret void264}265 266define void @truncstore_v5i32_to_v5i8(ptr addrspace(1) %out, <5 x i32> %val) {267; SI-LABEL: truncstore_v5i32_to_v5i8:268; SI: ; %bb.0:269; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)270; SI-NEXT: v_and_b32_e32 v4, 0xff, v4271; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3272; SI-NEXT: v_and_b32_e32 v2, 0xff, v2273; SI-NEXT: s_mov_b32 s6, 0274; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5275; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4276; SI-NEXT: v_or_b32_e32 v2, v2, v3277; SI-NEXT: s_mov_b32 s7, 0xf000278; SI-NEXT: s_mov_b32 s4, s6279; SI-NEXT: s_mov_b32 s5, s6280; SI-NEXT: v_or_b32_e32 v4, v5, v4281; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2282; SI-NEXT: v_or_b32_e32 v2, v2, v4283; SI-NEXT: buffer_store_byte v6, v[0:1], s[4:7], 0 addr64 offset:4284; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64285; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)286; SI-NEXT: s_setpc_b64 s[30:31]287;288; VI-LABEL: truncstore_v5i32_to_v5i8:289; VI: ; %bb.0:290; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)291; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3292; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD293; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v5294; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD295; VI-NEXT: v_or_b32_sdwa v4, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD296; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0297; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc298; VI-NEXT: flat_store_byte v[2:3], v6299; VI-NEXT: flat_store_dword v[0:1], v4300; VI-NEXT: s_waitcnt vmcnt(0)301; VI-NEXT: s_setpc_b64 s[30:31]302 %trunc = trunc <5 x i32> %val to <5 x i8>303 store <5 x i8> %trunc, ptr addrspace(1) %out304 ret void305}306 307define void @truncstore_v6i32_to_v6i1(ptr addrspace(1) %out, <6 x i32> %val) {308; SI-LABEL: truncstore_v6i32_to_v6i1:309; SI: ; %bb.0:310; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)311; SI-NEXT: v_and_b32_e32 v3, 1, v3312; SI-NEXT: v_and_b32_e32 v2, 1, v2313; SI-NEXT: v_lshlrev_b32_e32 v3, 1, v3314; SI-NEXT: v_or_b32_e32 v2, v2, v3315; SI-NEXT: v_and_b32_e32 v3, 1, v4316; SI-NEXT: v_lshlrev_b32_e32 v3, 2, v3317; SI-NEXT: v_or_b32_e32 v2, v2, v3318; SI-NEXT: v_and_b32_e32 v3, 1, v5319; SI-NEXT: v_lshlrev_b32_e32 v3, 3, v3320; SI-NEXT: v_or_b32_e32 v2, v2, v3321; SI-NEXT: v_and_b32_e32 v3, 1, v6322; SI-NEXT: v_lshlrev_b32_e32 v3, 4, v3323; SI-NEXT: v_or_b32_e32 v2, v2, v3324; SI-NEXT: v_lshlrev_b32_e32 v3, 5, v7325; SI-NEXT: s_mov_b32 s6, 0326; SI-NEXT: v_or_b32_e32 v2, v2, v3327; SI-NEXT: s_mov_b32 s7, 0xf000328; SI-NEXT: s_mov_b32 s4, s6329; SI-NEXT: s_mov_b32 s5, s6330; SI-NEXT: v_and_b32_e32 v2, 63, v2331; SI-NEXT: buffer_store_byte v2, v[0:1], s[4:7], 0 addr64332; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)333; SI-NEXT: s_setpc_b64 s[30:31]334;335; VI-LABEL: truncstore_v6i32_to_v6i1:336; VI: ; %bb.0:337; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)338; VI-NEXT: v_and_b32_e32 v3, 1, v3339; VI-NEXT: v_and_b32_e32 v2, 1, v2340; VI-NEXT: v_lshlrev_b16_e32 v3, 1, v3341; VI-NEXT: v_or_b32_e32 v2, v2, v3342; VI-NEXT: v_and_b32_e32 v3, 1, v4343; VI-NEXT: v_lshlrev_b16_e32 v3, 2, v3344; VI-NEXT: v_or_b32_e32 v2, v2, v3345; VI-NEXT: v_and_b32_e32 v3, 1, v5346; VI-NEXT: v_lshlrev_b16_e32 v3, 3, v3347; VI-NEXT: v_or_b32_e32 v2, v2, v3348; VI-NEXT: v_and_b32_e32 v3, 1, v6349; VI-NEXT: v_lshlrev_b16_e32 v3, 4, v3350; VI-NEXT: v_or_b32_e32 v2, v2, v3351; VI-NEXT: v_lshlrev_b16_e32 v3, 5, v7352; VI-NEXT: v_or_b32_e32 v2, v2, v3353; VI-NEXT: v_and_b32_e32 v2, 63, v2354; VI-NEXT: flat_store_byte v[0:1], v2355; VI-NEXT: s_waitcnt vmcnt(0)356; VI-NEXT: s_setpc_b64 s[30:31]357 %trunc = trunc <6 x i32> %val to <6 x i1>358 store <6 x i1> %trunc, ptr addrspace(1) %out359 ret void360}361 362define void @truncstore_v6i32_to_v6i8(ptr addrspace(1) %out, <6 x i32> %val) {363; SI-LABEL: truncstore_v6i32_to_v6i8:364; SI: ; %bb.0:365; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)366; SI-NEXT: v_and_b32_e32 v4, 0xff, v4367; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3368; SI-NEXT: v_and_b32_e32 v2, 0xff, v2369; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5370; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4371; SI-NEXT: v_or_b32_e32 v2, v2, v3372; SI-NEXT: v_or_b32_e32 v4, v5, v4373; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2374; SI-NEXT: s_mov_b32 s6, 0375; SI-NEXT: v_or_b32_e32 v2, v2, v4376; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v7377; SI-NEXT: v_and_b32_e32 v4, 0xff, v6378; SI-NEXT: s_mov_b32 s7, 0xf000379; SI-NEXT: s_mov_b32 s4, s6380; SI-NEXT: s_mov_b32 s5, s6381; SI-NEXT: v_or_b32_e32 v3, v4, v3382; SI-NEXT: buffer_store_short v3, v[0:1], s[4:7], 0 addr64 offset:4383; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64384; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)385; SI-NEXT: s_setpc_b64 s[30:31]386;387; VI-LABEL: truncstore_v6i32_to_v6i8:388; VI: ; %bb.0:389; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)390; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3391; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD392; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v5393; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD394; VI-NEXT: v_or_b32_sdwa v4, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD395; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v7396; VI-NEXT: v_or_b32_sdwa v5, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD397; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0398; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc399; VI-NEXT: flat_store_short v[2:3], v5400; VI-NEXT: flat_store_dword v[0:1], v4401; VI-NEXT: s_waitcnt vmcnt(0)402; VI-NEXT: s_setpc_b64 s[30:31]403 %trunc = trunc <6 x i32> %val to <6 x i8>404 store <6 x i8> %trunc, ptr addrspace(1) %out405 ret void406}407 408define void @truncstore_v6i32_to_v6i16(ptr addrspace(1) %out, <6 x i32> %val) {409; SI-LABEL: truncstore_v6i32_to_v6i16:410; SI: ; %bb.0:411; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)412; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5413; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4414; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3415; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2416; SI-NEXT: s_mov_b32 s6, 0417; SI-NEXT: v_or_b32_e32 v4, v4, v5418; SI-NEXT: v_or_b32_e32 v3, v2, v3419; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v7420; SI-NEXT: v_and_b32_e32 v5, 0xffff, v6421; SI-NEXT: s_mov_b32 s7, 0xf000422; SI-NEXT: s_mov_b32 s4, s6423; SI-NEXT: s_mov_b32 s5, s6424; SI-NEXT: v_or_b32_e32 v2, v5, v2425; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:8426; SI-NEXT: buffer_store_dwordx2 v[3:4], v[0:1], s[4:7], 0 addr64427; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)428; SI-NEXT: s_setpc_b64 s[30:31]429;430; VI-LABEL: truncstore_v6i32_to_v6i16:431; VI: ; %bb.0:432; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)433; VI-NEXT: s_mov_b32 s4, 0x1000504434; VI-NEXT: v_perm_b32 v6, v6, v7, s4435; VI-NEXT: v_perm_b32 v5, v4, v5, s4436; VI-NEXT: v_perm_b32 v4, v2, v3, s4437; VI-NEXT: flat_store_dwordx3 v[0:1], v[4:6]438; VI-NEXT: s_waitcnt vmcnt(0)439; VI-NEXT: s_setpc_b64 s[30:31]440 %trunc = trunc <6 x i32> %val to <6 x i16>441 store <6 x i16> %trunc, ptr addrspace(1) %out442 ret void443}444 445;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:446; GCN: {{.*}}447