496 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s3; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s4; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s5 6declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone7 8define amdgpu_kernel void @trunc_i64_to_i32_store(ptr addrspace(1) %out, [8 x i32], i64 %in) {9; SI-LABEL: trunc_i64_to_i32_store:10; SI: ; %bb.0:11; SI-NEXT: s_load_dword s6, s[4:5], 0x1312; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x913; SI-NEXT: s_mov_b32 s3, 0xf00014; SI-NEXT: s_mov_b32 s2, -115; SI-NEXT: s_waitcnt lgkmcnt(0)16; SI-NEXT: v_mov_b32_e32 v0, s617; SI-NEXT: buffer_store_dword v0, off, s[0:3], 018; SI-NEXT: s_endpgm19;20; VI-LABEL: trunc_i64_to_i32_store:21; VI: ; %bb.0:22; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2423; VI-NEXT: s_load_dword s2, s[4:5], 0x4c24; VI-NEXT: s_waitcnt lgkmcnt(0)25; VI-NEXT: v_mov_b32_e32 v0, s026; VI-NEXT: v_mov_b32_e32 v1, s127; VI-NEXT: v_mov_b32_e32 v2, s228; VI-NEXT: flat_store_dword v[0:1], v229; VI-NEXT: s_endpgm30;31; EG-LABEL: trunc_i64_to_i32_store:32; EG: ; %bb.0:33; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]34; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 135; EG-NEXT: CF_END36; EG-NEXT: PAD37; EG-NEXT: ALU clause starting at 4:38; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,39; EG-NEXT: MOV * T1.X, KC0[4].W,40; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)41 %result = trunc i64 %in to i32 store i32 %result, ptr addrspace(1) %out, align 442 ret void43}44 45define amdgpu_kernel void @trunc_load_shl_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {46; SI-LABEL: trunc_load_shl_i64:47; SI: ; %bb.0:48; SI-NEXT: s_load_dword s6, s[4:5], 0x1349; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x950; SI-NEXT: s_mov_b32 s3, 0xf00051; SI-NEXT: s_mov_b32 s2, -152; SI-NEXT: s_waitcnt lgkmcnt(0)53; SI-NEXT: s_lshl_b32 s4, s6, 254; SI-NEXT: v_mov_b32_e32 v0, s455; SI-NEXT: buffer_store_dword v0, off, s[0:3], 056; SI-NEXT: s_endpgm57;58; VI-LABEL: trunc_load_shl_i64:59; VI: ; %bb.0:60; VI-NEXT: s_load_dword s2, s[4:5], 0x4c61; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2462; VI-NEXT: s_waitcnt lgkmcnt(0)63; VI-NEXT: s_lshl_b32 s2, s2, 264; VI-NEXT: v_mov_b32_e32 v0, s065; VI-NEXT: v_mov_b32_e32 v1, s166; VI-NEXT: v_mov_b32_e32 v2, s267; VI-NEXT: flat_store_dword v[0:1], v268; VI-NEXT: s_endpgm69;70; EG-LABEL: trunc_load_shl_i64:71; EG: ; %bb.0:72; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]73; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 174; EG-NEXT: CF_END75; EG-NEXT: PAD76; EG-NEXT: ALU clause starting at 4:77; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,78; EG-NEXT: LSHL * T1.X, KC0[4].W, literal.x,79; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)80 %b = shl i64 %a, 281 %result = trunc i64 %b to i3282 store i32 %result, ptr addrspace(1) %out, align 483 ret void84}85 86define amdgpu_kernel void @trunc_shl_i64(ptr addrspace(1) %out2, ptr addrspace(1) %out, i64 %a) {87; SI-LABEL: trunc_shl_i64:88; SI: ; %bb.0:89; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x990; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd91; SI-NEXT: s_mov_b32 s7, 0xf00092; SI-NEXT: s_mov_b32 s6, -193; SI-NEXT: s_waitcnt lgkmcnt(0)94; SI-NEXT: s_mov_b32 s4, s095; SI-NEXT: s_lshl_b64 s[8:9], s[8:9], 296; SI-NEXT: s_add_u32 s8, s8, 0x3a897; SI-NEXT: s_mov_b32 s5, s198; SI-NEXT: s_mov_b32 s0, s299; SI-NEXT: s_mov_b32 s1, s3100; SI-NEXT: s_mov_b32 s2, s6101; SI-NEXT: s_mov_b32 s3, s7102; SI-NEXT: v_mov_b32_e32 v0, s8103; SI-NEXT: s_addc_u32 s9, s9, 0104; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0105; SI-NEXT: s_waitcnt expcnt(0)106; SI-NEXT: v_mov_b32_e32 v0, s8107; SI-NEXT: v_mov_b32_e32 v1, s9108; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0109; SI-NEXT: s_endpgm110;111; VI-LABEL: trunc_shl_i64:112; VI: ; %bb.0:113; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24114; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34115; VI-NEXT: s_waitcnt lgkmcnt(0)116; VI-NEXT: v_mov_b32_e32 v0, s0117; VI-NEXT: v_mov_b32_e32 v1, s1118; VI-NEXT: s_lshl_b64 s[0:1], s[4:5], 2119; VI-NEXT: s_add_u32 s0, s0, 0x3a8120; VI-NEXT: v_mov_b32_e32 v2, s2121; VI-NEXT: v_mov_b32_e32 v3, s3122; VI-NEXT: s_addc_u32 s1, s1, 0123; VI-NEXT: v_mov_b32_e32 v4, s0124; VI-NEXT: flat_store_dword v[2:3], v4125; VI-NEXT: v_mov_b32_e32 v3, s1126; VI-NEXT: v_mov_b32_e32 v2, s0127; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]128; VI-NEXT: s_endpgm129;130; EG-LABEL: trunc_shl_i64:131; EG: ; %bb.0:132; EG-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]133; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0134; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1135; EG-NEXT: CF_END136; EG-NEXT: ALU clause starting at 4:137; EG-NEXT: LSHL * T0.W, KC0[2].W, literal.x,138; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)139; EG-NEXT: BIT_ALIGN_INT T1.W, KC0[3].X, KC0[2].W, literal.x,140; EG-NEXT: ADDC_UINT * T2.W, PV.W, literal.y,141; EG-NEXT: 30(4.203895e-44), 936(1.311615e-42)142; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,143; EG-NEXT: ADD_INT T1.Y, PV.W, PS,144; EG-NEXT: ADD_INT * T1.X, T0.W, literal.y,145; EG-NEXT: 2(2.802597e-45), 936(1.311615e-42)146; EG-NEXT: LSHR * T2.X, KC0[2].Z, literal.x,147; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)148 %aa = add i64 %a, 234 ; Prevent shrinking store.149 %b = shl i64 %aa, 2150 %result = trunc i64 %b to i32151 store i32 %result, ptr addrspace(1) %out, align 4152 store i64 %b, ptr addrspace(1) %out2, align 8 ; Prevent reducing ops to 32-bits153 ret void154}155 156define amdgpu_kernel void @trunc_i32_to_i1(ptr addrspace(1) %out, ptr addrspace(1) %ptr) {157; SI-LABEL: trunc_i32_to_i1:158; SI: ; %bb.0:159; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9160; SI-NEXT: s_mov_b32 s7, 0xf000161; SI-NEXT: s_mov_b32 s6, -1162; SI-NEXT: s_mov_b32 s10, s6163; SI-NEXT: s_mov_b32 s11, s7164; SI-NEXT: s_waitcnt lgkmcnt(0)165; SI-NEXT: s_mov_b32 s8, s2166; SI-NEXT: s_mov_b32 s9, s3167; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0168; SI-NEXT: s_mov_b32 s4, s0169; SI-NEXT: s_mov_b32 s5, s1170; SI-NEXT: s_waitcnt vmcnt(0)171; SI-NEXT: v_and_b32_e32 v0, 1, v0172; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0173; SI-NEXT: s_endpgm174;175; VI-LABEL: trunc_i32_to_i1:176; VI: ; %bb.0:177; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24178; VI-NEXT: s_waitcnt lgkmcnt(0)179; VI-NEXT: v_mov_b32_e32 v0, s2180; VI-NEXT: v_mov_b32_e32 v1, s3181; VI-NEXT: flat_load_dword v2, v[0:1]182; VI-NEXT: v_mov_b32_e32 v0, s0183; VI-NEXT: v_mov_b32_e32 v1, s1184; VI-NEXT: s_waitcnt vmcnt(0)185; VI-NEXT: v_and_b32_e32 v2, 1, v2186; VI-NEXT: flat_store_dword v[0:1], v2187; VI-NEXT: s_endpgm188;189; EG-LABEL: trunc_i32_to_i1:190; EG: ; %bb.0:191; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]192; EG-NEXT: TEX 0 @6193; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]194; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1195; EG-NEXT: CF_END196; EG-NEXT: PAD197; EG-NEXT: Fetch clause starting at 6:198; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1199; EG-NEXT: ALU clause starting at 8:200; EG-NEXT: MOV * T0.X, KC0[2].Z,201; EG-NEXT: ALU clause starting at 9:202; EG-NEXT: AND_INT T0.X, T0.X, 1,203; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,204; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)205 %a = load i32, ptr addrspace(1) %ptr, align 4206 %trunc = trunc i32 %a to i1207 %result = select i1 %trunc, i32 1, i32 0208 store i32 %result, ptr addrspace(1) %out, align 4209 ret void210}211 212define amdgpu_kernel void @trunc_i8_to_i1(ptr addrspace(1) %out, ptr addrspace(1) %ptr) {213; SI-LABEL: trunc_i8_to_i1:214; SI: ; %bb.0:215; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9216; SI-NEXT: s_mov_b32 s7, 0xf000217; SI-NEXT: s_mov_b32 s6, -1218; SI-NEXT: s_mov_b32 s10, s6219; SI-NEXT: s_mov_b32 s11, s7220; SI-NEXT: s_waitcnt lgkmcnt(0)221; SI-NEXT: s_mov_b32 s8, s2222; SI-NEXT: s_mov_b32 s9, s3223; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0224; SI-NEXT: s_mov_b32 s4, s0225; SI-NEXT: s_mov_b32 s5, s1226; SI-NEXT: s_waitcnt vmcnt(0)227; SI-NEXT: v_and_b32_e32 v0, 1, v0228; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0229; SI-NEXT: s_endpgm230;231; VI-LABEL: trunc_i8_to_i1:232; VI: ; %bb.0:233; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24234; VI-NEXT: s_waitcnt lgkmcnt(0)235; VI-NEXT: v_mov_b32_e32 v0, s2236; VI-NEXT: v_mov_b32_e32 v1, s3237; VI-NEXT: flat_load_ubyte v2, v[0:1]238; VI-NEXT: v_mov_b32_e32 v0, s0239; VI-NEXT: v_mov_b32_e32 v1, s1240; VI-NEXT: s_waitcnt vmcnt(0)241; VI-NEXT: v_and_b32_e32 v2, 1, v2242; VI-NEXT: flat_store_byte v[0:1], v2243; VI-NEXT: s_endpgm244;245; EG-LABEL: trunc_i8_to_i1:246; EG: ; %bb.0:247; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]248; EG-NEXT: TEX 0 @6249; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]250; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X251; EG-NEXT: CF_END252; EG-NEXT: PAD253; EG-NEXT: Fetch clause starting at 6:254; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1255; EG-NEXT: ALU clause starting at 8:256; EG-NEXT: MOV * T0.X, KC0[2].Z,257; EG-NEXT: ALU clause starting at 9:258; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,259; EG-NEXT: AND_INT * T1.W, T0.X, 1,260; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)261; EG-NEXT: LSHL * T0.W, PV.W, literal.x,262; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)263; EG-NEXT: LSHL T0.X, T1.W, PV.W,264; EG-NEXT: LSHL * T0.W, literal.x, PV.W,265; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)266; EG-NEXT: MOV T0.Y, 0.0,267; EG-NEXT: MOV * T0.Z, 0.0,268; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,269; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)270 %a = load i8, ptr addrspace(1) %ptr, align 4271 %trunc = trunc i8 %a to i1272 %result = select i1 %trunc, i8 1, i8 0273 store i8 %result, ptr addrspace(1) %out, align 4274 ret void275}276 277define amdgpu_kernel void @sgpr_trunc_i16_to_i1(ptr addrspace(1) %out, i16 %a) {278; SI-LABEL: sgpr_trunc_i16_to_i1:279; SI: ; %bb.0:280; SI-NEXT: s_load_dword s6, s[4:5], 0xb281; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9282; SI-NEXT: s_mov_b32 s3, 0xf000283; SI-NEXT: s_mov_b32 s2, -1284; SI-NEXT: s_waitcnt lgkmcnt(0)285; SI-NEXT: s_and_b32 s4, s6, 1286; SI-NEXT: v_mov_b32_e32 v0, s4287; SI-NEXT: buffer_store_short v0, off, s[0:3], 0288; SI-NEXT: s_endpgm289;290; VI-LABEL: sgpr_trunc_i16_to_i1:291; VI: ; %bb.0:292; VI-NEXT: s_load_dword s2, s[4:5], 0x2c293; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24294; VI-NEXT: s_waitcnt lgkmcnt(0)295; VI-NEXT: s_and_b32 s2, s2, 1296; VI-NEXT: v_mov_b32_e32 v0, s0297; VI-NEXT: v_mov_b32_e32 v1, s1298; VI-NEXT: v_mov_b32_e32 v2, s2299; VI-NEXT: flat_store_short v[0:1], v2300; VI-NEXT: s_endpgm301;302; EG-LABEL: sgpr_trunc_i16_to_i1:303; EG: ; %bb.0:304; EG-NEXT: ALU 0, @8, KC0[], KC1[]305; EG-NEXT: TEX 0 @6306; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]307; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X308; EG-NEXT: CF_END309; EG-NEXT: PAD310; EG-NEXT: Fetch clause starting at 6:311; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3312; EG-NEXT: ALU clause starting at 8:313; EG-NEXT: MOV * T0.X, 0.0,314; EG-NEXT: ALU clause starting at 9:315; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,316; EG-NEXT: AND_INT * T1.W, T0.X, 1,317; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)318; EG-NEXT: LSHL * T0.W, PV.W, literal.x,319; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)320; EG-NEXT: LSHL T0.X, T1.W, PV.W,321; EG-NEXT: LSHL * T0.W, literal.x, PV.W,322; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)323; EG-NEXT: MOV T0.Y, 0.0,324; EG-NEXT: MOV * T0.Z, 0.0,325; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,326; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)327 %trunc = trunc i16 %a to i1328 %result = select i1 %trunc, i16 1, i16 0329 store i16 %result, ptr addrspace(1) %out, align 4330 ret void331}332 333define amdgpu_kernel void @sgpr_trunc_i32_to_i1(ptr addrspace(1) %out, i32 %a) {334; SI-LABEL: sgpr_trunc_i32_to_i1:335; SI: ; %bb.0:336; SI-NEXT: s_load_dword s6, s[4:5], 0xb337; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9338; SI-NEXT: s_mov_b32 s3, 0xf000339; SI-NEXT: s_mov_b32 s2, -1340; SI-NEXT: s_waitcnt lgkmcnt(0)341; SI-NEXT: s_and_b32 s4, s6, 1342; SI-NEXT: v_mov_b32_e32 v0, s4343; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0344; SI-NEXT: s_endpgm345;346; VI-LABEL: sgpr_trunc_i32_to_i1:347; VI: ; %bb.0:348; VI-NEXT: s_load_dword s2, s[4:5], 0x2c349; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24350; VI-NEXT: s_waitcnt lgkmcnt(0)351; VI-NEXT: s_and_b32 s2, s2, 1352; VI-NEXT: v_mov_b32_e32 v0, s0353; VI-NEXT: v_mov_b32_e32 v1, s1354; VI-NEXT: v_mov_b32_e32 v2, s2355; VI-NEXT: flat_store_dword v[0:1], v2356; VI-NEXT: s_endpgm357;358; EG-LABEL: sgpr_trunc_i32_to_i1:359; EG: ; %bb.0:360; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]361; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1362; EG-NEXT: CF_END363; EG-NEXT: PAD364; EG-NEXT: ALU clause starting at 4:365; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,366; EG-NEXT: AND_INT * T1.X, KC0[2].Z, 1,367; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)368 %trunc = trunc i32 %a to i1369 %result = select i1 %trunc, i32 1, i32 0370 store i32 %result, ptr addrspace(1) %out, align 4371 ret void372}373 374define amdgpu_kernel void @s_trunc_i64_to_i1(ptr addrspace(1) %out, [8 x i32], i64 %x) {375; SI-LABEL: s_trunc_i64_to_i1:376; SI: ; %bb.0:377; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x13378; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9379; SI-NEXT: s_mov_b32 s3, 0xf000380; SI-NEXT: s_mov_b32 s2, -1381; SI-NEXT: s_waitcnt lgkmcnt(0)382; SI-NEXT: s_bitcmp1_b32 s6, 0383; SI-NEXT: s_cselect_b32 s4, 63, -12384; SI-NEXT: v_mov_b32_e32 v0, s4385; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0386; SI-NEXT: s_endpgm387;388; VI-LABEL: s_trunc_i64_to_i1:389; VI: ; %bb.0:390; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x4c391; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24392; VI-NEXT: s_waitcnt lgkmcnt(0)393; VI-NEXT: s_bitcmp1_b32 s0, 0394; VI-NEXT: s_cselect_b32 s0, 63, -12395; VI-NEXT: v_mov_b32_e32 v0, s2396; VI-NEXT: v_mov_b32_e32 v1, s3397; VI-NEXT: v_mov_b32_e32 v2, s0398; VI-NEXT: flat_store_dword v[0:1], v2399; VI-NEXT: s_endpgm400;401; EG-LABEL: s_trunc_i64_to_i1:402; EG: ; %bb.0:403; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]404; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1405; EG-NEXT: CF_END406; EG-NEXT: PAD407; EG-NEXT: ALU clause starting at 4:408; EG-NEXT: MOV T0.W, literal.x,409; EG-NEXT: AND_INT * T1.W, KC0[4].W, 1,410; EG-NEXT: 63(8.828180e-44), 0(0.000000e+00)411; EG-NEXT: CNDE_INT T0.X, PS, literal.x, PV.W,412; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,413; EG-NEXT: -12(nan), 2(2.802597e-45)414 %trunc = trunc i64 %x to i1415 %sel = select i1 %trunc, i32 63, i32 -12416 store i32 %sel, ptr addrspace(1) %out417 ret void418}419 420define amdgpu_kernel void @v_trunc_i64_to_i1(ptr addrspace(1) %out, ptr addrspace(1) %in) {421; SI-LABEL: v_trunc_i64_to_i1:422; SI: ; %bb.0:423; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9424; SI-NEXT: s_mov_b32 s7, 0xf000425; SI-NEXT: s_mov_b32 s6, 0426; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v0427; SI-NEXT: v_mov_b32_e32 v2, 0428; SI-NEXT: s_waitcnt lgkmcnt(0)429; SI-NEXT: s_mov_b64 s[4:5], s[2:3]430; SI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64431; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0432; SI-NEXT: s_mov_b64 s[2:3], s[6:7]433; SI-NEXT: s_waitcnt vmcnt(0)434; SI-NEXT: v_and_b32_e32 v0, 1, v3435; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0436; SI-NEXT: v_cndmask_b32_e64 v0, -12, 63, vcc437; SI-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64438; SI-NEXT: s_endpgm439;440; VI-LABEL: v_trunc_i64_to_i1:441; VI: ; %bb.0:442; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24443; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0444; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0445; VI-NEXT: s_waitcnt lgkmcnt(0)446; VI-NEXT: v_mov_b32_e32 v2, s3447; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v1448; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc449; VI-NEXT: flat_load_dwordx2 v[1:2], v[1:2]450; VI-NEXT: v_mov_b32_e32 v3, s1451; VI-NEXT: s_waitcnt vmcnt(0)452; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0453; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc454; VI-NEXT: v_and_b32_e32 v0, 1, v1455; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0456; VI-NEXT: v_cndmask_b32_e64 v0, -12, 63, vcc457; VI-NEXT: flat_store_dword v[2:3], v0458; VI-NEXT: s_endpgm459;460; EG-LABEL: v_trunc_i64_to_i1:461; EG: ; %bb.0:462; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]463; EG-NEXT: TEX 0 @6464; EG-NEXT: ALU 8, @11, KC0[CB0:0-32], KC1[]465; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1466; EG-NEXT: CF_END467; EG-NEXT: PAD468; EG-NEXT: Fetch clause starting at 6:469; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1470; EG-NEXT: ALU clause starting at 8:471; EG-NEXT: LSHL * T0.W, T0.X, literal.x,472; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)473; EG-NEXT: ADD_INT * T1.X, KC0[2].Z, PV.W,474; EG-NEXT: ALU clause starting at 11:475; EG-NEXT: LSHL T0.Z, T0.X, literal.x,476; EG-NEXT: AND_INT T0.W, T1.X, 1, BS:VEC_120/SCL_212477; EG-NEXT: MOV * T1.W, literal.y,478; EG-NEXT: 2(2.802597e-45), 63(8.828180e-44)479; EG-NEXT: CNDE_INT T0.X, PV.W, literal.x, PS,480; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, PV.Z,481; EG-NEXT: -12(nan), 0(0.000000e+00)482; EG-NEXT: LSHR * T1.X, PV.W, literal.x,483; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)484 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone485 %gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid486 %out.gep = getelementptr i32, ptr addrspace(1) %out, i32 %tid487 %x = load i64, ptr addrspace(1) %gep488 489 %trunc = trunc i64 %x to i1490 %sel = select i1 %trunc, i32 63, i32 -12491 store i32 %sel, ptr addrspace(1) %out.gep492 ret void493}494;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:495; GCN: {{.*}}496