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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s3 4; extract element 0 as shift5define i32 @cast_v4i32_to_i128_trunc_i32(<4 x i32> %arg) {6; CHECK-LABEL: cast_v4i32_to_i128_trunc_i32:7; CHECK: ; %bb.0:8; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; CHECK-NEXT: s_setpc_b64 s[30:31]10 %bigint = bitcast <4 x i32> %arg to i12811 %trunc = trunc i128 %bigint to i3212 ret i32 %trunc13}14 15; extract element 1 as shift16define i32 @cast_v4i32_to_i128_lshr_32_trunc_i32(<4 x i32> %arg) {17; CHECK-LABEL: cast_v4i32_to_i128_lshr_32_trunc_i32:18; CHECK: ; %bb.0:19; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)20; CHECK-NEXT: v_mov_b32_e32 v0, v121; CHECK-NEXT: s_setpc_b64 s[30:31]22 %bigint = bitcast <4 x i32> %arg to i12823 %srl = lshr i128 %bigint, 3224 %trunc = trunc i128 %srl to i3225 ret i32 %trunc26}27 28; extract element 2 as shift29define i32 @cast_v4i32_to_i128_lshr_64_trunc_i32(<4 x i32> %arg) {30; CHECK-LABEL: cast_v4i32_to_i128_lshr_64_trunc_i32:31; CHECK: ; %bb.0:32; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; CHECK-NEXT: v_mov_b32_e32 v0, v234; CHECK-NEXT: s_setpc_b64 s[30:31]35 %bigint = bitcast <4 x i32> %arg to i12836 %srl = lshr i128 %bigint, 6437 %trunc = trunc i128 %srl to i3238 ret i32 %trunc39}40 41; extract element 3 as shift42define i32 @cast_v4i32_to_i128_lshr_96_trunc_i32(<4 x i32> %arg) {43; CHECK-LABEL: cast_v4i32_to_i128_lshr_96_trunc_i32:44; CHECK: ; %bb.0:45; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; CHECK-NEXT: v_mov_b32_e32 v0, v347; CHECK-NEXT: s_setpc_b64 s[30:31]48 %bigint = bitcast <4 x i32> %arg to i12849 %srl = lshr i128 %bigint, 9650 %trunc = trunc i128 %srl to i3251 ret i32 %trunc52}53 54; Shift not aligned to element, not a simple extract55define i32 @cast_v4i32_to_i128_lshr_33_trunc_i32(<4 x i32> %arg) {56; CHECK-LABEL: cast_v4i32_to_i128_lshr_33_trunc_i32:57; CHECK: ; %bb.0:58; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)59; CHECK-NEXT: v_alignbit_b32 v0, v2, v1, 160; CHECK-NEXT: s_setpc_b64 s[30:31]61 %bigint = bitcast <4 x i32> %arg to i12862 %srl = lshr i128 %bigint, 3363 %trunc = trunc i128 %srl to i3264 ret i32 %trunc65}66 67; extract misaligned element68define i32 @cast_v4i32_to_i128_lshr_31_trunc_i32(<4 x i32> %arg) {69; CHECK-LABEL: cast_v4i32_to_i128_lshr_31_trunc_i32:70; CHECK: ; %bb.0:71; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; CHECK-NEXT: v_alignbit_b32 v0, v1, v0, 3173; CHECK-NEXT: s_setpc_b64 s[30:31]74 %bigint = bitcast <4 x i32> %arg to i12875 %srl = lshr i128 %bigint, 3176 %trunc = trunc i128 %srl to i3277 ret i32 %trunc78}79 80; extract misaligned element81define i32 @cast_v4i32_to_i128_lshr_48_trunc_i32(<4 x i32> %arg) {82; CHECK-LABEL: cast_v4i32_to_i128_lshr_48_trunc_i32:83; CHECK: ; %bb.0:84; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)85; CHECK-NEXT: s_mov_b32 s4, 0x100070686; CHECK-NEXT: v_perm_b32 v0, v1, v2, s487; CHECK-NEXT: s_setpc_b64 s[30:31]88 %bigint = bitcast <4 x i32> %arg to i12889 %srl = lshr i128 %bigint, 4890 %trunc = trunc i128 %srl to i3291 ret i32 %trunc92}93 94; extract elements 1 and 2 with shift95define i64 @cast_v4i32_to_i128_lshr_32_trunc_i64(<4 x i32> %arg) {96; CHECK-LABEL: cast_v4i32_to_i128_lshr_32_trunc_i64:97; CHECK: ; %bb.0:98; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)99; CHECK-NEXT: v_mov_b32_e32 v0, v1100; CHECK-NEXT: v_mov_b32_e32 v1, v2101; CHECK-NEXT: s_setpc_b64 s[30:31]102 %bigint = bitcast <4 x i32> %arg to i128103 %srl = lshr i128 %bigint, 32104 %trunc = trunc i128 %srl to i64105 ret i64 %trunc106}107 108; extract elements 2 and 3 with shift109define i64 @cast_v4i32_to_i128_lshr_64_trunc_i64(<4 x i32> %arg) {110; CHECK-LABEL: cast_v4i32_to_i128_lshr_64_trunc_i64:111; CHECK: ; %bb.0:112; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; CHECK-NEXT: v_mov_b32_e32 v1, v3114; CHECK-NEXT: v_mov_b32_e32 v0, v2115; CHECK-NEXT: s_setpc_b64 s[30:31]116 %bigint = bitcast <4 x i32> %arg to i128117 %srl = lshr i128 %bigint, 64118 %trunc = trunc i128 %srl to i64119 ret i64 %trunc120}121 122; FIXME: We don't process this case because we see multiple bitcasts123; before a 32-bit build_vector124define i32 @build_vector_i16_to_shift(i16 %arg0, i16 %arg1, i16 %arg2, i16 %arg3) {125; CHECK-LABEL: build_vector_i16_to_shift:126; CHECK: ; %bb.0:127; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)128; CHECK-NEXT: s_mov_b32 s4, 0x5040100129; CHECK-NEXT: v_perm_b32 v0, v3, v2, s4130; CHECK-NEXT: s_setpc_b64 s[30:31]131 %ins.0 = insertelement <4 x i16> poison, i16 %arg0, i32 0132 %ins.1 = insertelement <4 x i16> %ins.0, i16 %arg1, i32 1133 %ins.2 = insertelement <4 x i16> %ins.1, i16 %arg2, i32 2134 %ins.3 = insertelement <4 x i16> %ins.2, i16 %arg3, i32 3135 136 %cast = bitcast <4 x i16> %ins.3 to i64137 %srl = lshr i64 %cast, 32138 %trunc = trunc i64 %srl to i32139 ret i32 %trunc140}141