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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 -stop-after twoaddressinstruction < %s | FileCheck %s3 4; Check that %16 gets constrained to register class sgpr_96_with_sub0_sub1.5define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align4(ptr addrspace(4) inreg %ptr) {6 ; CHECK-LABEL: name: s_load_constant_v3i32_align47 ; CHECK: bb.0 (%ir-block.0):8 ; CHECK-NEXT: liveins: $sgpr0, $sgpr19 ; CHECK-NEXT: {{ $}}10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY killed $sgpr011 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY killed $sgpr112 ; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:sreg_64 = COPY killed [[COPY]]13 ; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:sreg_64 = COPY killed [[COPY1]]14 ; CHECK-NEXT: early-clobber %11:sreg_64_xexec = S_LOAD_DWORDX2_IMM_ec [[COPY2]], 0, 0 :: (invariant load (<2 x s32>) from %ir.ptr, align 4, addrspace 4)15 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed [[COPY2]], 8, 0 :: (invariant load (s32) from %ir.ptr + 8, addrspace 4)16 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY %11.sub017 ; CHECK-NEXT: $sgpr0 = COPY killed [[COPY3]]18 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY killed %11.sub119 ; CHECK-NEXT: $sgpr1 = COPY killed [[COPY4]]20 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY killed [[S_LOAD_DWORD_IMM]]21 ; CHECK-NEXT: $sgpr2 = COPY killed [[COPY5]]22 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit killed $sgpr0, implicit killed $sgpr1, implicit killed $sgpr223 %load = load <3 x i32>, ptr addrspace(4) %ptr, align 424 ret <3 x i32> %load25}26