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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,register-coalescer -verify-machineinstrs -o - %s | FileCheck %s3 4# Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE.5---6name: f7tracksRegLiveness: true8body: |9 bb.0:10 liveins: $vgpr0, $vgpr111 12 ; CHECK-LABEL: name: f13 ; CHECK: liveins: $vgpr0, $vgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr016 ; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr117 ; CHECK-NEXT: $vgpr2_vgpr3 = COPY [[COPY]]18 ; CHECK-NEXT: S_NOP 0, implicit $vgpr2_vgpr319 %0:vgpr_32 = COPY $vgpr020 %1:vgpr_32 = COPY $vgpr121 %35:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub122 $vgpr2_vgpr3 = COPY %3523 S_NOP 0, implicit $vgpr2_vgpr324...25