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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 %s3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s5 6define amdgpu_kernel void @test_udivrem(ptr addrspace(1) %out0, [8 x i32], ptr addrspace(1) %out1, [8 x i32], i32 %x, [8 x i32], i32 %y) {7; R600-LABEL: test_udivrem:8; R600: ; %bb.0:9; R600-NEXT: ALU 21, @4, KC0[CB0:0-32], KC1[]10; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 011; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 112; R600-NEXT: CF_END13; R600-NEXT: ALU clause starting at 4:14; R600-NEXT: SUB_INT T0.W, 0.0, KC0[9].X,15; R600-NEXT: RECIP_UINT * T0.X, KC0[9].X,16; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,17; R600-NEXT: MULHI * T0.Y, T0.X, PS,18; R600-NEXT: ADD_INT * T0.W, T0.X, PS,19; R600-NEXT: MULHI * T0.X, KC0[6].W, PV.W,20; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[9].X,21; R600-NEXT: SUB_INT * T0.W, KC0[6].W, PS,22; R600-NEXT: SUB_INT T1.W, PV.W, KC0[9].X,23; R600-NEXT: SETGE_UINT * T2.W, PV.W, KC0[9].X,24; R600-NEXT: CNDE_INT * T0.W, PS, T0.W, PV.W,25; R600-NEXT: ADD_INT T0.Z, T0.X, 1,26; R600-NEXT: SUB_INT T1.W, PV.W, KC0[9].X,27; R600-NEXT: SETGE_UINT * T3.W, PV.W, KC0[9].X,28; R600-NEXT: CNDE_INT T1.X, PS, T0.W, PV.W,29; R600-NEXT: CNDE_INT T0.W, T2.W, T0.X, PV.Z,30; R600-NEXT: LSHR * T0.X, KC0[4].Z, literal.x,31; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)32; R600-NEXT: ADD_INT * T1.W, PV.W, 1,33; R600-NEXT: CNDE_INT T2.X, T3.W, T0.W, PV.W,34; R600-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,35; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)36;37; GFX6-LABEL: test_udivrem:38; GFX6: ; %bb.0:39; GFX6-NEXT: s_load_dword s8, s[4:5], 0x2640; GFX6-NEXT: s_mov_b32 s3, 0xf00041; GFX6-NEXT: s_mov_b32 s2, -142; GFX6-NEXT: s_mov_b32 s6, s243; GFX6-NEXT: s_mov_b32 s7, s344; GFX6-NEXT: s_waitcnt lgkmcnt(0)45; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s846; GFX6-NEXT: s_sub_i32 s0, 0, s847; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v048; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v049; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v050; GFX6-NEXT: v_mul_lo_u32 v1, s0, v051; GFX6-NEXT: s_load_dword s9, s[4:5], 0x1d52; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x953; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x1354; GFX6-NEXT: v_mul_hi_u32 v1, v0, v155; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v156; GFX6-NEXT: s_waitcnt lgkmcnt(0)57; GFX6-NEXT: v_mul_hi_u32 v0, s9, v058; GFX6-NEXT: v_readfirstlane_b32 s10, v059; GFX6-NEXT: s_mul_i32 s10, s10, s860; GFX6-NEXT: s_sub_i32 s9, s9, s1061; GFX6-NEXT: s_sub_i32 s10, s9, s862; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v063; GFX6-NEXT: s_cmp_ge_u32 s9, s864; GFX6-NEXT: s_cselect_b64 vcc, -1, 065; GFX6-NEXT: s_cselect_b32 s9, s10, s966; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc67; GFX6-NEXT: s_sub_i32 s10, s9, s868; GFX6-NEXT: v_add_i32_e32 v1, vcc, 1, v069; GFX6-NEXT: s_cmp_ge_u32 s9, s870; GFX6-NEXT: s_cselect_b64 vcc, -1, 071; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc72; GFX6-NEXT: s_cselect_b32 s8, s10, s973; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 074; GFX6-NEXT: s_waitcnt expcnt(0)75; GFX6-NEXT: v_mov_b32_e32 v0, s876; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 077; GFX6-NEXT: s_endpgm78;79; GFX8-LABEL: test_udivrem:80; GFX8: ; %bb.0:81; GFX8-NEXT: s_load_dword s6, s[4:5], 0x9882; GFX8-NEXT: s_waitcnt lgkmcnt(0)83; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s684; GFX8-NEXT: s_sub_i32 s0, 0, s685; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v086; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v087; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v088; GFX8-NEXT: v_mul_lo_u32 v1, s0, v089; GFX8-NEXT: s_load_dword s7, s[4:5], 0x7490; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2491; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x4c92; GFX8-NEXT: v_mul_hi_u32 v1, v0, v193; GFX8-NEXT: s_waitcnt lgkmcnt(0)94; GFX8-NEXT: v_mov_b32_e32 v2, s295; GFX8-NEXT: v_mov_b32_e32 v3, s396; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v197; GFX8-NEXT: v_mul_hi_u32 v4, s7, v098; GFX8-NEXT: v_mov_b32_e32 v0, s099; GFX8-NEXT: v_mov_b32_e32 v1, s1100; GFX8-NEXT: v_readfirstlane_b32 s0, v4101; GFX8-NEXT: s_mul_i32 s0, s0, s6102; GFX8-NEXT: s_sub_i32 s0, s7, s0103; GFX8-NEXT: s_sub_i32 s1, s0, s6104; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v4105; GFX8-NEXT: s_cmp_ge_u32 s0, s6106; GFX8-NEXT: s_cselect_b64 vcc, -1, 0107; GFX8-NEXT: s_cselect_b32 s0, s1, s0108; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc109; GFX8-NEXT: s_sub_i32 s1, s0, s6110; GFX8-NEXT: v_add_u32_e32 v5, vcc, 1, v4111; GFX8-NEXT: s_cmp_ge_u32 s0, s6112; GFX8-NEXT: s_cselect_b64 vcc, -1, 0113; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc114; GFX8-NEXT: s_cselect_b32 s0, s1, s0115; GFX8-NEXT: flat_store_dword v[0:1], v4116; GFX8-NEXT: v_mov_b32_e32 v0, s0117; GFX8-NEXT: flat_store_dword v[2:3], v0118; GFX8-NEXT: s_endpgm119 %result0 = udiv i32 %x, %y120 store i32 %result0, ptr addrspace(1) %out0121 %result1 = urem i32 %x, %y122 store i32 %result1, ptr addrspace(1) %out1123 ret void124}125 126define amdgpu_kernel void @test_udivrem_v2(ptr addrspace(1) %out, <2 x i32> %x, <2 x i32> %y) {127; R600-LABEL: test_udivrem_v2:128; R600: ; %bb.0:129; R600-NEXT: ALU 29, @4, KC0[CB0:0-32], KC1[]130; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1131; R600-NEXT: CF_END132; R600-NEXT: PAD133; R600-NEXT: ALU clause starting at 4:134; R600-NEXT: SUB_INT T0.W, 0.0, KC0[3].Z,135; R600-NEXT: RECIP_UINT * T0.X, KC0[3].Z,136; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,137; R600-NEXT: SUB_INT T0.W, 0.0, KC0[3].Y,138; R600-NEXT: RECIP_UINT * T0.Z, KC0[3].Y,139; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,140; R600-NEXT: MULHI * T0.W, T0.Z, PS,141; R600-NEXT: ADD_INT T0.W, T0.Z, PS,142; R600-NEXT: MULHI * T0.Y, T0.X, T0.Y,143; R600-NEXT: ADD_INT T1.W, T0.X, PS,144; R600-NEXT: MULHI * T0.X, KC0[2].W, PV.W,145; R600-NEXT: MULHI * T0.Y, KC0[3].X, PV.W,146; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[3].Z,147; R600-NEXT: SUB_INT T0.W, KC0[3].X, PS,148; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[3].Y,149; R600-NEXT: SUB_INT T0.Z, KC0[2].W, PS,150; R600-NEXT: SETGE_UINT T1.W, PV.W, KC0[3].Z,151; R600-NEXT: SUB_INT * T2.W, PV.W, KC0[3].Z,152; R600-NEXT: CNDE_INT T1.Z, PV.W, T0.W, PS,153; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Y,154; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Y,155; R600-NEXT: CNDE_INT T0.Z, PV.W, T0.Z, PS,156; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Z,157; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Z,158; R600-NEXT: CNDE_INT T0.Y, PV.W, T1.Z, PS,159; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Y,160; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Y,161; R600-NEXT: CNDE_INT T0.X, PV.W, T0.Z, PS,162; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,163; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)164;165; GFX6-LABEL: test_udivrem_v2:166; GFX6: ; %bb.0:167; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb168; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9169; GFX6-NEXT: s_mov_b32 s7, 0xf000170; GFX6-NEXT: s_waitcnt lgkmcnt(0)171; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2172; GFX6-NEXT: s_sub_i32 s6, 0, s2173; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s3174; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0175; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2176; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0177; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0178; GFX6-NEXT: v_mul_lo_u32 v1, s6, v0179; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1180; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1181; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0182; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2183; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1184; GFX6-NEXT: v_readfirstlane_b32 s6, v0185; GFX6-NEXT: s_mul_i32 s6, s6, s2186; GFX6-NEXT: s_sub_i32 s0, s0, s6187; GFX6-NEXT: s_sub_i32 s6, s0, s2188; GFX6-NEXT: s_cmp_ge_u32 s0, s2189; GFX6-NEXT: s_cselect_b32 s0, s6, s0190; GFX6-NEXT: s_sub_i32 s6, s0, s2191; GFX6-NEXT: s_cmp_ge_u32 s0, s2192; GFX6-NEXT: s_cselect_b32 s0, s6, s0193; GFX6-NEXT: s_sub_i32 s2, 0, s3194; GFX6-NEXT: v_mul_lo_u32 v0, s2, v1195; GFX6-NEXT: s_mov_b32 s6, -1196; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0197; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0198; GFX6-NEXT: v_mul_hi_u32 v0, s1, v0199; GFX6-NEXT: v_readfirstlane_b32 s2, v0200; GFX6-NEXT: s_mul_i32 s2, s2, s3201; GFX6-NEXT: s_sub_i32 s1, s1, s2202; GFX6-NEXT: s_sub_i32 s2, s1, s3203; GFX6-NEXT: s_cmp_ge_u32 s1, s3204; GFX6-NEXT: s_cselect_b32 s1, s2, s1205; GFX6-NEXT: s_sub_i32 s2, s1, s3206; GFX6-NEXT: s_cmp_ge_u32 s1, s3207; GFX6-NEXT: s_cselect_b32 s1, s2, s1208; GFX6-NEXT: v_mov_b32_e32 v0, s0209; GFX6-NEXT: v_mov_b32_e32 v1, s1210; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0211; GFX6-NEXT: s_endpgm212;213; GFX8-LABEL: test_udivrem_v2:214; GFX8: ; %bb.0:215; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c216; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24217; GFX8-NEXT: s_waitcnt lgkmcnt(0)218; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2219; GFX8-NEXT: s_sub_i32 s6, 0, s2220; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s3221; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0222; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2223; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0224; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0225; GFX8-NEXT: v_mul_lo_u32 v1, s6, v0226; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1227; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1228; GFX8-NEXT: v_mul_hi_u32 v0, s0, v0229; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2230; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1231; GFX8-NEXT: v_mov_b32_e32 v2, s4232; GFX8-NEXT: v_readfirstlane_b32 s6, v0233; GFX8-NEXT: s_mul_i32 s6, s6, s2234; GFX8-NEXT: s_sub_i32 s0, s0, s6235; GFX8-NEXT: s_sub_i32 s6, s0, s2236; GFX8-NEXT: s_cmp_ge_u32 s0, s2237; GFX8-NEXT: s_cselect_b32 s0, s6, s0238; GFX8-NEXT: s_sub_i32 s6, s0, s2239; GFX8-NEXT: s_cmp_ge_u32 s0, s2240; GFX8-NEXT: s_cselect_b32 s0, s6, s0241; GFX8-NEXT: s_sub_i32 s2, 0, s3242; GFX8-NEXT: v_mul_lo_u32 v0, s2, v1243; GFX8-NEXT: v_mov_b32_e32 v3, s5244; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0245; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0246; GFX8-NEXT: v_mul_hi_u32 v1, s1, v0247; GFX8-NEXT: v_mov_b32_e32 v0, s0248; GFX8-NEXT: v_readfirstlane_b32 s0, v1249; GFX8-NEXT: s_mul_i32 s0, s0, s3250; GFX8-NEXT: s_sub_i32 s0, s1, s0251; GFX8-NEXT: s_sub_i32 s1, s0, s3252; GFX8-NEXT: s_cmp_ge_u32 s0, s3253; GFX8-NEXT: s_cselect_b32 s0, s1, s0254; GFX8-NEXT: s_sub_i32 s1, s0, s3255; GFX8-NEXT: s_cmp_ge_u32 s0, s3256; GFX8-NEXT: s_cselect_b32 s0, s1, s0257; GFX8-NEXT: v_mov_b32_e32 v1, s0258; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]259; GFX8-NEXT: s_endpgm260 %result0 = udiv <2 x i32> %x, %y261 store <2 x i32> %result0, ptr addrspace(1) %out262 %result1 = urem <2 x i32> %x, %y263 store <2 x i32> %result1, ptr addrspace(1) %out264 ret void265}266 267define amdgpu_kernel void @test_udivrem_v4(ptr addrspace(1) %out, <4 x i32> %x, <4 x i32> %y) {268; R600-LABEL: test_udivrem_v4:269; R600: ; %bb.0:270; R600-NEXT: ALU 57, @4, KC0[CB0:0-32], KC1[]271; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1272; R600-NEXT: CF_END273; R600-NEXT: PAD274; R600-NEXT: ALU clause starting at 4:275; R600-NEXT: SUB_INT T0.W, 0.0, KC0[5].X,276; R600-NEXT: RECIP_UINT * T0.X, KC0[5].X,277; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,278; R600-NEXT: SUB_INT T0.W, 0.0, KC0[4].Z,279; R600-NEXT: RECIP_UINT * T0.Z, KC0[4].Z,280; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,281; R600-NEXT: MULHI * T0.W, T0.Z, PS,282; R600-NEXT: ADD_INT T0.W, T0.Z, PS,283; R600-NEXT: MULHI * T0.Y, T0.X, T0.Y,284; R600-NEXT: ADD_INT T1.W, T0.X, PS,285; R600-NEXT: MULHI * T0.X, KC0[3].Z, PV.W,286; R600-NEXT: MULHI * T0.Y, KC0[4].X, PV.W,287; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[5].X,288; R600-NEXT: RECIP_UINT * T0.Z, KC0[4].Y,289; R600-NEXT: SUB_INT T0.W, 0.0, KC0[4].W,290; R600-NEXT: RECIP_UINT * T1.X, KC0[4].W,291; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,292; R600-NEXT: SUB_INT T1.W, 0.0, KC0[4].Y,293; R600-NEXT: MULHI * T0.W, T1.X, PS,294; R600-NEXT: ADD_INT T0.W, T1.X, PS,295; R600-NEXT: MULLO_INT * T1.X, PV.W, T0.Z,296; R600-NEXT: MULHI * T0.W, KC0[3].W, PV.W,297; R600-NEXT: MULLO_INT * T0.W, PS, KC0[4].W,298; R600-NEXT: SUB_INT T0.W, KC0[3].W, PS,299; R600-NEXT: MULHI * T1.X, T0.Z, T1.X,300; R600-NEXT: SETGE_UINT T1.Y, PV.W, KC0[4].W,301; R600-NEXT: ADD_INT T0.Z, T0.Z, PS,302; R600-NEXT: SUB_INT T1.W, KC0[4].X, T0.Y,303; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[4].Z,304; R600-NEXT: SUB_INT T0.Y, KC0[3].Z, PS,305; R600-NEXT: SETGE_UINT T1.Z, PV.W, KC0[5].X,306; R600-NEXT: SUB_INT * T2.W, PV.W, KC0[5].X,307; R600-NEXT: MULHI * T0.X, KC0[3].Y, T0.Z,308; R600-NEXT: SUB_INT T1.X, T0.W, KC0[4].W,309; R600-NEXT: CNDE_INT T2.Y, T1.Z, T1.W, T2.W,310; R600-NEXT: SETGE_UINT T0.Z, T0.Y, KC0[4].Z,311; R600-NEXT: SUB_INT T1.W, T0.Y, KC0[4].Z,312; R600-NEXT: MULLO_INT * T0.X, PS, KC0[4].Y,313; R600-NEXT: CNDE_INT T2.X, PV.Z, T0.Y, PV.W,314; R600-NEXT: SETGE_UINT T0.Y, PV.Y, KC0[5].X,315; R600-NEXT: SUB_INT T0.Z, PV.Y, KC0[5].X,316; R600-NEXT: SUB_INT T1.W, KC0[3].Y, PS,317; R600-NEXT: CNDE_INT * T0.W, T1.Y, T0.W, PV.X,318; R600-NEXT: SETGE_UINT T0.X, PS, KC0[4].W,319; R600-NEXT: SUB_INT T1.Y, PS, KC0[4].W,320; R600-NEXT: SETGE_UINT T1.Z, PV.W, KC0[4].Y,321; R600-NEXT: SUB_INT T2.W, PV.W, KC0[4].Y,322; R600-NEXT: CNDE_INT * T3.W, PV.Y, T2.Y, PV.Z,323; R600-NEXT: CNDE_INT T0.Y, PV.Z, T1.W, PV.W,324; R600-NEXT: CNDE_INT T3.Z, PV.X, T0.W, PV.Y, BS:VEC_021/SCL_122325; R600-NEXT: SETGE_UINT T0.W, T2.X, KC0[4].Z,326; R600-NEXT: SUB_INT * T1.W, T2.X, KC0[4].Z,327; R600-NEXT: CNDE_INT T3.Y, PV.W, T2.X, PS,328; R600-NEXT: SETGE_UINT T0.W, PV.Y, KC0[4].Y,329; R600-NEXT: SUB_INT * T1.W, PV.Y, KC0[4].Y,330; R600-NEXT: CNDE_INT T3.X, PV.W, T0.Y, PS,331; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,332; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)333;334; GFX6-LABEL: test_udivrem_v4:335; GFX6: ; %bb.0:336; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd337; GFX6-NEXT: s_mov_b32 s3, 0xf000338; GFX6-NEXT: s_mov_b32 s2, -1339; GFX6-NEXT: s_waitcnt lgkmcnt(0)340; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s12341; GFX6-NEXT: s_sub_i32 s0, 0, s12342; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s13343; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0344; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2345; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0346; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0347; GFX6-NEXT: v_mul_lo_u32 v1, s0, v0348; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1349; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1350; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0351; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2352; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1353; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s14354; GFX6-NEXT: v_readfirstlane_b32 s0, v0355; GFX6-NEXT: s_mul_i32 s0, s0, s12356; GFX6-NEXT: s_sub_i32 s0, s8, s0357; GFX6-NEXT: s_sub_i32 s1, s0, s12358; GFX6-NEXT: s_cmp_ge_u32 s0, s12359; GFX6-NEXT: s_cselect_b32 s0, s1, s0360; GFX6-NEXT: s_sub_i32 s1, s0, s12361; GFX6-NEXT: s_cmp_ge_u32 s0, s12362; GFX6-NEXT: s_cselect_b32 s6, s1, s0363; GFX6-NEXT: s_sub_i32 s0, 0, s13364; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1365; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2366; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0367; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0368; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0369; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2370; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1371; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s15372; GFX6-NEXT: v_readfirstlane_b32 s0, v0373; GFX6-NEXT: s_mul_i32 s0, s0, s13374; GFX6-NEXT: s_sub_i32 s0, s9, s0375; GFX6-NEXT: s_sub_i32 s1, s0, s13376; GFX6-NEXT: s_cmp_ge_u32 s0, s13377; GFX6-NEXT: s_cselect_b32 s0, s1, s0378; GFX6-NEXT: s_sub_i32 s1, s0, s13379; GFX6-NEXT: s_cmp_ge_u32 s0, s13380; GFX6-NEXT: s_cselect_b32 s7, s1, s0381; GFX6-NEXT: s_sub_i32 s0, 0, s14382; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1383; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2384; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0385; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0386; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0387; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2388; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1389; GFX6-NEXT: v_readfirstlane_b32 s0, v0390; GFX6-NEXT: s_mul_i32 s0, s0, s14391; GFX6-NEXT: s_sub_i32 s0, s10, s0392; GFX6-NEXT: s_sub_i32 s1, s0, s14393; GFX6-NEXT: s_cmp_ge_u32 s0, s14394; GFX6-NEXT: s_cselect_b32 s0, s1, s0395; GFX6-NEXT: s_sub_i32 s1, s0, s14396; GFX6-NEXT: s_cmp_ge_u32 s0, s14397; GFX6-NEXT: s_cselect_b32 s8, s1, s0398; GFX6-NEXT: s_sub_i32 s0, 0, s15399; GFX6-NEXT: v_mul_lo_u32 v0, s0, v1400; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9401; GFX6-NEXT: v_mul_hi_u32 v0, v1, v0402; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0403; GFX6-NEXT: v_mul_hi_u32 v2, s11, v0404; GFX6-NEXT: v_mov_b32_e32 v0, s6405; GFX6-NEXT: v_mov_b32_e32 v1, s7406; GFX6-NEXT: v_readfirstlane_b32 s4, v2407; GFX6-NEXT: s_mul_i32 s4, s4, s15408; GFX6-NEXT: s_sub_i32 s4, s11, s4409; GFX6-NEXT: s_sub_i32 s5, s4, s15410; GFX6-NEXT: s_cmp_ge_u32 s4, s15411; GFX6-NEXT: s_cselect_b32 s4, s5, s4412; GFX6-NEXT: s_sub_i32 s5, s4, s15413; GFX6-NEXT: s_cmp_ge_u32 s4, s15414; GFX6-NEXT: s_cselect_b32 s4, s5, s4415; GFX6-NEXT: v_mov_b32_e32 v2, s8416; GFX6-NEXT: v_mov_b32_e32 v3, s4417; GFX6-NEXT: s_waitcnt lgkmcnt(0)418; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0419; GFX6-NEXT: s_endpgm420;421; GFX8-LABEL: test_udivrem_v4:422; GFX8: ; %bb.0:423; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34424; GFX8-NEXT: s_waitcnt lgkmcnt(0)425; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s12426; GFX8-NEXT: s_sub_i32 s0, 0, s12427; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s13428; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0429; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2430; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0431; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0432; GFX8-NEXT: v_mul_lo_u32 v1, s0, v0433; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1434; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1435; GFX8-NEXT: v_mul_hi_u32 v0, s8, v0436; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2437; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1438; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s14439; GFX8-NEXT: v_readfirstlane_b32 s0, v0440; GFX8-NEXT: s_mul_i32 s0, s0, s12441; GFX8-NEXT: s_sub_i32 s0, s8, s0442; GFX8-NEXT: s_sub_i32 s1, s0, s12443; GFX8-NEXT: s_cmp_ge_u32 s0, s12444; GFX8-NEXT: s_cselect_b32 s0, s1, s0445; GFX8-NEXT: s_sub_i32 s1, s0, s12446; GFX8-NEXT: s_cmp_ge_u32 s0, s12447; GFX8-NEXT: s_cselect_b32 s2, s1, s0448; GFX8-NEXT: s_sub_i32 s0, 0, s13449; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1450; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2451; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0452; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0453; GFX8-NEXT: v_mul_hi_u32 v0, s9, v0454; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2455; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1456; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s15457; GFX8-NEXT: v_readfirstlane_b32 s0, v0458; GFX8-NEXT: s_mul_i32 s0, s0, s13459; GFX8-NEXT: s_sub_i32 s0, s9, s0460; GFX8-NEXT: s_sub_i32 s1, s0, s13461; GFX8-NEXT: s_cmp_ge_u32 s0, s13462; GFX8-NEXT: s_cselect_b32 s0, s1, s0463; GFX8-NEXT: s_sub_i32 s1, s0, s13464; GFX8-NEXT: s_cmp_ge_u32 s0, s13465; GFX8-NEXT: s_cselect_b32 s3, s1, s0466; GFX8-NEXT: s_sub_i32 s0, 0, s14467; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1468; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2469; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0470; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0471; GFX8-NEXT: v_mul_hi_u32 v0, s10, v0472; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2473; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1474; GFX8-NEXT: v_readfirstlane_b32 s0, v0475; GFX8-NEXT: s_mul_i32 s0, s0, s14476; GFX8-NEXT: s_sub_i32 s0, s10, s0477; GFX8-NEXT: s_sub_i32 s1, s0, s14478; GFX8-NEXT: s_cmp_ge_u32 s0, s14479; GFX8-NEXT: s_cselect_b32 s0, s1, s0480; GFX8-NEXT: s_sub_i32 s1, s0, s14481; GFX8-NEXT: s_cmp_ge_u32 s0, s14482; GFX8-NEXT: s_cselect_b32 s6, s1, s0483; GFX8-NEXT: s_sub_i32 s0, 0, s15484; GFX8-NEXT: v_mul_lo_u32 v0, s0, v1485; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24486; GFX8-NEXT: v_mov_b32_e32 v2, s6487; GFX8-NEXT: v_mul_hi_u32 v0, v1, v0488; GFX8-NEXT: s_waitcnt lgkmcnt(0)489; GFX8-NEXT: v_mov_b32_e32 v5, s1490; GFX8-NEXT: v_mov_b32_e32 v4, s0491; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0492; GFX8-NEXT: v_mul_hi_u32 v3, s11, v0493; GFX8-NEXT: v_mov_b32_e32 v0, s2494; GFX8-NEXT: v_mov_b32_e32 v1, s3495; GFX8-NEXT: v_readfirstlane_b32 s2, v3496; GFX8-NEXT: s_mul_i32 s2, s2, s15497; GFX8-NEXT: s_sub_i32 s2, s11, s2498; GFX8-NEXT: s_sub_i32 s3, s2, s15499; GFX8-NEXT: s_cmp_ge_u32 s2, s15500; GFX8-NEXT: s_cselect_b32 s2, s3, s2501; GFX8-NEXT: s_sub_i32 s3, s2, s15502; GFX8-NEXT: s_cmp_ge_u32 s2, s15503; GFX8-NEXT: s_cselect_b32 s2, s3, s2504; GFX8-NEXT: v_mov_b32_e32 v3, s2505; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]506; GFX8-NEXT: s_endpgm507 %result0 = udiv <4 x i32> %x, %y508 store <4 x i32> %result0, ptr addrspace(1) %out509 %result1 = urem <4 x i32> %x, %y510 store <4 x i32> %result1, ptr addrspace(1) %out511 ret void512}513