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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI %s4; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s5 6define amdgpu_kernel void @udiv24_i8(ptr addrspace(1) %out, ptr addrspace(1) %in) {7; SI-LABEL: udiv24_i8:8; SI: ; %bb.0:9; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x910; SI-NEXT: s_mov_b32 s7, 0xf00011; SI-NEXT: s_mov_b32 s6, -112; SI-NEXT: s_mov_b32 s10, s613; SI-NEXT: s_mov_b32 s11, s714; SI-NEXT: s_waitcnt lgkmcnt(0)15; SI-NEXT: s_mov_b32 s8, s216; SI-NEXT: s_mov_b32 s9, s317; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 018; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:119; SI-NEXT: s_mov_b32 s4, s020; SI-NEXT: s_mov_b32 s5, s121; SI-NEXT: s_waitcnt vmcnt(1)22; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v023; SI-NEXT: s_waitcnt vmcnt(0)24; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v125; SI-NEXT: v_rcp_iflag_f32_e32 v2, v126; SI-NEXT: v_mul_f32_e32 v2, v0, v227; SI-NEXT: v_trunc_f32_e32 v2, v228; SI-NEXT: v_fma_f32 v0, -v2, v1, v029; SI-NEXT: v_cvt_u32_f32_e32 v2, v230; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v131; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc32; SI-NEXT: buffer_store_byte v0, off, s[4:7], 033; SI-NEXT: s_endpgm34;35; VI-LABEL: udiv24_i8:36; VI: ; %bb.0:37; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2438; VI-NEXT: s_mov_b32 s7, 0xf00039; VI-NEXT: s_mov_b32 s6, -140; VI-NEXT: s_mov_b32 s10, s641; VI-NEXT: s_mov_b32 s11, s742; VI-NEXT: s_waitcnt lgkmcnt(0)43; VI-NEXT: s_mov_b32 s8, s244; VI-NEXT: s_mov_b32 s9, s345; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:146; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 047; VI-NEXT: s_mov_b32 s4, s048; VI-NEXT: s_mov_b32 s5, s149; VI-NEXT: s_waitcnt vmcnt(1)50; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v051; VI-NEXT: v_rcp_iflag_f32_e32 v2, v052; VI-NEXT: s_waitcnt vmcnt(0)53; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v154; VI-NEXT: v_mul_f32_e32 v2, v1, v255; VI-NEXT: v_trunc_f32_e32 v2, v256; VI-NEXT: v_cvt_u32_f32_e32 v3, v257; VI-NEXT: v_mad_f32 v1, -v2, v0, v158; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v059; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc60; VI-NEXT: buffer_store_byte v0, off, s[4:7], 061; VI-NEXT: s_endpgm62;63; EG-LABEL: udiv24_i8:64; EG: ; %bb.0:65; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]66; EG-NEXT: TEX 1 @667; EG-NEXT: ALU 23, @11, KC0[CB0:0-32], KC1[]68; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X69; EG-NEXT: CF_END70; EG-NEXT: PAD71; EG-NEXT: Fetch clause starting at 6:72; EG-NEXT: VTX_READ_8 T1.X, T0.X, 1, #173; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #174; EG-NEXT: ALU clause starting at 10:75; EG-NEXT: MOV * T0.X, KC0[2].Z,76; EG-NEXT: ALU clause starting at 11:77; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,78; EG-NEXT: RECIP_IEEE * T0.Z, PS,79; EG-NEXT: UINT_TO_FLT * T0.X, T0.X,80; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z,81; EG-NEXT: TRUNC * T0.W, PV.W,82; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X,83; EG-NEXT: TRUNC * T0.W, PV.W,84; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,85; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,86; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,87; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)88; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,89; EG-NEXT: ADD_INT * T1.W, PS, PV.W,90; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)91; EG-NEXT: AND_INT T1.W, PS, literal.x,92; EG-NEXT: LSHL * T0.W, PV.W, literal.y,93; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)94; EG-NEXT: LSHL T0.X, PV.W, PS,95; EG-NEXT: LSHL * T0.W, literal.x, PS,96; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)97; EG-NEXT: MOV T0.Y, 0.0,98; EG-NEXT: MOV * T0.Z, 0.0,99; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,100; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)101 %den_ptr = getelementptr i8, ptr addrspace(1) %in, i8 1102 %num = load i8, ptr addrspace(1) %in103 %den = load i8, ptr addrspace(1) %den_ptr104 %result = udiv i8 %num, %den105 store i8 %result, ptr addrspace(1) %out106 ret void107}108 109define amdgpu_kernel void @udiv24_i8_denorm_flush_in_out(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {110; SI-LABEL: udiv24_i8_denorm_flush_in_out:111; SI: ; %bb.0:112; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9113; SI-NEXT: s_mov_b32 s7, 0xf000114; SI-NEXT: s_mov_b32 s6, -1115; SI-NEXT: s_mov_b32 s10, s6116; SI-NEXT: s_mov_b32 s11, s7117; SI-NEXT: s_waitcnt lgkmcnt(0)118; SI-NEXT: s_mov_b32 s8, s2119; SI-NEXT: s_mov_b32 s9, s3120; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0121; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1122; SI-NEXT: s_mov_b32 s4, s0123; SI-NEXT: s_mov_b32 s5, s1124; SI-NEXT: s_waitcnt vmcnt(1)125; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0126; SI-NEXT: s_waitcnt vmcnt(0)127; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1128; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1129; SI-NEXT: v_mul_f32_e32 v2, v0, v2130; SI-NEXT: v_trunc_f32_e32 v2, v2131; SI-NEXT: v_fma_f32 v0, -v2, v1, v0132; SI-NEXT: v_cvt_u32_f32_e32 v2, v2133; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1134; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc135; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0136; SI-NEXT: s_endpgm137;138; VI-LABEL: udiv24_i8_denorm_flush_in_out:139; VI: ; %bb.0:140; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24141; VI-NEXT: s_mov_b32 s7, 0xf000142; VI-NEXT: s_mov_b32 s6, -1143; VI-NEXT: s_mov_b32 s10, s6144; VI-NEXT: s_mov_b32 s11, s7145; VI-NEXT: s_waitcnt lgkmcnt(0)146; VI-NEXT: s_mov_b32 s8, s2147; VI-NEXT: s_mov_b32 s9, s3148; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1149; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0150; VI-NEXT: s_mov_b32 s4, s0151; VI-NEXT: s_mov_b32 s5, s1152; VI-NEXT: s_waitcnt vmcnt(1)153; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0154; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0155; VI-NEXT: s_waitcnt vmcnt(0)156; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1157; VI-NEXT: v_mul_f32_e32 v2, v1, v2158; VI-NEXT: v_trunc_f32_e32 v2, v2159; VI-NEXT: v_cvt_u32_f32_e32 v3, v2160; VI-NEXT: v_mad_f32 v1, -v2, v0, v1161; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0162; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc163; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0164; VI-NEXT: s_endpgm165;166; EG-LABEL: udiv24_i8_denorm_flush_in_out:167; EG: ; %bb.0:168; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]169; EG-NEXT: TEX 1 @6170; EG-NEXT: ALU 23, @11, KC0[CB0:0-32], KC1[]171; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X172; EG-NEXT: CF_END173; EG-NEXT: PAD174; EG-NEXT: Fetch clause starting at 6:175; EG-NEXT: VTX_READ_8 T1.X, T0.X, 1, #1176; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1177; EG-NEXT: ALU clause starting at 10:178; EG-NEXT: MOV * T0.X, KC0[2].Z,179; EG-NEXT: ALU clause starting at 11:180; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,181; EG-NEXT: RECIP_IEEE * T0.Z, PS,182; EG-NEXT: UINT_TO_FLT * T0.X, T0.X,183; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z,184; EG-NEXT: TRUNC * T0.W, PV.W,185; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X,186; EG-NEXT: TRUNC * T0.W, PV.W,187; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,188; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,189; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,190; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)191; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,192; EG-NEXT: ADD_INT * T1.W, PS, PV.W,193; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)194; EG-NEXT: AND_INT T1.W, PS, literal.x,195; EG-NEXT: LSHL * T0.W, PV.W, literal.y,196; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)197; EG-NEXT: LSHL T0.X, PV.W, PS,198; EG-NEXT: LSHL * T0.W, literal.x, PS,199; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)200; EG-NEXT: MOV T0.Y, 0.0,201; EG-NEXT: MOV * T0.Z, 0.0,202; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,203; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)204 %den_ptr = getelementptr i8, ptr addrspace(1) %in, i8 1205 %num = load i8, ptr addrspace(1) %in206 %den = load i8, ptr addrspace(1) %den_ptr207 %result = udiv i8 %num, %den208 store i8 %result, ptr addrspace(1) %out209 ret void210}211 212define amdgpu_kernel void @udiv24_i8_denorm_flush_in(ptr addrspace(1) %out, ptr addrspace(1) %in) #1 {213; SI-LABEL: udiv24_i8_denorm_flush_in:214; SI: ; %bb.0:215; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9216; SI-NEXT: s_mov_b32 s7, 0xf000217; SI-NEXT: s_mov_b32 s6, -1218; SI-NEXT: s_mov_b32 s10, s6219; SI-NEXT: s_mov_b32 s11, s7220; SI-NEXT: s_waitcnt lgkmcnt(0)221; SI-NEXT: s_mov_b32 s8, s2222; SI-NEXT: s_mov_b32 s9, s3223; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0224; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1225; SI-NEXT: s_mov_b32 s4, s0226; SI-NEXT: s_mov_b32 s5, s1227; SI-NEXT: s_waitcnt vmcnt(1)228; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0229; SI-NEXT: s_waitcnt vmcnt(0)230; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1231; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1232; SI-NEXT: v_mul_f32_e32 v2, v0, v2233; SI-NEXT: v_trunc_f32_e32 v2, v2234; SI-NEXT: v_fma_f32 v0, -v2, v1, v0235; SI-NEXT: v_cvt_u32_f32_e32 v2, v2236; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1237; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc238; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0239; SI-NEXT: s_endpgm240;241; VI-LABEL: udiv24_i8_denorm_flush_in:242; VI: ; %bb.0:243; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24244; VI-NEXT: s_mov_b32 s7, 0xf000245; VI-NEXT: s_mov_b32 s6, -1246; VI-NEXT: s_mov_b32 s10, s6247; VI-NEXT: s_mov_b32 s11, s7248; VI-NEXT: s_waitcnt lgkmcnt(0)249; VI-NEXT: s_mov_b32 s8, s2250; VI-NEXT: s_mov_b32 s9, s3251; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1252; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0253; VI-NEXT: s_mov_b32 s4, s0254; VI-NEXT: s_mov_b32 s5, s1255; VI-NEXT: s_waitcnt vmcnt(1)256; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0257; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0258; VI-NEXT: s_waitcnt vmcnt(0)259; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1260; VI-NEXT: v_mul_f32_e32 v2, v1, v2261; VI-NEXT: v_trunc_f32_e32 v2, v2262; VI-NEXT: v_cvt_u32_f32_e32 v3, v2263; VI-NEXT: v_mad_f32 v1, -v2, v0, v1264; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0265; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc266; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0267; VI-NEXT: s_endpgm268;269; EG-LABEL: udiv24_i8_denorm_flush_in:270; EG: ; %bb.0:271; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]272; EG-NEXT: TEX 1 @6273; EG-NEXT: ALU 23, @11, KC0[CB0:0-32], KC1[]274; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X275; EG-NEXT: CF_END276; EG-NEXT: PAD277; EG-NEXT: Fetch clause starting at 6:278; EG-NEXT: VTX_READ_8 T1.X, T0.X, 1, #1279; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1280; EG-NEXT: ALU clause starting at 10:281; EG-NEXT: MOV * T0.X, KC0[2].Z,282; EG-NEXT: ALU clause starting at 11:283; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,284; EG-NEXT: RECIP_IEEE * T0.Z, PS,285; EG-NEXT: UINT_TO_FLT * T0.X, T0.X,286; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z,287; EG-NEXT: TRUNC * T0.W, PV.W,288; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X,289; EG-NEXT: TRUNC * T0.W, PV.W,290; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,291; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,292; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,293; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)294; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,295; EG-NEXT: ADD_INT * T1.W, PS, PV.W,296; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)297; EG-NEXT: AND_INT T1.W, PS, literal.x,298; EG-NEXT: LSHL * T0.W, PV.W, literal.y,299; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)300; EG-NEXT: LSHL T0.X, PV.W, PS,301; EG-NEXT: LSHL * T0.W, literal.x, PS,302; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)303; EG-NEXT: MOV T0.Y, 0.0,304; EG-NEXT: MOV * T0.Z, 0.0,305; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,306; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)307 %den_ptr = getelementptr i8, ptr addrspace(1) %in, i8 1308 %num = load i8, ptr addrspace(1) %in309 %den = load i8, ptr addrspace(1) %den_ptr310 %result = udiv i8 %num, %den311 store i8 %result, ptr addrspace(1) %out312 ret void313}314 315define amdgpu_kernel void @udiv24_i8_denorm_flush_out(ptr addrspace(1) %out, ptr addrspace(1) %in) #2 {316; SI-LABEL: udiv24_i8_denorm_flush_out:317; SI: ; %bb.0:318; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9319; SI-NEXT: s_mov_b32 s7, 0xf000320; SI-NEXT: s_mov_b32 s6, -1321; SI-NEXT: s_mov_b32 s10, s6322; SI-NEXT: s_mov_b32 s11, s7323; SI-NEXT: s_waitcnt lgkmcnt(0)324; SI-NEXT: s_mov_b32 s8, s2325; SI-NEXT: s_mov_b32 s9, s3326; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0327; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1328; SI-NEXT: s_mov_b32 s4, s0329; SI-NEXT: s_mov_b32 s5, s1330; SI-NEXT: s_waitcnt vmcnt(1)331; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0332; SI-NEXT: s_waitcnt vmcnt(0)333; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1334; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1335; SI-NEXT: v_mul_f32_e32 v2, v0, v2336; SI-NEXT: v_trunc_f32_e32 v2, v2337; SI-NEXT: v_fma_f32 v0, -v2, v1, v0338; SI-NEXT: v_cvt_u32_f32_e32 v2, v2339; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1340; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc341; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0342; SI-NEXT: s_endpgm343;344; VI-LABEL: udiv24_i8_denorm_flush_out:345; VI: ; %bb.0:346; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24347; VI-NEXT: s_mov_b32 s7, 0xf000348; VI-NEXT: s_mov_b32 s6, -1349; VI-NEXT: s_mov_b32 s10, s6350; VI-NEXT: s_mov_b32 s11, s7351; VI-NEXT: s_waitcnt lgkmcnt(0)352; VI-NEXT: s_mov_b32 s8, s2353; VI-NEXT: s_mov_b32 s9, s3354; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:1355; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0356; VI-NEXT: s_mov_b32 s4, s0357; VI-NEXT: s_mov_b32 s5, s1358; VI-NEXT: s_waitcnt vmcnt(1)359; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0360; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0361; VI-NEXT: s_waitcnt vmcnt(0)362; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v1363; VI-NEXT: v_mul_f32_e32 v2, v1, v2364; VI-NEXT: v_trunc_f32_e32 v2, v2365; VI-NEXT: v_cvt_u32_f32_e32 v3, v2366; VI-NEXT: v_mad_f32 v1, -v2, v0, v1367; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0368; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc369; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0370; VI-NEXT: s_endpgm371;372; EG-LABEL: udiv24_i8_denorm_flush_out:373; EG: ; %bb.0:374; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]375; EG-NEXT: TEX 1 @6376; EG-NEXT: ALU 23, @11, KC0[CB0:0-32], KC1[]377; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X378; EG-NEXT: CF_END379; EG-NEXT: PAD380; EG-NEXT: Fetch clause starting at 6:381; EG-NEXT: VTX_READ_8 T1.X, T0.X, 1, #1382; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1383; EG-NEXT: ALU clause starting at 10:384; EG-NEXT: MOV * T0.X, KC0[2].Z,385; EG-NEXT: ALU clause starting at 11:386; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,387; EG-NEXT: RECIP_IEEE * T0.Z, PS,388; EG-NEXT: UINT_TO_FLT * T0.X, T0.X,389; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z,390; EG-NEXT: TRUNC * T0.W, PV.W,391; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X,392; EG-NEXT: TRUNC * T0.W, PV.W,393; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,394; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,395; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,396; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)397; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,398; EG-NEXT: ADD_INT * T1.W, PS, PV.W,399; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)400; EG-NEXT: AND_INT T1.W, PS, literal.x,401; EG-NEXT: LSHL * T0.W, PV.W, literal.y,402; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)403; EG-NEXT: LSHL T0.X, PV.W, PS,404; EG-NEXT: LSHL * T0.W, literal.x, PS,405; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)406; EG-NEXT: MOV T0.Y, 0.0,407; EG-NEXT: MOV * T0.Z, 0.0,408; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,409; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)410 %den_ptr = getelementptr i8, ptr addrspace(1) %in, i8 1411 %num = load i8, ptr addrspace(1) %in412 %den = load i8, ptr addrspace(1) %den_ptr413 %result = udiv i8 %num, %den414 store i8 %result, ptr addrspace(1) %out415 ret void416}417 418define amdgpu_kernel void @udiv24_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {419; SI-LABEL: udiv24_i16:420; SI: ; %bb.0:421; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9422; SI-NEXT: s_mov_b32 s7, 0xf000423; SI-NEXT: s_mov_b32 s6, -1424; SI-NEXT: s_mov_b32 s10, s6425; SI-NEXT: s_mov_b32 s11, s7426; SI-NEXT: s_waitcnt lgkmcnt(0)427; SI-NEXT: s_mov_b32 s8, s2428; SI-NEXT: s_mov_b32 s9, s3429; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0430; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:2431; SI-NEXT: s_mov_b32 s4, s0432; SI-NEXT: s_mov_b32 s5, s1433; SI-NEXT: s_waitcnt vmcnt(1)434; SI-NEXT: v_cvt_f32_u32_e32 v0, v0435; SI-NEXT: s_waitcnt vmcnt(0)436; SI-NEXT: v_cvt_f32_u32_e32 v1, v1437; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1438; SI-NEXT: v_mul_f32_e32 v2, v0, v2439; SI-NEXT: v_trunc_f32_e32 v2, v2440; SI-NEXT: v_fma_f32 v0, -v2, v1, v0441; SI-NEXT: v_cvt_u32_f32_e32 v2, v2442; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1443; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc444; SI-NEXT: buffer_store_short v0, off, s[4:7], 0445; SI-NEXT: s_endpgm446;447; VI-LABEL: udiv24_i16:448; VI: ; %bb.0:449; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24450; VI-NEXT: s_mov_b32 s7, 0xf000451; VI-NEXT: s_mov_b32 s6, -1452; VI-NEXT: s_mov_b32 s10, s6453; VI-NEXT: s_mov_b32 s11, s7454; VI-NEXT: s_waitcnt lgkmcnt(0)455; VI-NEXT: s_mov_b32 s8, s2456; VI-NEXT: s_mov_b32 s9, s3457; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:2458; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0459; VI-NEXT: s_mov_b32 s4, s0460; VI-NEXT: s_mov_b32 s5, s1461; VI-NEXT: s_waitcnt vmcnt(1)462; VI-NEXT: v_cvt_f32_u32_e32 v0, v0463; VI-NEXT: s_waitcnt vmcnt(0)464; VI-NEXT: v_cvt_f32_u32_e32 v1, v1465; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0466; VI-NEXT: v_mul_f32_e32 v2, v1, v2467; VI-NEXT: v_trunc_f32_e32 v2, v2468; VI-NEXT: v_cvt_u32_f32_e32 v3, v2469; VI-NEXT: v_mad_f32 v1, -v2, v0, v1470; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0471; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc472; VI-NEXT: buffer_store_short v0, off, s[4:7], 0473; VI-NEXT: s_endpgm474;475; EG-LABEL: udiv24_i16:476; EG: ; %bb.0:477; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]478; EG-NEXT: TEX 1 @6479; EG-NEXT: ALU 23, @11, KC0[CB0:0-32], KC1[]480; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X481; EG-NEXT: CF_END482; EG-NEXT: PAD483; EG-NEXT: Fetch clause starting at 6:484; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1485; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1486; EG-NEXT: ALU clause starting at 10:487; EG-NEXT: MOV * T0.X, KC0[2].Z,488; EG-NEXT: ALU clause starting at 11:489; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,490; EG-NEXT: RECIP_IEEE * T0.Z, PS,491; EG-NEXT: UINT_TO_FLT * T0.X, T0.X,492; EG-NEXT: MUL_IEEE * T0.W, PS, T0.Z,493; EG-NEXT: TRUNC * T0.W, PV.W,494; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.X,495; EG-NEXT: TRUNC * T0.W, PV.W,496; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,497; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,498; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,499; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)500; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,501; EG-NEXT: ADD_INT * T1.W, PS, PV.W,502; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)503; EG-NEXT: AND_INT T1.W, PS, literal.x,504; EG-NEXT: LSHL * T0.W, PV.W, literal.y,505; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)506; EG-NEXT: LSHL T0.X, PV.W, PS,507; EG-NEXT: LSHL * T0.W, literal.x, PS,508; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)509; EG-NEXT: MOV T0.Y, 0.0,510; EG-NEXT: MOV * T0.Z, 0.0,511; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,512; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)513 %den_ptr = getelementptr i16, ptr addrspace(1) %in, i16 1514 %num = load i16, ptr addrspace(1) %in, align 2515 %den = load i16, ptr addrspace(1) %den_ptr, align 2516 %result = udiv i16 %num, %den517 store i16 %result, ptr addrspace(1) %out, align 2518 ret void519}520 521define amdgpu_kernel void @udiv23_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {522; SI-LABEL: udiv23_i32:523; SI: ; %bb.0:524; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9525; SI-NEXT: s_waitcnt lgkmcnt(0)526; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0527; SI-NEXT: s_mov_b32 s3, 0xf000528; SI-NEXT: s_mov_b32 s2, -1529; SI-NEXT: s_waitcnt lgkmcnt(0)530; SI-NEXT: s_and_b32 s4, s4, 0x7fffff531; SI-NEXT: s_and_b32 s5, s5, 0x7fffff532; SI-NEXT: v_cvt_f32_u32_e32 v0, s4533; SI-NEXT: v_cvt_f32_u32_e32 v1, s5534; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1535; SI-NEXT: v_mul_f32_e32 v2, v0, v2536; SI-NEXT: v_trunc_f32_e32 v2, v2537; SI-NEXT: v_fma_f32 v0, -v2, v1, v0538; SI-NEXT: v_cvt_u32_f32_e32 v2, v2539; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1540; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc541; SI-NEXT: v_and_b32_e32 v0, 0x7fffff, v0542; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0543; SI-NEXT: s_endpgm544;545; VI-LABEL: udiv23_i32:546; VI: ; %bb.0:547; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24548; VI-NEXT: s_waitcnt lgkmcnt(0)549; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0550; VI-NEXT: s_waitcnt lgkmcnt(0)551; VI-NEXT: s_and_b32 s3, s3, 0x7fffff552; VI-NEXT: v_cvt_f32_u32_e32 v0, s3553; VI-NEXT: s_and_b32 s2, s2, 0x7fffff554; VI-NEXT: v_cvt_f32_u32_e32 v1, s2555; VI-NEXT: s_mov_b32 s3, 0xf000556; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0557; VI-NEXT: s_mov_b32 s2, -1558; VI-NEXT: v_mul_f32_e32 v2, v1, v2559; VI-NEXT: v_trunc_f32_e32 v2, v2560; VI-NEXT: v_cvt_u32_f32_e32 v3, v2561; VI-NEXT: v_mad_f32 v1, -v2, v0, v1562; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0563; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc564; VI-NEXT: v_and_b32_e32 v0, 0x7fffff, v0565; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0566; VI-NEXT: s_endpgm567;568; EG-LABEL: udiv23_i32:569; EG: ; %bb.0:570; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]571; EG-NEXT: TEX 0 @6572; EG-NEXT: ALU 18, @9, KC0[CB0:0-32], KC1[]573; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1574; EG-NEXT: CF_END575; EG-NEXT: PAD576; EG-NEXT: Fetch clause starting at 6:577; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1578; EG-NEXT: ALU clause starting at 8:579; EG-NEXT: MOV * T0.X, KC0[2].Z,580; EG-NEXT: ALU clause starting at 9:581; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,582; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)583; EG-NEXT: UINT_TO_FLT * T0.Y, PV.W,584; EG-NEXT: AND_INT T0.W, T0.X, literal.x,585; EG-NEXT: RECIP_IEEE * T0.X, PS,586; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)587; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,588; EG-NEXT: MUL_IEEE * T0.W, PS, T0.X,589; EG-NEXT: TRUNC * T0.W, PV.W,590; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.Z,591; EG-NEXT: TRUNC * T0.W, PV.W,592; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,593; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,594; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,595; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)596; EG-NEXT: ADD_INT * T0.W, PS, PV.W,597; EG-NEXT: AND_INT T0.X, PV.W, literal.x,598; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,599; EG-NEXT: 8388607(1.175494e-38), 2(2.802597e-45)600 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1601 %num = load i32, ptr addrspace(1) %in, align 4602 %den = load i32, ptr addrspace(1) %den_ptr, align 4603 %num.i23.0 = shl i32 %num, 9604 %den.i23.0 = shl i32 %den, 9605 %num.i23 = lshr i32 %num.i23.0, 9606 %den.i23 = lshr i32 %den.i23.0, 9607 %result = udiv i32 %num.i23, %den.i23608 store i32 %result, ptr addrspace(1) %out, align 4609 ret void610}611 612define amdgpu_kernel void @udiv24_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {613; SI-LABEL: udiv24_i32:614; SI: ; %bb.0:615; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9616; SI-NEXT: s_waitcnt lgkmcnt(0)617; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0618; SI-NEXT: s_mov_b32 s3, 0xf000619; SI-NEXT: s_mov_b32 s2, -1620; SI-NEXT: s_waitcnt lgkmcnt(0)621; SI-NEXT: s_and_b32 s4, s4, 0xffffff622; SI-NEXT: s_and_b32 s5, s5, 0xffffff623; SI-NEXT: v_cvt_f32_u32_e32 v0, s4624; SI-NEXT: v_cvt_f32_u32_e32 v1, s5625; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1626; SI-NEXT: v_mul_f32_e32 v2, v0, v2627; SI-NEXT: v_trunc_f32_e32 v2, v2628; SI-NEXT: v_fma_f32 v0, -v2, v1, v0629; SI-NEXT: v_cvt_u32_f32_e32 v2, v2630; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1631; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc632; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v0633; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0634; SI-NEXT: s_endpgm635;636; VI-LABEL: udiv24_i32:637; VI: ; %bb.0:638; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24639; VI-NEXT: s_waitcnt lgkmcnt(0)640; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0641; VI-NEXT: s_waitcnt lgkmcnt(0)642; VI-NEXT: s_and_b32 s3, s3, 0xffffff643; VI-NEXT: v_cvt_f32_u32_e32 v0, s3644; VI-NEXT: s_and_b32 s2, s2, 0xffffff645; VI-NEXT: v_cvt_f32_u32_e32 v1, s2646; VI-NEXT: s_mov_b32 s3, 0xf000647; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0648; VI-NEXT: s_mov_b32 s2, -1649; VI-NEXT: v_mul_f32_e32 v2, v1, v2650; VI-NEXT: v_trunc_f32_e32 v2, v2651; VI-NEXT: v_cvt_u32_f32_e32 v3, v2652; VI-NEXT: v_mad_f32 v1, -v2, v0, v1653; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0654; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc655; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v0656; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0657; VI-NEXT: s_endpgm658;659; EG-LABEL: udiv24_i32:660; EG: ; %bb.0:661; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]662; EG-NEXT: TEX 0 @6663; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]664; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1665; EG-NEXT: CF_END666; EG-NEXT: PAD667; EG-NEXT: Fetch clause starting at 6:668; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1669; EG-NEXT: ALU clause starting at 8:670; EG-NEXT: MOV * T0.X, KC0[2].Z,671; EG-NEXT: ALU clause starting at 9:672; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,673; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)674; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,675; EG-NEXT: RECIP_UINT * T0.Y, PV.W,676; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,677; EG-NEXT: MULHI * T0.Z, T0.Y, PS,678; EG-NEXT: ADD_INT T1.W, T0.Y, PS,679; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,680; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)681; EG-NEXT: MULHI * T0.X, PS, PV.W,682; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,683; EG-NEXT: SUB_INT * T1.W, T2.W, PS,684; EG-NEXT: ADD_INT T0.Z, T0.X, 1,685; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,686; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,687; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,688; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,689; EG-NEXT: ADD_INT T3.W, PS, 1,690; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,691; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,692; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,693; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)694 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1695 %num = load i32, ptr addrspace(1) %in, align 4696 %den = load i32, ptr addrspace(1) %den_ptr, align 4697 %num.i24.0 = shl i32 %num, 8698 %den.i24.0 = shl i32 %den, 8699 %num.i24 = lshr i32 %num.i24.0, 8700 %den.i24 = lshr i32 %den.i24.0, 8701 %result = udiv i32 %num.i24, %den.i24702 store i32 %result, ptr addrspace(1) %out, align 4703 ret void704}705 706define amdgpu_kernel void @no_udiv24_u23_u24_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {707; SI-LABEL: no_udiv24_u23_u24_i32:708; SI: ; %bb.0:709; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9710; SI-NEXT: s_waitcnt lgkmcnt(0)711; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0712; SI-NEXT: s_mov_b32 s3, 0xf000713; SI-NEXT: s_mov_b32 s2, -1714; SI-NEXT: s_waitcnt lgkmcnt(0)715; SI-NEXT: s_and_b32 s4, s4, 0x7fffff716; SI-NEXT: s_and_b32 s5, s5, 0xffffff717; SI-NEXT: v_cvt_f32_u32_e32 v0, s4718; SI-NEXT: v_cvt_f32_u32_e32 v1, s5719; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1720; SI-NEXT: v_mul_f32_e32 v2, v0, v2721; SI-NEXT: v_trunc_f32_e32 v2, v2722; SI-NEXT: v_fma_f32 v0, -v2, v1, v0723; SI-NEXT: v_cvt_u32_f32_e32 v2, v2724; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1725; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc726; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v0727; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0728; SI-NEXT: s_endpgm729;730; VI-LABEL: no_udiv24_u23_u24_i32:731; VI: ; %bb.0:732; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24733; VI-NEXT: s_waitcnt lgkmcnt(0)734; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0735; VI-NEXT: s_waitcnt lgkmcnt(0)736; VI-NEXT: s_and_b32 s3, s3, 0xffffff737; VI-NEXT: v_cvt_f32_u32_e32 v0, s3738; VI-NEXT: s_and_b32 s2, s2, 0x7fffff739; VI-NEXT: v_cvt_f32_u32_e32 v1, s2740; VI-NEXT: s_mov_b32 s3, 0xf000741; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0742; VI-NEXT: s_mov_b32 s2, -1743; VI-NEXT: v_mul_f32_e32 v2, v1, v2744; VI-NEXT: v_trunc_f32_e32 v2, v2745; VI-NEXT: v_cvt_u32_f32_e32 v3, v2746; VI-NEXT: v_mad_f32 v1, -v2, v0, v1747; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0748; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc749; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v0750; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0751; VI-NEXT: s_endpgm752;753; EG-LABEL: no_udiv24_u23_u24_i32:754; EG: ; %bb.0:755; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]756; EG-NEXT: TEX 0 @6757; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]758; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1759; EG-NEXT: CF_END760; EG-NEXT: PAD761; EG-NEXT: Fetch clause starting at 6:762; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1763; EG-NEXT: ALU clause starting at 8:764; EG-NEXT: MOV * T0.X, KC0[2].Z,765; EG-NEXT: ALU clause starting at 9:766; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,767; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)768; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,769; EG-NEXT: RECIP_UINT * T0.Y, PV.W,770; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,771; EG-NEXT: MULHI * T0.Z, T0.Y, PS,772; EG-NEXT: ADD_INT T1.W, T0.Y, PS,773; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,774; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)775; EG-NEXT: MULHI * T0.X, PS, PV.W,776; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,777; EG-NEXT: SUB_INT * T1.W, T2.W, PS,778; EG-NEXT: ADD_INT T0.Z, T0.X, 1,779; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,780; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,781; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,782; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,783; EG-NEXT: ADD_INT T3.W, PS, 1,784; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,785; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,786; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,787; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)788 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1789 %num = load i32, ptr addrspace(1) %in, align 4790 %den = load i32, ptr addrspace(1) %den_ptr, align 4791 %num.i23.0 = shl i32 %num, 9792 %den.i24.0 = shl i32 %den, 8793 %num.i23 = lshr i32 %num.i23.0, 9794 %den.i24 = lshr i32 %den.i24.0, 8795 %result = udiv i32 %num.i23, %den.i24796 store i32 %result, ptr addrspace(1) %out, align 4797 ret void798}799 800define amdgpu_kernel void @no_udiv24_u24_u23_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {801; SI-LABEL: no_udiv24_u24_u23_i32:802; SI: ; %bb.0:803; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9804; SI-NEXT: s_waitcnt lgkmcnt(0)805; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0806; SI-NEXT: s_mov_b32 s3, 0xf000807; SI-NEXT: s_mov_b32 s2, -1808; SI-NEXT: s_waitcnt lgkmcnt(0)809; SI-NEXT: s_and_b32 s4, s4, 0xffffff810; SI-NEXT: s_and_b32 s5, s5, 0x7fffff811; SI-NEXT: v_cvt_f32_u32_e32 v0, s4812; SI-NEXT: v_cvt_f32_u32_e32 v1, s5813; SI-NEXT: v_rcp_iflag_f32_e32 v2, v1814; SI-NEXT: v_mul_f32_e32 v2, v0, v2815; SI-NEXT: v_trunc_f32_e32 v2, v2816; SI-NEXT: v_fma_f32 v0, -v2, v1, v0817; SI-NEXT: v_cvt_u32_f32_e32 v2, v2818; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1819; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc820; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v0821; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0822; SI-NEXT: s_endpgm823;824; VI-LABEL: no_udiv24_u24_u23_i32:825; VI: ; %bb.0:826; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24827; VI-NEXT: s_waitcnt lgkmcnt(0)828; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0829; VI-NEXT: s_waitcnt lgkmcnt(0)830; VI-NEXT: s_and_b32 s3, s3, 0x7fffff831; VI-NEXT: v_cvt_f32_u32_e32 v0, s3832; VI-NEXT: s_and_b32 s2, s2, 0xffffff833; VI-NEXT: v_cvt_f32_u32_e32 v1, s2834; VI-NEXT: s_mov_b32 s3, 0xf000835; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0836; VI-NEXT: s_mov_b32 s2, -1837; VI-NEXT: v_mul_f32_e32 v2, v1, v2838; VI-NEXT: v_trunc_f32_e32 v2, v2839; VI-NEXT: v_cvt_u32_f32_e32 v3, v2840; VI-NEXT: v_mad_f32 v1, -v2, v0, v1841; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0842; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc843; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v0844; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0845; VI-NEXT: s_endpgm846;847; EG-LABEL: no_udiv24_u24_u23_i32:848; EG: ; %bb.0:849; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]850; EG-NEXT: TEX 0 @6851; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]852; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1853; EG-NEXT: CF_END854; EG-NEXT: PAD855; EG-NEXT: Fetch clause starting at 6:856; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1857; EG-NEXT: ALU clause starting at 8:858; EG-NEXT: MOV * T0.X, KC0[2].Z,859; EG-NEXT: ALU clause starting at 9:860; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,861; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)862; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,863; EG-NEXT: RECIP_UINT * T0.Y, PV.W,864; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,865; EG-NEXT: MULHI * T0.Z, T0.Y, PS,866; EG-NEXT: ADD_INT T1.W, T0.Y, PS,867; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,868; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)869; EG-NEXT: MULHI * T0.X, PS, PV.W,870; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,871; EG-NEXT: SUB_INT * T1.W, T2.W, PS,872; EG-NEXT: ADD_INT T0.Z, T0.X, 1,873; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,874; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,875; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,876; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,877; EG-NEXT: ADD_INT T3.W, PS, 1,878; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,879; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,880; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,881; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)882 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 1883 %num = load i32, ptr addrspace(1) %in, align 4884 %den = load i32, ptr addrspace(1) %den_ptr, align 4885 %num.i24.0 = shl i32 %num, 8886 %den.i23.0 = shl i32 %den, 9887 %num.i24 = lshr i32 %num.i24.0, 8888 %den.i23 = lshr i32 %den.i23.0, 9889 %result = udiv i32 %num.i24, %den.i23890 store i32 %result, ptr addrspace(1) %out, align 4891 ret void892}893 894; RCP_IFLAG is for URECIP in the full 32b alg895define amdgpu_kernel void @udiv25_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {896; SI-LABEL: udiv25_i32:897; SI: ; %bb.0:898; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9899; SI-NEXT: s_waitcnt lgkmcnt(0)900; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0901; SI-NEXT: s_mov_b32 s3, 0xf000902; SI-NEXT: s_mov_b32 s2, -1903; SI-NEXT: s_waitcnt lgkmcnt(0)904; SI-NEXT: s_and_b32 s4, s4, 0x1ffffff905; SI-NEXT: s_and_b32 s5, s5, 0x1ffffff906; SI-NEXT: v_cvt_f32_u32_e32 v0, s5907; SI-NEXT: s_sub_i32 s6, 0, s5908; SI-NEXT: v_rcp_iflag_f32_e32 v0, v0909; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0910; SI-NEXT: v_cvt_u32_f32_e32 v0, v0911; SI-NEXT: v_mul_lo_u32 v1, s6, v0912; SI-NEXT: v_mul_hi_u32 v1, v0, v1913; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v1914; SI-NEXT: v_mul_hi_u32 v0, s4, v0915; SI-NEXT: v_readfirstlane_b32 s6, v0916; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v0917; SI-NEXT: s_mul_i32 s6, s6, s5918; SI-NEXT: s_sub_i32 s4, s4, s6919; SI-NEXT: s_sub_i32 s6, s4, s5920; SI-NEXT: s_cmp_ge_u32 s4, s5921; SI-NEXT: s_cselect_b64 vcc, -1, 0922; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc923; SI-NEXT: s_cselect_b32 s4, s6, s4924; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v0925; SI-NEXT: s_cmp_ge_u32 s4, s5926; SI-NEXT: s_cselect_b64 vcc, -1, 0927; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc928; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0929; SI-NEXT: s_endpgm930;931; VI-LABEL: udiv25_i32:932; VI: ; %bb.0:933; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24934; VI-NEXT: s_waitcnt lgkmcnt(0)935; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0936; VI-NEXT: s_waitcnt lgkmcnt(0)937; VI-NEXT: s_and_b32 s4, s3, 0x1ffffff938; VI-NEXT: v_cvt_f32_u32_e32 v0, s4939; VI-NEXT: s_sub_i32 s3, 0, s4940; VI-NEXT: s_and_b32 s5, s2, 0x1ffffff941; VI-NEXT: s_mov_b32 s2, -1942; VI-NEXT: v_rcp_iflag_f32_e32 v0, v0943; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0944; VI-NEXT: v_cvt_u32_f32_e32 v0, v0945; VI-NEXT: v_mul_lo_u32 v1, s3, v0946; VI-NEXT: s_mov_b32 s3, 0xf000947; VI-NEXT: v_mul_hi_u32 v1, v0, v1948; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1949; VI-NEXT: v_mul_hi_u32 v0, s5, v0950; VI-NEXT: v_readfirstlane_b32 s6, v0951; VI-NEXT: s_mul_i32 s6, s6, s4952; VI-NEXT: s_sub_i32 s5, s5, s6953; VI-NEXT: s_sub_i32 s6, s5, s4954; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0955; VI-NEXT: s_cmp_ge_u32 s5, s4956; VI-NEXT: s_cselect_b64 vcc, -1, 0957; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc958; VI-NEXT: s_cselect_b32 s5, s6, s5959; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0960; VI-NEXT: s_cmp_ge_u32 s5, s4961; VI-NEXT: s_cselect_b64 vcc, -1, 0962; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc963; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0964; VI-NEXT: s_endpgm965;966; EG-LABEL: udiv25_i32:967; EG: ; %bb.0:968; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]969; EG-NEXT: TEX 0 @6970; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]971; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1972; EG-NEXT: CF_END973; EG-NEXT: PAD974; EG-NEXT: Fetch clause starting at 6:975; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1976; EG-NEXT: ALU clause starting at 8:977; EG-NEXT: MOV * T0.X, KC0[2].Z,978; EG-NEXT: ALU clause starting at 9:979; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,980; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)981; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,982; EG-NEXT: RECIP_UINT * T0.Y, PV.W,983; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,984; EG-NEXT: MULHI * T0.Z, T0.Y, PS,985; EG-NEXT: ADD_INT T1.W, T0.Y, PS,986; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,987; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)988; EG-NEXT: MULHI * T0.X, PS, PV.W,989; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,990; EG-NEXT: SUB_INT * T1.W, T2.W, PS,991; EG-NEXT: ADD_INT T0.Z, T0.X, 1,992; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,993; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,994; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,995; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,996; EG-NEXT: ADD_INT T3.W, PS, 1,997; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,998; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,999; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1000; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1001 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11002 %num = load i32, ptr addrspace(1) %in, align 41003 %den = load i32, ptr addrspace(1) %den_ptr, align 41004 %num.i25.0 = shl i32 %num, 71005 %den.i25.0 = shl i32 %den, 71006 %num.i25 = lshr i32 %num.i25.0, 71007 %den.i25 = lshr i32 %den.i25.0, 71008 %result = udiv i32 %num.i25, %den.i251009 store i32 %result, ptr addrspace(1) %out, align 41010 ret void1011}1012 1013; RCP_IFLAG is for URECIP in the full 32b alg1014define amdgpu_kernel void @test_no_udiv24_i32_1(ptr addrspace(1) %out, ptr addrspace(1) %in) {1015; SI-LABEL: test_no_udiv24_i32_1:1016; SI: ; %bb.0:1017; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91018; SI-NEXT: s_waitcnt lgkmcnt(0)1019; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01020; SI-NEXT: s_mov_b32 s3, 0xf0001021; SI-NEXT: s_mov_b32 s2, -11022; SI-NEXT: s_waitcnt lgkmcnt(0)1023; SI-NEXT: s_and_b32 s4, s4, 0xffffff1024; SI-NEXT: s_and_b32 s5, s5, 0x1ffffff1025; SI-NEXT: v_cvt_f32_u32_e32 v0, s51026; SI-NEXT: s_sub_i32 s6, 0, s51027; SI-NEXT: v_rcp_iflag_f32_e32 v0, v01028; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01029; SI-NEXT: v_cvt_u32_f32_e32 v0, v01030; SI-NEXT: v_mul_lo_u32 v1, s6, v01031; SI-NEXT: v_mul_hi_u32 v1, v0, v11032; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v11033; SI-NEXT: v_mul_hi_u32 v0, s4, v01034; SI-NEXT: v_readfirstlane_b32 s6, v01035; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v01036; SI-NEXT: s_mul_i32 s6, s6, s51037; SI-NEXT: s_sub_i32 s4, s4, s61038; SI-NEXT: s_sub_i32 s6, s4, s51039; SI-NEXT: s_cmp_ge_u32 s4, s51040; SI-NEXT: s_cselect_b64 vcc, -1, 01041; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1042; SI-NEXT: s_cselect_b32 s4, s6, s41043; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v01044; SI-NEXT: s_cmp_ge_u32 s4, s51045; SI-NEXT: s_cselect_b64 vcc, -1, 01046; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1047; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01048; SI-NEXT: s_endpgm1049;1050; VI-LABEL: test_no_udiv24_i32_1:1051; VI: ; %bb.0:1052; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241053; VI-NEXT: s_waitcnt lgkmcnt(0)1054; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01055; VI-NEXT: s_waitcnt lgkmcnt(0)1056; VI-NEXT: s_and_b32 s4, s3, 0x1ffffff1057; VI-NEXT: v_cvt_f32_u32_e32 v0, s41058; VI-NEXT: s_sub_i32 s3, 0, s41059; VI-NEXT: s_and_b32 s5, s2, 0xffffff1060; VI-NEXT: s_mov_b32 s2, -11061; VI-NEXT: v_rcp_iflag_f32_e32 v0, v01062; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01063; VI-NEXT: v_cvt_u32_f32_e32 v0, v01064; VI-NEXT: v_mul_lo_u32 v1, s3, v01065; VI-NEXT: s_mov_b32 s3, 0xf0001066; VI-NEXT: v_mul_hi_u32 v1, v0, v11067; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v11068; VI-NEXT: v_mul_hi_u32 v0, s5, v01069; VI-NEXT: v_readfirstlane_b32 s6, v01070; VI-NEXT: s_mul_i32 s6, s6, s41071; VI-NEXT: s_sub_i32 s5, s5, s61072; VI-NEXT: s_sub_i32 s6, s5, s41073; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v01074; VI-NEXT: s_cmp_ge_u32 s5, s41075; VI-NEXT: s_cselect_b64 vcc, -1, 01076; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1077; VI-NEXT: s_cselect_b32 s5, s6, s51078; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v01079; VI-NEXT: s_cmp_ge_u32 s5, s41080; VI-NEXT: s_cselect_b64 vcc, -1, 01081; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1082; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01083; VI-NEXT: s_endpgm1084;1085; EG-LABEL: test_no_udiv24_i32_1:1086; EG: ; %bb.0:1087; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1088; EG-NEXT: TEX 0 @61089; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]1090; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11091; EG-NEXT: CF_END1092; EG-NEXT: PAD1093; EG-NEXT: Fetch clause starting at 6:1094; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11095; EG-NEXT: ALU clause starting at 8:1096; EG-NEXT: MOV * T0.X, KC0[2].Z,1097; EG-NEXT: ALU clause starting at 9:1098; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,1099; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)1100; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,1101; EG-NEXT: RECIP_UINT * T0.Y, PV.W,1102; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,1103; EG-NEXT: MULHI * T0.Z, T0.Y, PS,1104; EG-NEXT: ADD_INT T1.W, T0.Y, PS,1105; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,1106; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1107; EG-NEXT: MULHI * T0.X, PS, PV.W,1108; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,1109; EG-NEXT: SUB_INT * T1.W, T2.W, PS,1110; EG-NEXT: ADD_INT T0.Z, T0.X, 1,1111; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1112; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,1113; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,1114; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,1115; EG-NEXT: ADD_INT T3.W, PS, 1,1116; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,1117; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,1118; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1119; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1120 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11121 %num = load i32, ptr addrspace(1) %in, align 41122 %den = load i32, ptr addrspace(1) %den_ptr, align 41123 %num.i24.0 = shl i32 %num, 81124 %den.i24.0 = shl i32 %den, 71125 %num.i24 = lshr i32 %num.i24.0, 81126 %den.i24 = lshr i32 %den.i24.0, 71127 %result = udiv i32 %num.i24, %den.i241128 store i32 %result, ptr addrspace(1) %out, align 41129 ret void1130}1131 1132; RCP_IFLAG is for URECIP in the full 32b alg1133define amdgpu_kernel void @test_no_udiv24_i32_2(ptr addrspace(1) %out, ptr addrspace(1) %in) {1134; SI-LABEL: test_no_udiv24_i32_2:1135; SI: ; %bb.0:1136; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91137; SI-NEXT: s_waitcnt lgkmcnt(0)1138; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01139; SI-NEXT: s_mov_b32 s3, 0xf0001140; SI-NEXT: s_mov_b32 s2, -11141; SI-NEXT: s_waitcnt lgkmcnt(0)1142; SI-NEXT: s_and_b32 s4, s4, 0x1ffffff1143; SI-NEXT: s_and_b32 s5, s5, 0xffffff1144; SI-NEXT: v_cvt_f32_u32_e32 v0, s51145; SI-NEXT: s_sub_i32 s6, 0, s51146; SI-NEXT: v_rcp_iflag_f32_e32 v0, v01147; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01148; SI-NEXT: v_cvt_u32_f32_e32 v0, v01149; SI-NEXT: v_mul_lo_u32 v1, s6, v01150; SI-NEXT: v_mul_hi_u32 v1, v0, v11151; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v11152; SI-NEXT: v_mul_hi_u32 v0, s4, v01153; SI-NEXT: v_readfirstlane_b32 s6, v01154; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v01155; SI-NEXT: s_mul_i32 s6, s6, s51156; SI-NEXT: s_sub_i32 s4, s4, s61157; SI-NEXT: s_sub_i32 s6, s4, s51158; SI-NEXT: s_cmp_ge_u32 s4, s51159; SI-NEXT: s_cselect_b64 vcc, -1, 01160; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1161; SI-NEXT: s_cselect_b32 s4, s6, s41162; SI-NEXT: v_add_i32_e32 v1, vcc, 1, v01163; SI-NEXT: s_cmp_ge_u32 s4, s51164; SI-NEXT: s_cselect_b64 vcc, -1, 01165; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1166; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01167; SI-NEXT: s_endpgm1168;1169; VI-LABEL: test_no_udiv24_i32_2:1170; VI: ; %bb.0:1171; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241172; VI-NEXT: s_waitcnt lgkmcnt(0)1173; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01174; VI-NEXT: s_waitcnt lgkmcnt(0)1175; VI-NEXT: s_and_b32 s4, s3, 0xffffff1176; VI-NEXT: v_cvt_f32_u32_e32 v0, s41177; VI-NEXT: s_sub_i32 s3, 0, s41178; VI-NEXT: s_and_b32 s5, s2, 0x1ffffff1179; VI-NEXT: s_mov_b32 s2, -11180; VI-NEXT: v_rcp_iflag_f32_e32 v0, v01181; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01182; VI-NEXT: v_cvt_u32_f32_e32 v0, v01183; VI-NEXT: v_mul_lo_u32 v1, s3, v01184; VI-NEXT: s_mov_b32 s3, 0xf0001185; VI-NEXT: v_mul_hi_u32 v1, v0, v11186; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v11187; VI-NEXT: v_mul_hi_u32 v0, s5, v01188; VI-NEXT: v_readfirstlane_b32 s6, v01189; VI-NEXT: s_mul_i32 s6, s6, s41190; VI-NEXT: s_sub_i32 s5, s5, s61191; VI-NEXT: s_sub_i32 s6, s5, s41192; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v01193; VI-NEXT: s_cmp_ge_u32 s5, s41194; VI-NEXT: s_cselect_b64 vcc, -1, 01195; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1196; VI-NEXT: s_cselect_b32 s5, s6, s51197; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v01198; VI-NEXT: s_cmp_ge_u32 s5, s41199; VI-NEXT: s_cselect_b64 vcc, -1, 01200; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc1201; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01202; VI-NEXT: s_endpgm1203;1204; EG-LABEL: test_no_udiv24_i32_2:1205; EG: ; %bb.0:1206; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1207; EG-NEXT: TEX 0 @61208; EG-NEXT: ALU 21, @9, KC0[CB0:0-32], KC1[]1209; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11210; EG-NEXT: CF_END1211; EG-NEXT: PAD1212; EG-NEXT: Fetch clause starting at 6:1213; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11214; EG-NEXT: ALU clause starting at 8:1215; EG-NEXT: MOV * T0.X, KC0[2].Z,1216; EG-NEXT: ALU clause starting at 9:1217; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,1218; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1219; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,1220; EG-NEXT: RECIP_UINT * T0.Y, PV.W,1221; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,1222; EG-NEXT: MULHI * T0.Z, T0.Y, PS,1223; EG-NEXT: ADD_INT T1.W, T0.Y, PS,1224; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,1225; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)1226; EG-NEXT: MULHI * T0.X, PS, PV.W,1227; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,1228; EG-NEXT: SUB_INT * T1.W, T2.W, PS,1229; EG-NEXT: ADD_INT T0.Z, T0.X, 1,1230; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1231; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,1232; EG-NEXT: CNDE_INT T1.W, PV.W, T1.W, PS,1233; EG-NEXT: CNDE_INT * T2.W, PV.W, T0.X, PV.Z,1234; EG-NEXT: ADD_INT T3.W, PS, 1,1235; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,1236; EG-NEXT: CNDE_INT T0.X, PS, T2.W, PV.W,1237; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1238; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1239 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11240 %num = load i32, ptr addrspace(1) %in, align 41241 %den = load i32, ptr addrspace(1) %den_ptr, align 41242 %num.i24.0 = shl i32 %num, 71243 %den.i24.0 = shl i32 %den, 81244 %num.i24 = lshr i32 %num.i24.0, 71245 %den.i24 = lshr i32 %den.i24.0, 81246 %result = udiv i32 %num.i24, %den.i241247 store i32 %result, ptr addrspace(1) %out, align 41248 ret void1249}1250 1251define amdgpu_kernel void @urem24_i8(ptr addrspace(1) %out, ptr addrspace(1) %in) {1252; SI-LABEL: urem24_i8:1253; SI: ; %bb.0:1254; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91255; SI-NEXT: s_mov_b32 s7, 0xf0001256; SI-NEXT: s_mov_b32 s6, -11257; SI-NEXT: s_mov_b32 s10, s61258; SI-NEXT: s_mov_b32 s11, s71259; SI-NEXT: s_waitcnt lgkmcnt(0)1260; SI-NEXT: s_mov_b32 s8, s21261; SI-NEXT: s_mov_b32 s9, s31262; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 01263; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:11264; SI-NEXT: s_mov_b32 s4, s01265; SI-NEXT: s_mov_b32 s5, s11266; SI-NEXT: s_waitcnt vmcnt(1)1267; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v01268; SI-NEXT: s_waitcnt vmcnt(0)1269; SI-NEXT: v_cvt_f32_ubyte0_e32 v3, v11270; SI-NEXT: v_rcp_iflag_f32_e32 v4, v31271; SI-NEXT: v_mul_f32_e32 v4, v2, v41272; SI-NEXT: v_trunc_f32_e32 v4, v41273; SI-NEXT: v_fma_f32 v2, -v4, v3, v21274; SI-NEXT: v_cvt_u32_f32_e32 v4, v41275; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v31276; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc1277; SI-NEXT: v_mul_lo_u32 v1, v2, v11278; SI-NEXT: v_subrev_i32_e32 v0, vcc, v1, v01279; SI-NEXT: buffer_store_byte v0, off, s[4:7], 01280; SI-NEXT: s_endpgm1281;1282; VI-LABEL: urem24_i8:1283; VI: ; %bb.0:1284; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241285; VI-NEXT: s_mov_b32 s7, 0xf0001286; VI-NEXT: s_mov_b32 s6, -11287; VI-NEXT: s_mov_b32 s10, s61288; VI-NEXT: s_mov_b32 s11, s71289; VI-NEXT: s_waitcnt lgkmcnt(0)1290; VI-NEXT: s_mov_b32 s8, s21291; VI-NEXT: s_mov_b32 s9, s31292; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:11293; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 01294; VI-NEXT: s_mov_b32 s4, s01295; VI-NEXT: s_mov_b32 s5, s11296; VI-NEXT: s_waitcnt vmcnt(1)1297; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v01298; VI-NEXT: v_rcp_iflag_f32_e32 v3, v21299; VI-NEXT: s_waitcnt vmcnt(0)1300; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v11301; VI-NEXT: v_mul_f32_e32 v3, v4, v31302; VI-NEXT: v_trunc_f32_e32 v3, v31303; VI-NEXT: v_cvt_u32_f32_e32 v5, v31304; VI-NEXT: v_mad_f32 v3, -v3, v2, v41305; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v21306; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc1307; VI-NEXT: v_mul_lo_u32 v0, v2, v01308; VI-NEXT: v_subrev_u32_e32 v0, vcc, v0, v11309; VI-NEXT: buffer_store_byte v0, off, s[4:7], 01310; VI-NEXT: s_endpgm1311;1312; EG-LABEL: urem24_i8:1313; EG: ; %bb.0:1314; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]1315; EG-NEXT: TEX 1 @61316; EG-NEXT: ALU 25, @11, KC0[CB0:0-32], KC1[]1317; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1318; EG-NEXT: CF_END1319; EG-NEXT: PAD1320; EG-NEXT: Fetch clause starting at 6:1321; EG-NEXT: VTX_READ_8 T1.X, T0.X, 1, #11322; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11323; EG-NEXT: ALU clause starting at 10:1324; EG-NEXT: MOV * T0.X, KC0[2].Z,1325; EG-NEXT: ALU clause starting at 11:1326; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,1327; EG-NEXT: RECIP_IEEE * T0.Z, PS,1328; EG-NEXT: UINT_TO_FLT * T0.W, T0.X,1329; EG-NEXT: MUL_IEEE * T1.W, PS, T0.Z,1330; EG-NEXT: TRUNC * T1.W, PV.W,1331; EG-NEXT: MULADD_IEEE T0.W, -PV.W, T0.Y, T0.W,1332; EG-NEXT: TRUNC * T1.W, PV.W,1333; EG-NEXT: SETGE * T0.W, |PV.W|, T0.Y,1334; EG-NEXT: CNDE T0.W, PV.W, 0.0, literal.x,1335; EG-NEXT: FLT_TO_UINT * T0.Y, T1.W,1336; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)1337; EG-NEXT: ADD_INT * T0.W, PS, PV.W,1338; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.X,1339; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,1340; EG-NEXT: SUB_INT * T1.W, T0.X, PS,1341; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1342; EG-NEXT: AND_INT T1.W, PS, literal.x,1343; EG-NEXT: LSHL * T0.W, PV.W, literal.y,1344; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)1345; EG-NEXT: LSHL T0.X, PV.W, PS,1346; EG-NEXT: LSHL * T0.W, literal.x, PS,1347; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)1348; EG-NEXT: MOV T0.Y, 0.0,1349; EG-NEXT: MOV * T0.Z, 0.0,1350; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1351; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1352 %den_ptr = getelementptr i8, ptr addrspace(1) %in, i8 11353 %num = load i8, ptr addrspace(1) %in1354 %den = load i8, ptr addrspace(1) %den_ptr1355 %result = urem i8 %num, %den1356 store i8 %result, ptr addrspace(1) %out1357 ret void1358}1359 1360define amdgpu_kernel void @urem24_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {1361; SI-LABEL: urem24_i16:1362; SI: ; %bb.0:1363; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91364; SI-NEXT: s_mov_b32 s7, 0xf0001365; SI-NEXT: s_mov_b32 s6, -11366; SI-NEXT: s_mov_b32 s10, s61367; SI-NEXT: s_mov_b32 s11, s71368; SI-NEXT: s_waitcnt lgkmcnt(0)1369; SI-NEXT: s_mov_b32 s8, s21370; SI-NEXT: s_mov_b32 s9, s31371; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 01372; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:21373; SI-NEXT: s_mov_b32 s4, s01374; SI-NEXT: s_mov_b32 s5, s11375; SI-NEXT: s_waitcnt vmcnt(1)1376; SI-NEXT: v_cvt_f32_u32_e32 v2, v01377; SI-NEXT: s_waitcnt vmcnt(0)1378; SI-NEXT: v_cvt_f32_u32_e32 v3, v11379; SI-NEXT: v_rcp_iflag_f32_e32 v4, v31380; SI-NEXT: v_mul_f32_e32 v4, v2, v41381; SI-NEXT: v_trunc_f32_e32 v4, v41382; SI-NEXT: v_fma_f32 v2, -v4, v3, v21383; SI-NEXT: v_cvt_u32_f32_e32 v4, v41384; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v31385; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc1386; SI-NEXT: v_mul_lo_u32 v1, v2, v11387; SI-NEXT: v_subrev_i32_e32 v0, vcc, v1, v01388; SI-NEXT: buffer_store_short v0, off, s[4:7], 01389; SI-NEXT: s_endpgm1390;1391; VI-LABEL: urem24_i16:1392; VI: ; %bb.0:1393; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241394; VI-NEXT: s_mov_b32 s7, 0xf0001395; VI-NEXT: s_mov_b32 s6, -11396; VI-NEXT: s_mov_b32 s10, s61397; VI-NEXT: s_mov_b32 s11, s71398; VI-NEXT: s_waitcnt lgkmcnt(0)1399; VI-NEXT: s_mov_b32 s8, s21400; VI-NEXT: s_mov_b32 s9, s31401; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:21402; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 01403; VI-NEXT: s_mov_b32 s4, s01404; VI-NEXT: s_mov_b32 s5, s11405; VI-NEXT: s_waitcnt vmcnt(1)1406; VI-NEXT: v_cvt_f32_u32_e32 v2, v01407; VI-NEXT: s_waitcnt vmcnt(0)1408; VI-NEXT: v_cvt_f32_u32_e32 v3, v11409; VI-NEXT: v_rcp_iflag_f32_e32 v4, v21410; VI-NEXT: v_mul_f32_e32 v4, v3, v41411; VI-NEXT: v_trunc_f32_e32 v4, v41412; VI-NEXT: v_cvt_u32_f32_e32 v5, v41413; VI-NEXT: v_mad_f32 v3, -v4, v2, v31414; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v21415; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc1416; VI-NEXT: v_mul_lo_u32 v0, v2, v01417; VI-NEXT: v_subrev_u32_e32 v0, vcc, v0, v11418; VI-NEXT: buffer_store_short v0, off, s[4:7], 01419; VI-NEXT: s_endpgm1420;1421; EG-LABEL: urem24_i16:1422; EG: ; %bb.0:1423; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]1424; EG-NEXT: TEX 1 @61425; EG-NEXT: ALU 25, @11, KC0[CB0:0-32], KC1[]1426; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1427; EG-NEXT: CF_END1428; EG-NEXT: PAD1429; EG-NEXT: Fetch clause starting at 6:1430; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #11431; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11432; EG-NEXT: ALU clause starting at 10:1433; EG-NEXT: MOV * T0.X, KC0[2].Z,1434; EG-NEXT: ALU clause starting at 11:1435; EG-NEXT: UINT_TO_FLT * T0.Y, T1.X,1436; EG-NEXT: RECIP_IEEE * T0.Z, PS,1437; EG-NEXT: UINT_TO_FLT * T0.W, T0.X,1438; EG-NEXT: MUL_IEEE * T1.W, PS, T0.Z,1439; EG-NEXT: TRUNC * T1.W, PV.W,1440; EG-NEXT: MULADD_IEEE T0.W, -PV.W, T0.Y, T0.W,1441; EG-NEXT: TRUNC * T1.W, PV.W,1442; EG-NEXT: SETGE * T0.W, |PV.W|, T0.Y,1443; EG-NEXT: CNDE T0.W, PV.W, 0.0, literal.x,1444; EG-NEXT: FLT_TO_UINT * T0.Y, T1.W,1445; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)1446; EG-NEXT: ADD_INT * T0.W, PS, PV.W,1447; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.X,1448; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,1449; EG-NEXT: SUB_INT * T1.W, T0.X, PS,1450; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1451; EG-NEXT: AND_INT T1.W, PS, literal.x,1452; EG-NEXT: LSHL * T0.W, PV.W, literal.y,1453; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1454; EG-NEXT: LSHL T0.X, PV.W, PS,1455; EG-NEXT: LSHL * T0.W, literal.x, PS,1456; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1457; EG-NEXT: MOV T0.Y, 0.0,1458; EG-NEXT: MOV * T0.Z, 0.0,1459; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1460; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1461 %den_ptr = getelementptr i16, ptr addrspace(1) %in, i16 11462 %num = load i16, ptr addrspace(1) %in, align 21463 %den = load i16, ptr addrspace(1) %den_ptr, align 21464 %result = urem i16 %num, %den1465 store i16 %result, ptr addrspace(1) %out, align 21466 ret void1467}1468 1469define amdgpu_kernel void @urem24_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {1470; SI-LABEL: urem24_i32:1471; SI: ; %bb.0:1472; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91473; SI-NEXT: s_waitcnt lgkmcnt(0)1474; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01475; SI-NEXT: s_mov_b32 s3, 0xf0001476; SI-NEXT: s_mov_b32 s2, -11477; SI-NEXT: s_waitcnt lgkmcnt(0)1478; SI-NEXT: s_and_b32 s6, s4, 0xffffff1479; SI-NEXT: s_and_b32 s7, s5, 0xffffff1480; SI-NEXT: v_cvt_f32_u32_e32 v0, s61481; SI-NEXT: v_cvt_f32_u32_e32 v1, s71482; SI-NEXT: v_rcp_iflag_f32_e32 v2, v11483; SI-NEXT: v_mul_f32_e32 v2, v0, v21484; SI-NEXT: v_trunc_f32_e32 v2, v21485; SI-NEXT: v_fma_f32 v0, -v2, v1, v01486; SI-NEXT: v_cvt_u32_f32_e32 v2, v21487; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v11488; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc1489; SI-NEXT: v_mul_lo_u32 v0, v0, s51490; SI-NEXT: v_sub_i32_e32 v0, vcc, s4, v01491; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v01492; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01493; SI-NEXT: s_endpgm1494;1495; VI-LABEL: urem24_i32:1496; VI: ; %bb.0:1497; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241498; VI-NEXT: s_waitcnt lgkmcnt(0)1499; VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01500; VI-NEXT: s_mov_b32 s3, 0xf0001501; VI-NEXT: s_waitcnt lgkmcnt(0)1502; VI-NEXT: s_and_b32 s2, s5, 0xffffff1503; VI-NEXT: v_cvt_f32_u32_e32 v0, s21504; VI-NEXT: s_and_b32 s2, s4, 0xffffff1505; VI-NEXT: v_cvt_f32_u32_e32 v1, s21506; VI-NEXT: s_mov_b32 s2, -11507; VI-NEXT: v_rcp_iflag_f32_e32 v2, v01508; VI-NEXT: v_mul_f32_e32 v2, v1, v21509; VI-NEXT: v_trunc_f32_e32 v2, v21510; VI-NEXT: v_cvt_u32_f32_e32 v3, v21511; VI-NEXT: v_mad_f32 v1, -v2, v0, v11512; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v01513; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc1514; VI-NEXT: v_mul_lo_u32 v0, v0, s51515; VI-NEXT: v_sub_u32_e32 v0, vcc, s4, v01516; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v01517; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01518; VI-NEXT: s_endpgm1519;1520; EG-LABEL: urem24_i32:1521; EG: ; %bb.0:1522; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1523; EG-NEXT: TEX 0 @61524; EG-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[]1525; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11526; EG-NEXT: CF_END1527; EG-NEXT: PAD1528; EG-NEXT: Fetch clause starting at 6:1529; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11530; EG-NEXT: ALU clause starting at 8:1531; EG-NEXT: MOV * T0.X, KC0[2].Z,1532; EG-NEXT: ALU clause starting at 9:1533; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,1534; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1535; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,1536; EG-NEXT: RECIP_UINT * T0.Y, PV.W,1537; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,1538; EG-NEXT: MULHI * T0.Z, T0.Y, PS,1539; EG-NEXT: ADD_INT T1.W, T0.Y, PS,1540; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,1541; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1542; EG-NEXT: MULHI * T0.X, PS, PV.W,1543; EG-NEXT: MULLO_INT * T0.X, PS, T0.W,1544; EG-NEXT: SUB_INT * T1.W, T2.W, PS,1545; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1546; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,1547; EG-NEXT: CNDE_INT * T1.W, PV.W, T1.W, PS,1548; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1549; EG-NEXT: SUB_INT * T0.W, PV.W, T0.W,1550; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS,1551; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1552; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1553 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11554 %num = load i32, ptr addrspace(1) %in, align 41555 %den = load i32, ptr addrspace(1) %den_ptr, align 41556 %num.i24.0 = shl i32 %num, 81557 %den.i24.0 = shl i32 %den, 81558 %num.i24 = lshr i32 %num.i24.0, 81559 %den.i24 = lshr i32 %den.i24.0, 81560 %result = urem i32 %num.i24, %den.i241561 store i32 %result, ptr addrspace(1) %out, align 41562 ret void1563}1564 1565; RCP_IFLAG is for URECIP in the full 32b alg1566define amdgpu_kernel void @urem25_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {1567; SI-LABEL: urem25_i32:1568; SI: ; %bb.0:1569; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91570; SI-NEXT: s_waitcnt lgkmcnt(0)1571; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01572; SI-NEXT: s_mov_b32 s3, 0xf0001573; SI-NEXT: s_waitcnt lgkmcnt(0)1574; SI-NEXT: s_and_b32 s2, s4, 0x1ffffff1575; SI-NEXT: s_and_b32 s4, s5, 0x1ffffff1576; SI-NEXT: v_cvt_f32_u32_e32 v0, s41577; SI-NEXT: s_sub_i32 s5, 0, s41578; SI-NEXT: v_rcp_iflag_f32_e32 v0, v01579; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01580; SI-NEXT: v_cvt_u32_f32_e32 v0, v01581; SI-NEXT: v_mul_lo_u32 v1, s5, v01582; SI-NEXT: v_mul_hi_u32 v1, v0, v11583; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v11584; SI-NEXT: v_mul_hi_u32 v0, s2, v01585; SI-NEXT: v_readfirstlane_b32 s5, v01586; SI-NEXT: s_mul_i32 s5, s5, s41587; SI-NEXT: s_sub_i32 s2, s2, s51588; SI-NEXT: s_sub_i32 s5, s2, s41589; SI-NEXT: s_cmp_ge_u32 s2, s41590; SI-NEXT: s_cselect_b32 s2, s5, s21591; SI-NEXT: s_sub_i32 s5, s2, s41592; SI-NEXT: s_cmp_ge_u32 s2, s41593; SI-NEXT: s_cselect_b32 s4, s5, s21594; SI-NEXT: s_mov_b32 s2, -11595; SI-NEXT: v_mov_b32_e32 v0, s41596; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01597; SI-NEXT: s_endpgm1598;1599; VI-LABEL: urem25_i32:1600; VI: ; %bb.0:1601; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241602; VI-NEXT: s_waitcnt lgkmcnt(0)1603; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01604; VI-NEXT: s_waitcnt lgkmcnt(0)1605; VI-NEXT: s_and_b32 s4, s3, 0x1ffffff1606; VI-NEXT: v_cvt_f32_u32_e32 v0, s41607; VI-NEXT: s_sub_i32 s3, 0, s41608; VI-NEXT: s_and_b32 s5, s2, 0x1ffffff1609; VI-NEXT: s_mov_b32 s2, -11610; VI-NEXT: v_rcp_iflag_f32_e32 v0, v01611; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01612; VI-NEXT: v_cvt_u32_f32_e32 v0, v01613; VI-NEXT: v_mul_lo_u32 v1, s3, v01614; VI-NEXT: s_mov_b32 s3, 0xf0001615; VI-NEXT: v_mul_hi_u32 v1, v0, v11616; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v11617; VI-NEXT: v_mul_hi_u32 v0, s5, v01618; VI-NEXT: v_readfirstlane_b32 s6, v01619; VI-NEXT: s_mul_i32 s6, s6, s41620; VI-NEXT: s_sub_i32 s5, s5, s61621; VI-NEXT: s_sub_i32 s6, s5, s41622; VI-NEXT: s_cmp_ge_u32 s5, s41623; VI-NEXT: s_cselect_b32 s5, s6, s51624; VI-NEXT: s_sub_i32 s6, s5, s41625; VI-NEXT: s_cmp_ge_u32 s5, s41626; VI-NEXT: s_cselect_b32 s4, s6, s51627; VI-NEXT: v_mov_b32_e32 v0, s41628; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01629; VI-NEXT: s_endpgm1630;1631; EG-LABEL: urem25_i32:1632; EG: ; %bb.0:1633; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1634; EG-NEXT: TEX 0 @61635; EG-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[]1636; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11637; EG-NEXT: CF_END1638; EG-NEXT: PAD1639; EG-NEXT: Fetch clause starting at 6:1640; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11641; EG-NEXT: ALU clause starting at 8:1642; EG-NEXT: MOV * T0.X, KC0[2].Z,1643; EG-NEXT: ALU clause starting at 9:1644; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,1645; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)1646; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,1647; EG-NEXT: RECIP_UINT * T0.Y, PV.W,1648; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,1649; EG-NEXT: MULHI * T0.Z, T0.Y, PS,1650; EG-NEXT: ADD_INT T1.W, T0.Y, PS,1651; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,1652; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)1653; EG-NEXT: MULHI * T0.X, PS, PV.W,1654; EG-NEXT: MULLO_INT * T0.X, PS, T0.W,1655; EG-NEXT: SUB_INT * T1.W, T2.W, PS,1656; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1657; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,1658; EG-NEXT: CNDE_INT * T1.W, PV.W, T1.W, PS,1659; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1660; EG-NEXT: SUB_INT * T0.W, PV.W, T0.W,1661; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS,1662; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1663; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1664 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11665 %num = load i32, ptr addrspace(1) %in, align 41666 %den = load i32, ptr addrspace(1) %den_ptr, align 41667 %num.i24.0 = shl i32 %num, 71668 %den.i24.0 = shl i32 %den, 71669 %num.i24 = lshr i32 %num.i24.0, 71670 %den.i24 = lshr i32 %den.i24.0, 71671 %result = urem i32 %num.i24, %den.i241672 store i32 %result, ptr addrspace(1) %out, align 41673 ret void1674}1675 1676; RCP_IFLAG is for URECIP in the full 32b alg1677define amdgpu_kernel void @test_no_urem24_i32_1(ptr addrspace(1) %out, ptr addrspace(1) %in) {1678; SI-LABEL: test_no_urem24_i32_1:1679; SI: ; %bb.0:1680; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91681; SI-NEXT: s_waitcnt lgkmcnt(0)1682; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01683; SI-NEXT: s_mov_b32 s3, 0xf0001684; SI-NEXT: s_waitcnt lgkmcnt(0)1685; SI-NEXT: s_and_b32 s2, s4, 0xffffff1686; SI-NEXT: s_and_b32 s4, s5, 0x1ffffff1687; SI-NEXT: v_cvt_f32_u32_e32 v0, s41688; SI-NEXT: s_sub_i32 s5, 0, s41689; SI-NEXT: v_rcp_iflag_f32_e32 v0, v01690; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01691; SI-NEXT: v_cvt_u32_f32_e32 v0, v01692; SI-NEXT: v_mul_lo_u32 v1, s5, v01693; SI-NEXT: v_mul_hi_u32 v1, v0, v11694; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v11695; SI-NEXT: v_mul_hi_u32 v0, s2, v01696; SI-NEXT: v_readfirstlane_b32 s5, v01697; SI-NEXT: s_mul_i32 s5, s5, s41698; SI-NEXT: s_sub_i32 s2, s2, s51699; SI-NEXT: s_sub_i32 s5, s2, s41700; SI-NEXT: s_cmp_ge_u32 s2, s41701; SI-NEXT: s_cselect_b32 s2, s5, s21702; SI-NEXT: s_sub_i32 s5, s2, s41703; SI-NEXT: s_cmp_ge_u32 s2, s41704; SI-NEXT: s_cselect_b32 s4, s5, s21705; SI-NEXT: s_mov_b32 s2, -11706; SI-NEXT: v_mov_b32_e32 v0, s41707; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01708; SI-NEXT: s_endpgm1709;1710; VI-LABEL: test_no_urem24_i32_1:1711; VI: ; %bb.0:1712; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241713; VI-NEXT: s_waitcnt lgkmcnt(0)1714; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01715; VI-NEXT: s_waitcnt lgkmcnt(0)1716; VI-NEXT: s_and_b32 s4, s3, 0x1ffffff1717; VI-NEXT: v_cvt_f32_u32_e32 v0, s41718; VI-NEXT: s_sub_i32 s3, 0, s41719; VI-NEXT: s_and_b32 s5, s2, 0xffffff1720; VI-NEXT: s_mov_b32 s2, -11721; VI-NEXT: v_rcp_iflag_f32_e32 v0, v01722; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01723; VI-NEXT: v_cvt_u32_f32_e32 v0, v01724; VI-NEXT: v_mul_lo_u32 v1, s3, v01725; VI-NEXT: s_mov_b32 s3, 0xf0001726; VI-NEXT: v_mul_hi_u32 v1, v0, v11727; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v11728; VI-NEXT: v_mul_hi_u32 v0, s5, v01729; VI-NEXT: v_readfirstlane_b32 s6, v01730; VI-NEXT: s_mul_i32 s6, s6, s41731; VI-NEXT: s_sub_i32 s5, s5, s61732; VI-NEXT: s_sub_i32 s6, s5, s41733; VI-NEXT: s_cmp_ge_u32 s5, s41734; VI-NEXT: s_cselect_b32 s5, s6, s51735; VI-NEXT: s_sub_i32 s6, s5, s41736; VI-NEXT: s_cmp_ge_u32 s5, s41737; VI-NEXT: s_cselect_b32 s4, s6, s51738; VI-NEXT: v_mov_b32_e32 v0, s41739; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01740; VI-NEXT: s_endpgm1741;1742; EG-LABEL: test_no_urem24_i32_1:1743; EG: ; %bb.0:1744; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1745; EG-NEXT: TEX 0 @61746; EG-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[]1747; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11748; EG-NEXT: CF_END1749; EG-NEXT: PAD1750; EG-NEXT: Fetch clause starting at 6:1751; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11752; EG-NEXT: ALU clause starting at 8:1753; EG-NEXT: MOV * T0.X, KC0[2].Z,1754; EG-NEXT: ALU clause starting at 9:1755; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,1756; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)1757; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,1758; EG-NEXT: RECIP_UINT * T0.Y, PV.W,1759; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,1760; EG-NEXT: MULHI * T0.Z, T0.Y, PS,1761; EG-NEXT: ADD_INT T1.W, T0.Y, PS,1762; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,1763; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1764; EG-NEXT: MULHI * T0.X, PS, PV.W,1765; EG-NEXT: MULLO_INT * T0.X, PS, T0.W,1766; EG-NEXT: SUB_INT * T1.W, T2.W, PS,1767; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1768; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,1769; EG-NEXT: CNDE_INT * T1.W, PV.W, T1.W, PS,1770; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1771; EG-NEXT: SUB_INT * T0.W, PV.W, T0.W,1772; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS,1773; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1774; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1775 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11776 %num = load i32, ptr addrspace(1) %in, align 41777 %den = load i32, ptr addrspace(1) %den_ptr, align 41778 %num.i24.0 = shl i32 %num, 81779 %den.i24.0 = shl i32 %den, 71780 %num.i24 = lshr i32 %num.i24.0, 81781 %den.i24 = lshr i32 %den.i24.0, 71782 %result = urem i32 %num.i24, %den.i241783 store i32 %result, ptr addrspace(1) %out, align 41784 ret void1785}1786 1787; RCP_IFLAG is for URECIP in the full 32b alg1788define amdgpu_kernel void @test_no_urem24_i32_2(ptr addrspace(1) %out, ptr addrspace(1) %in) {1789; SI-LABEL: test_no_urem24_i32_2:1790; SI: ; %bb.0:1791; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91792; SI-NEXT: s_waitcnt lgkmcnt(0)1793; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01794; SI-NEXT: s_mov_b32 s3, 0xf0001795; SI-NEXT: s_waitcnt lgkmcnt(0)1796; SI-NEXT: s_and_b32 s2, s4, 0x1ffffff1797; SI-NEXT: s_and_b32 s4, s5, 0xffffff1798; SI-NEXT: v_cvt_f32_u32_e32 v0, s41799; SI-NEXT: s_sub_i32 s5, 0, s41800; SI-NEXT: v_rcp_iflag_f32_e32 v0, v01801; SI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01802; SI-NEXT: v_cvt_u32_f32_e32 v0, v01803; SI-NEXT: v_mul_lo_u32 v1, s5, v01804; SI-NEXT: v_mul_hi_u32 v1, v0, v11805; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v11806; SI-NEXT: v_mul_hi_u32 v0, s2, v01807; SI-NEXT: v_readfirstlane_b32 s5, v01808; SI-NEXT: s_mul_i32 s5, s5, s41809; SI-NEXT: s_sub_i32 s2, s2, s51810; SI-NEXT: s_sub_i32 s5, s2, s41811; SI-NEXT: s_cmp_ge_u32 s2, s41812; SI-NEXT: s_cselect_b32 s2, s5, s21813; SI-NEXT: s_sub_i32 s5, s2, s41814; SI-NEXT: s_cmp_ge_u32 s2, s41815; SI-NEXT: s_cselect_b32 s4, s5, s21816; SI-NEXT: s_mov_b32 s2, -11817; SI-NEXT: v_mov_b32_e32 v0, s41818; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01819; SI-NEXT: s_endpgm1820;1821; VI-LABEL: test_no_urem24_i32_2:1822; VI: ; %bb.0:1823; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241824; VI-NEXT: s_waitcnt lgkmcnt(0)1825; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01826; VI-NEXT: s_waitcnt lgkmcnt(0)1827; VI-NEXT: s_and_b32 s4, s3, 0xffffff1828; VI-NEXT: v_cvt_f32_u32_e32 v0, s41829; VI-NEXT: s_sub_i32 s3, 0, s41830; VI-NEXT: s_and_b32 s5, s2, 0x1ffffff1831; VI-NEXT: s_mov_b32 s2, -11832; VI-NEXT: v_rcp_iflag_f32_e32 v0, v01833; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v01834; VI-NEXT: v_cvt_u32_f32_e32 v0, v01835; VI-NEXT: v_mul_lo_u32 v1, s3, v01836; VI-NEXT: s_mov_b32 s3, 0xf0001837; VI-NEXT: v_mul_hi_u32 v1, v0, v11838; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v11839; VI-NEXT: v_mul_hi_u32 v0, s5, v01840; VI-NEXT: v_readfirstlane_b32 s6, v01841; VI-NEXT: s_mul_i32 s6, s6, s41842; VI-NEXT: s_sub_i32 s5, s5, s61843; VI-NEXT: s_sub_i32 s6, s5, s41844; VI-NEXT: s_cmp_ge_u32 s5, s41845; VI-NEXT: s_cselect_b32 s5, s6, s51846; VI-NEXT: s_sub_i32 s6, s5, s41847; VI-NEXT: s_cmp_ge_u32 s5, s41848; VI-NEXT: s_cselect_b32 s4, s6, s51849; VI-NEXT: v_mov_b32_e32 v0, s41850; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01851; VI-NEXT: s_endpgm1852;1853; EG-LABEL: test_no_urem24_i32_2:1854; EG: ; %bb.0:1855; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1856; EG-NEXT: TEX 0 @61857; EG-NEXT: ALU 19, @9, KC0[CB0:0-32], KC1[]1858; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11859; EG-NEXT: CF_END1860; EG-NEXT: PAD1861; EG-NEXT: Fetch clause starting at 6:1862; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11863; EG-NEXT: ALU clause starting at 8:1864; EG-NEXT: MOV * T0.X, KC0[2].Z,1865; EG-NEXT: ALU clause starting at 9:1866; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,1867; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1868; EG-NEXT: SUB_INT T1.W, 0.0, PV.W,1869; EG-NEXT: RECIP_UINT * T0.Y, PV.W,1870; EG-NEXT: MULLO_INT * T0.Z, PV.W, PS,1871; EG-NEXT: MULHI * T0.Z, T0.Y, PS,1872; EG-NEXT: ADD_INT T1.W, T0.Y, PS,1873; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,1874; EG-NEXT: 33554431(9.403954e-38), 0(0.000000e+00)1875; EG-NEXT: MULHI * T0.X, PS, PV.W,1876; EG-NEXT: MULLO_INT * T0.X, PS, T0.W,1877; EG-NEXT: SUB_INT * T1.W, T2.W, PS,1878; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1879; EG-NEXT: SUB_INT * T3.W, PV.W, T0.W,1880; EG-NEXT: CNDE_INT * T1.W, PV.W, T1.W, PS,1881; EG-NEXT: SETGE_UINT T2.W, PV.W, T0.W,1882; EG-NEXT: SUB_INT * T0.W, PV.W, T0.W,1883; EG-NEXT: CNDE_INT T0.X, PV.W, T1.W, PS,1884; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1885; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1886 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11887 %num = load i32, ptr addrspace(1) %in, align 41888 %den = load i32, ptr addrspace(1) %den_ptr, align 41889 %num.i24.0 = shl i32 %num, 71890 %den.i24.0 = shl i32 %den, 81891 %num.i24 = lshr i32 %num.i24.0, 71892 %den.i24 = lshr i32 %den.i24.0, 81893 %result = urem i32 %num.i24, %den.i241894 store i32 %result, ptr addrspace(1) %out, align 41895 ret void1896}1897 1898define amdgpu_kernel void @test_udiv24_u16_u23_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {1899; SI-LABEL: test_udiv24_u16_u23_i32:1900; SI: ; %bb.0:1901; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91902; SI-NEXT: s_waitcnt lgkmcnt(0)1903; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01904; SI-NEXT: s_mov_b32 s3, 0xf0001905; SI-NEXT: s_mov_b32 s2, -11906; SI-NEXT: s_waitcnt lgkmcnt(0)1907; SI-NEXT: s_and_b32 s4, s4, 0xffff1908; SI-NEXT: s_and_b32 s5, s5, 0x7fffff1909; SI-NEXT: v_cvt_f32_u32_e32 v0, s41910; SI-NEXT: v_cvt_f32_u32_e32 v1, s51911; SI-NEXT: v_rcp_iflag_f32_e32 v2, v11912; SI-NEXT: v_mul_f32_e32 v2, v0, v21913; SI-NEXT: v_trunc_f32_e32 v2, v21914; SI-NEXT: v_fma_f32 v0, -v2, v1, v01915; SI-NEXT: v_cvt_u32_f32_e32 v2, v21916; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v11917; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc1918; SI-NEXT: v_and_b32_e32 v0, 0x7fffff, v01919; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01920; SI-NEXT: s_endpgm1921;1922; VI-LABEL: test_udiv24_u16_u23_i32:1923; VI: ; %bb.0:1924; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241925; VI-NEXT: s_waitcnt lgkmcnt(0)1926; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x01927; VI-NEXT: s_waitcnt lgkmcnt(0)1928; VI-NEXT: s_and_b32 s3, s3, 0x7fffff1929; VI-NEXT: v_cvt_f32_u32_e32 v0, s31930; VI-NEXT: s_and_b32 s2, s2, 0xffff1931; VI-NEXT: v_cvt_f32_u32_e32 v1, s21932; VI-NEXT: s_mov_b32 s3, 0xf0001933; VI-NEXT: v_rcp_iflag_f32_e32 v2, v01934; VI-NEXT: s_mov_b32 s2, -11935; VI-NEXT: v_mul_f32_e32 v2, v1, v21936; VI-NEXT: v_trunc_f32_e32 v2, v21937; VI-NEXT: v_cvt_u32_f32_e32 v3, v21938; VI-NEXT: v_mad_f32 v1, -v2, v0, v11939; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v01940; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc1941; VI-NEXT: v_and_b32_e32 v0, 0x7fffff, v01942; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01943; VI-NEXT: s_endpgm1944;1945; EG-LABEL: test_udiv24_u16_u23_i32:1946; EG: ; %bb.0:1947; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]1948; EG-NEXT: TEX 0 @61949; EG-NEXT: ALU 18, @9, KC0[CB0:0-32], KC1[]1950; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11951; EG-NEXT: CF_END1952; EG-NEXT: PAD1953; EG-NEXT: Fetch clause starting at 6:1954; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #11955; EG-NEXT: ALU clause starting at 8:1956; EG-NEXT: MOV * T0.X, KC0[2].Z,1957; EG-NEXT: ALU clause starting at 9:1958; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,1959; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)1960; EG-NEXT: UINT_TO_FLT * T0.Y, PV.W,1961; EG-NEXT: AND_INT T0.W, T0.X, literal.x,1962; EG-NEXT: RECIP_IEEE * T0.X, PS,1963; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1964; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,1965; EG-NEXT: MUL_IEEE * T0.W, PS, T0.X,1966; EG-NEXT: TRUNC * T0.W, PV.W,1967; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.Z,1968; EG-NEXT: TRUNC * T0.W, PV.W,1969; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,1970; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,1971; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,1972; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)1973; EG-NEXT: ADD_INT * T0.W, PS, PV.W,1974; EG-NEXT: AND_INT T0.X, PV.W, literal.x,1975; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1976; EG-NEXT: 8388607(1.175494e-38), 2(2.802597e-45)1977 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 11978 %num = load i32, ptr addrspace(1) %in, align 41979 %den = load i32, ptr addrspace(1) %den_ptr, align 41980 %num.i16.0 = shl i32 %num, 161981 %den.i23.0 = shl i32 %den, 91982 %num.i16 = lshr i32 %num.i16.0, 161983 %den.i23 = lshr i32 %den.i23.0, 91984 %result = udiv i32 %num.i16, %den.i231985 store i32 %result, ptr addrspace(1) %out, align 41986 ret void1987}1988 1989define amdgpu_kernel void @test_udiv24_u23_u16_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {1990; SI-LABEL: test_udiv24_u23_u16_i32:1991; SI: ; %bb.0:1992; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91993; SI-NEXT: s_waitcnt lgkmcnt(0)1994; SI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x01995; SI-NEXT: s_mov_b32 s3, 0xf0001996; SI-NEXT: s_mov_b32 s2, -11997; SI-NEXT: s_waitcnt lgkmcnt(0)1998; SI-NEXT: s_and_b32 s4, s4, 0x7fffff1999; SI-NEXT: s_and_b32 s5, s5, 0xffff2000; SI-NEXT: v_cvt_f32_u32_e32 v0, s42001; SI-NEXT: v_cvt_f32_u32_e32 v1, s52002; SI-NEXT: v_rcp_iflag_f32_e32 v2, v12003; SI-NEXT: v_mul_f32_e32 v2, v0, v22004; SI-NEXT: v_trunc_f32_e32 v2, v22005; SI-NEXT: v_fma_f32 v0, -v2, v1, v02006; SI-NEXT: v_cvt_u32_f32_e32 v2, v22007; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v12008; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc2009; SI-NEXT: v_and_b32_e32 v0, 0x7fffff, v02010; SI-NEXT: buffer_store_dword v0, off, s[0:3], 02011; SI-NEXT: s_endpgm2012;2013; VI-LABEL: test_udiv24_u23_u16_i32:2014; VI: ; %bb.0:2015; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x242016; VI-NEXT: s_waitcnt lgkmcnt(0)2017; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x02018; VI-NEXT: s_waitcnt lgkmcnt(0)2019; VI-NEXT: s_and_b32 s3, s3, 0xffff2020; VI-NEXT: v_cvt_f32_u32_e32 v0, s32021; VI-NEXT: s_and_b32 s2, s2, 0x7fffff2022; VI-NEXT: v_cvt_f32_u32_e32 v1, s22023; VI-NEXT: s_mov_b32 s3, 0xf0002024; VI-NEXT: v_rcp_iflag_f32_e32 v2, v02025; VI-NEXT: s_mov_b32 s2, -12026; VI-NEXT: v_mul_f32_e32 v2, v1, v22027; VI-NEXT: v_trunc_f32_e32 v2, v22028; VI-NEXT: v_cvt_u32_f32_e32 v3, v22029; VI-NEXT: v_mad_f32 v1, -v2, v0, v12030; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v02031; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc2032; VI-NEXT: v_and_b32_e32 v0, 0x7fffff, v02033; VI-NEXT: buffer_store_dword v0, off, s[0:3], 02034; VI-NEXT: s_endpgm2035;2036; EG-LABEL: test_udiv24_u23_u16_i32:2037; EG: ; %bb.0:2038; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]2039; EG-NEXT: TEX 0 @62040; EG-NEXT: ALU 18, @9, KC0[CB0:0-32], KC1[]2041; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 12042; EG-NEXT: CF_END2043; EG-NEXT: PAD2044; EG-NEXT: Fetch clause starting at 6:2045; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #12046; EG-NEXT: ALU clause starting at 8:2047; EG-NEXT: MOV * T0.X, KC0[2].Z,2048; EG-NEXT: ALU clause starting at 9:2049; EG-NEXT: AND_INT * T0.W, T0.Y, literal.x,2050; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)2051; EG-NEXT: UINT_TO_FLT * T0.Y, PV.W,2052; EG-NEXT: AND_INT T0.W, T0.X, literal.x,2053; EG-NEXT: RECIP_IEEE * T0.X, PS,2054; EG-NEXT: 8388607(1.175494e-38), 0(0.000000e+00)2055; EG-NEXT: UINT_TO_FLT * T0.Z, PV.W,2056; EG-NEXT: MUL_IEEE * T0.W, PS, T0.X,2057; EG-NEXT: TRUNC * T0.W, PV.W,2058; EG-NEXT: MULADD_IEEE T1.W, -PV.W, T0.Y, T0.Z,2059; EG-NEXT: TRUNC * T0.W, PV.W,2060; EG-NEXT: SETGE * T1.W, |PV.W|, T0.Y,2061; EG-NEXT: CNDE T1.W, PV.W, 0.0, literal.x,2062; EG-NEXT: FLT_TO_UINT * T0.X, T0.W,2063; EG-NEXT: 1(1.401298e-45), 0(0.000000e+00)2064; EG-NEXT: ADD_INT * T0.W, PS, PV.W,2065; EG-NEXT: AND_INT T0.X, PV.W, literal.x,2066; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,2067; EG-NEXT: 8388607(1.175494e-38), 2(2.802597e-45)2068 %den_ptr = getelementptr i32, ptr addrspace(1) %in, i32 12069 %num = load i32, ptr addrspace(1) %in, align 42070 %den = load i32, ptr addrspace(1) %den_ptr, align 42071 %num.i23.0 = shl i32 %num, 92072 %den.i16.0 = shl i32 %den, 162073 %num.i23 = lshr i32 %num.i23.0, 92074 %den.i16 = lshr i32 %den.i16.0, 162075 %result = udiv i32 %num.i23, %den.i162076 store i32 %result, ptr addrspace(1) %out, align 42077 ret void2078}2079 2080attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }2081attributes #1 = { "denormal-fp-math-f32"="ieee,preserve-sign" }2082attributes #2 = { "denormal-fp-math-f32"="preserve-sign,ieee" }2083