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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=GFX942 %s5 6declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone7 8define amdgpu_kernel void @v_uint_to_fp_i64_to_f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {9; SI-LABEL: v_uint_to_fp_i64_to_f64:10; SI: ; %bb.0:11; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x012; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v013; SI-NEXT: s_add_i32 s12, s12, s1714; SI-NEXT: s_mov_b32 flat_scratch_lo, s1315; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 816; SI-NEXT: s_waitcnt lgkmcnt(0)17; SI-NEXT: v_mov_b32_e32 v1, s318; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v019; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc20; SI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]21; SI-NEXT: s_waitcnt vmcnt(0)22; SI-NEXT: v_cvt_f64_u32_e32 v[1:2], v123; SI-NEXT: v_cvt_f64_u32_e32 v[3:4], v024; SI-NEXT: v_ldexp_f64 v[0:1], v[1:2], 3225; SI-NEXT: v_mov_b32_e32 v2, s026; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[3:4]27; SI-NEXT: v_mov_b32_e32 v3, s128; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]29; SI-NEXT: s_endpgm30;31; VI-LABEL: v_uint_to_fp_i64_to_f64:32; VI: ; %bb.0:33; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x034; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v035; VI-NEXT: s_add_i32 s12, s12, s1736; VI-NEXT: s_mov_b32 flat_scratch_lo, s1337; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 838; VI-NEXT: s_waitcnt lgkmcnt(0)39; VI-NEXT: v_mov_b32_e32 v1, s340; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v041; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc42; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]43; VI-NEXT: s_waitcnt vmcnt(0)44; VI-NEXT: v_cvt_f64_u32_e32 v[1:2], v145; VI-NEXT: v_cvt_f64_u32_e32 v[3:4], v046; VI-NEXT: v_ldexp_f64 v[1:2], v[1:2], 3247; VI-NEXT: v_add_f64 v[0:1], v[1:2], v[3:4]48; VI-NEXT: v_mov_b32_e32 v2, s049; VI-NEXT: v_mov_b32_e32 v3, s150; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]51; VI-NEXT: s_endpgm52;53; GFX942-LABEL: v_uint_to_fp_i64_to_f64:54; GFX942: ; %bb.0:55; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x056; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v057; GFX942-NEXT: v_lshlrev_b32_e32 v0, 3, v058; GFX942-NEXT: v_mov_b32_e32 v4, 059; GFX942-NEXT: s_waitcnt lgkmcnt(0)60; GFX942-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3]61; GFX942-NEXT: s_waitcnt vmcnt(0)62; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], v163; GFX942-NEXT: v_ldexp_f64 v[2:3], v[2:3], 3264; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], v065; GFX942-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]66; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]67; GFX942-NEXT: s_endpgm68 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone69 %gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid70 %val = load i64, ptr addrspace(1) %gep, align 871 %result = uitofp i64 %val to double72 store double %result, ptr addrspace(1) %out73 ret void74}75 76define amdgpu_kernel void @s_uint_to_fp_i64_to_f64(ptr addrspace(1) %out, i64 %in) {77; SI-LABEL: s_uint_to_fp_i64_to_f64:78; SI: ; %bb.0:79; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x080; SI-NEXT: s_add_i32 s12, s12, s1781; SI-NEXT: s_mov_b32 flat_scratch_lo, s1382; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 883; SI-NEXT: s_waitcnt lgkmcnt(0)84; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s385; SI-NEXT: v_cvt_f64_u32_e32 v[2:3], s286; SI-NEXT: v_mov_b32_e32 v4, s087; SI-NEXT: v_mov_b32_e32 v5, s188; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 3289; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]90; SI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]91; SI-NEXT: s_endpgm92;93; VI-LABEL: s_uint_to_fp_i64_to_f64:94; VI: ; %bb.0:95; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x096; VI-NEXT: s_add_i32 s12, s12, s1797; VI-NEXT: s_mov_b32 flat_scratch_lo, s1398; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 899; VI-NEXT: s_waitcnt lgkmcnt(0)100; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s3101; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s2102; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32103; VI-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]104; VI-NEXT: v_mov_b32_e32 v2, s0105; VI-NEXT: v_mov_b32_e32 v3, s1106; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]107; VI-NEXT: s_endpgm108;109; GFX942-LABEL: s_uint_to_fp_i64_to_f64:110; GFX942: ; %bb.0:111; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0112; GFX942-NEXT: v_mov_b32_e32 v4, 0113; GFX942-NEXT: s_waitcnt lgkmcnt(0)114; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s3115; GFX942-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32116; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s2117; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]118; GFX942-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]119; GFX942-NEXT: s_endpgm120 %cast = uitofp i64 %in to double121 store double %cast, ptr addrspace(1) %out, align 8122 ret void123}124 125define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f64(ptr addrspace(1) %out, <2 x i64> %in) {126; SI-LABEL: s_uint_to_fp_v2i64_to_v2f64:127; SI: ; %bb.0:128; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4129; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0130; SI-NEXT: s_add_i32 s12, s12, s17131; SI-NEXT: s_mov_b32 flat_scratch_lo, s13132; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8133; SI-NEXT: s_waitcnt lgkmcnt(0)134; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s3135; SI-NEXT: v_cvt_f64_u32_e32 v[2:3], s1136; SI-NEXT: v_cvt_f64_u32_e32 v[4:5], s2137; SI-NEXT: v_cvt_f64_u32_e32 v[6:7], s0138; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32139; SI-NEXT: v_ldexp_f64 v[8:9], v[2:3], 32140; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[4:5]141; SI-NEXT: v_add_f64 v[0:1], v[8:9], v[6:7]142; SI-NEXT: v_mov_b32_e32 v4, s4143; SI-NEXT: v_mov_b32_e32 v5, s5144; SI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]145; SI-NEXT: s_endpgm146;147; VI-LABEL: s_uint_to_fp_v2i64_to_v2f64:148; VI: ; %bb.0:149; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10150; VI-NEXT: s_add_i32 s12, s12, s17151; VI-NEXT: s_mov_b32 flat_scratch_lo, s13152; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8153; VI-NEXT: s_waitcnt lgkmcnt(0)154; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s3155; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s1156; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], s0157; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0158; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32159; VI-NEXT: v_ldexp_f64 v[4:5], v[2:3], 32160; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s2161; VI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]162; VI-NEXT: v_add_f64 v[0:1], v[4:5], v[6:7]163; VI-NEXT: s_waitcnt lgkmcnt(0)164; VI-NEXT: v_mov_b32_e32 v5, s1165; VI-NEXT: v_mov_b32_e32 v4, s0166; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]167; VI-NEXT: s_endpgm168;169; GFX942-LABEL: s_uint_to_fp_v2i64_to_v2f64:170; GFX942: ; %bb.0:171; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10172; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0173; GFX942-NEXT: v_mov_b32_e32 v6, 0174; GFX942-NEXT: s_waitcnt lgkmcnt(0)175; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s3176; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s2177; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s1178; GFX942-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32179; GFX942-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]180; GFX942-NEXT: v_ldexp_f64 v[0:1], v[4:5], 32181; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s0182; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5]183; GFX942-NEXT: global_store_dwordx4 v6, v[0:3], s[6:7]184; GFX942-NEXT: s_endpgm185 %cast = uitofp <2 x i64> %in to <2 x double>186 store <2 x double> %cast, ptr addrspace(1) %out, align 16187 ret void188}189 190define amdgpu_kernel void @s_uint_to_fp_v4i64_to_v4f64(ptr addrspace(1) %out, <4 x i64> %in) {191; SI-LABEL: s_uint_to_fp_v4i64_to_v4f64:192; SI: ; %bb.0:193; SI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x8194; SI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0195; SI-NEXT: s_add_i32 s12, s12, s17196; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8197; SI-NEXT: s_mov_b32 flat_scratch_lo, s13198; SI-NEXT: s_waitcnt lgkmcnt(0)199; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s3200; SI-NEXT: v_cvt_f64_u32_e32 v[4:5], s1201; SI-NEXT: v_cvt_f64_u32_e32 v[2:3], s2202; SI-NEXT: v_cvt_f64_u32_e32 v[6:7], s0203; SI-NEXT: v_cvt_f64_u32_e32 v[8:9], s7204; SI-NEXT: v_cvt_f64_u32_e32 v[10:11], s5205; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32206; SI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 32207; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]208; SI-NEXT: v_add_f64 v[0:1], v[4:5], v[6:7]209; SI-NEXT: v_cvt_f64_u32_e32 v[4:5], s6210; SI-NEXT: v_cvt_f64_u32_e32 v[12:13], s4211; SI-NEXT: v_ldexp_f64 v[6:7], v[8:9], 32212; SI-NEXT: v_ldexp_f64 v[8:9], v[10:11], 32213; SI-NEXT: s_add_u32 s0, s8, 16214; SI-NEXT: s_addc_u32 s1, s9, 0215; SI-NEXT: v_add_f64 v[6:7], v[6:7], v[4:5]216; SI-NEXT: v_add_f64 v[4:5], v[8:9], v[12:13]217; SI-NEXT: v_mov_b32_e32 v9, s1218; SI-NEXT: v_mov_b32_e32 v8, s0219; SI-NEXT: flat_store_dwordx4 v[8:9], v[4:7]220; SI-NEXT: s_nop 0221; SI-NEXT: v_mov_b32_e32 v4, s8222; SI-NEXT: v_mov_b32_e32 v5, s9223; SI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]224; SI-NEXT: s_endpgm225;226; VI-LABEL: s_uint_to_fp_v4i64_to_v4f64:227; VI: ; %bb.0:228; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x20229; VI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0230; VI-NEXT: s_add_i32 s12, s12, s17231; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8232; VI-NEXT: s_mov_b32 flat_scratch_lo, s13233; VI-NEXT: s_waitcnt lgkmcnt(0)234; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s7235; VI-NEXT: v_cvt_f64_u32_e32 v[4:5], s5236; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s3237; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], s1238; VI-NEXT: v_ldexp_f64 v[8:9], v[2:3], 32239; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 32240; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32241; VI-NEXT: v_ldexp_f64 v[10:11], v[6:7], 32242; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], s6243; VI-NEXT: v_cvt_f64_u32_e32 v[12:13], s4244; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s2245; VI-NEXT: v_cvt_f64_u32_e32 v[14:15], s0246; VI-NEXT: v_add_f64 v[6:7], v[8:9], v[6:7]247; VI-NEXT: v_add_f64 v[4:5], v[4:5], v[12:13]248; VI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]249; VI-NEXT: v_add_f64 v[0:1], v[10:11], v[14:15]250; VI-NEXT: s_add_u32 s0, s8, 16251; VI-NEXT: s_addc_u32 s1, s9, 0252; VI-NEXT: v_mov_b32_e32 v11, s1253; VI-NEXT: v_mov_b32_e32 v8, s8254; VI-NEXT: v_mov_b32_e32 v10, s0255; VI-NEXT: v_mov_b32_e32 v9, s9256; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]257; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]258; VI-NEXT: s_endpgm259;260; GFX942-LABEL: s_uint_to_fp_v4i64_to_v4f64:261; GFX942: ; %bb.0:262; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20263; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0264; GFX942-NEXT: v_mov_b32_e32 v10, 0265; GFX942-NEXT: s_waitcnt lgkmcnt(0)266; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s11267; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s10268; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s9269; GFX942-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32270; GFX942-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]271; GFX942-NEXT: v_ldexp_f64 v[0:1], v[4:5], 32272; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s8273; GFX942-NEXT: v_add_f64 v[0:1], v[0:1], v[4:5]274; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s15275; GFX942-NEXT: v_ldexp_f64 v[4:5], v[4:5], 32276; GFX942-NEXT: v_cvt_f64_u32_e32 v[6:7], s14277; GFX942-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]278; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s13279; GFX942-NEXT: v_ldexp_f64 v[4:5], v[4:5], 32280; GFX942-NEXT: v_cvt_f64_u32_e32 v[8:9], s12281; GFX942-NEXT: v_add_f64 v[4:5], v[4:5], v[8:9]282; GFX942-NEXT: global_store_dwordx4 v10, v[4:7], s[0:1] offset:16283; GFX942-NEXT: global_store_dwordx4 v10, v[0:3], s[0:1]284; GFX942-NEXT: s_endpgm285 %cast = uitofp <4 x i64> %in to <4 x double>286 store <4 x double> %cast, ptr addrspace(1) %out, align 16287 ret void288}289 290define amdgpu_kernel void @s_uint_to_fp_i32_to_f64(ptr addrspace(1) %out, i32 %in) {291; SI-LABEL: s_uint_to_fp_i32_to_f64:292; SI: ; %bb.0:293; SI-NEXT: s_load_dword s2, s[8:9], 0x2294; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0295; SI-NEXT: s_add_i32 s12, s12, s17296; SI-NEXT: s_mov_b32 flat_scratch_lo, s13297; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8298; SI-NEXT: s_waitcnt lgkmcnt(0)299; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s2300; SI-NEXT: v_mov_b32_e32 v3, s1301; SI-NEXT: v_mov_b32_e32 v2, s0302; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]303; SI-NEXT: s_endpgm304;305; VI-LABEL: s_uint_to_fp_i32_to_f64:306; VI: ; %bb.0:307; VI-NEXT: s_load_dword s2, s[8:9], 0x8308; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0309; VI-NEXT: s_add_i32 s12, s12, s17310; VI-NEXT: s_mov_b32 flat_scratch_lo, s13311; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8312; VI-NEXT: s_waitcnt lgkmcnt(0)313; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s2314; VI-NEXT: v_mov_b32_e32 v3, s1315; VI-NEXT: v_mov_b32_e32 v2, s0316; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]317; VI-NEXT: s_endpgm318;319; GFX942-LABEL: s_uint_to_fp_i32_to_f64:320; GFX942: ; %bb.0:321; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8322; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0323; GFX942-NEXT: v_mov_b32_e32 v2, 0324; GFX942-NEXT: s_waitcnt lgkmcnt(0)325; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s2326; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]327; GFX942-NEXT: s_endpgm328 %cast = uitofp i32 %in to double329 store double %cast, ptr addrspace(1) %out, align 8330 ret void331}332 333define amdgpu_kernel void @s_uint_to_fp_v2i32_to_v2f64(ptr addrspace(1) %out, <2 x i32> %in) {334; GCN-LABEL: s_uint_to_fp_v2i32_to_v2f64:335; GCN: ; %bb.0:336; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0337; GCN-NEXT: s_add_i32 s12, s12, s17338; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13339; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8340; GCN-NEXT: s_waitcnt lgkmcnt(0)341; GCN-NEXT: v_cvt_f64_u32_e32 v[2:3], s3342; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], s2343; GCN-NEXT: v_mov_b32_e32 v5, s1344; GCN-NEXT: v_mov_b32_e32 v4, s0345; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]346; GCN-NEXT: s_endpgm347;348; GFX942-LABEL: s_uint_to_fp_v2i32_to_v2f64:349; GFX942: ; %bb.0:350; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0351; GFX942-NEXT: v_mov_b32_e32 v4, 0352; GFX942-NEXT: s_waitcnt lgkmcnt(0)353; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s3354; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s2355; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]356; GFX942-NEXT: s_endpgm357 %cast = uitofp <2 x i32> %in to <2 x double>358 store <2 x double> %cast, ptr addrspace(1) %out, align 16359 ret void360}361 362define amdgpu_kernel void @s_uint_to_fp_v4i32_to_v4f64(ptr addrspace(1) %out, <4 x i32> %in) {363; SI-LABEL: s_uint_to_fp_v4i32_to_v4f64:364; SI: ; %bb.0:365; SI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4366; SI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0367; SI-NEXT: s_add_i32 s12, s12, s17368; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8369; SI-NEXT: s_mov_b32 flat_scratch_lo, s13370; SI-NEXT: s_waitcnt lgkmcnt(0)371; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s0372; SI-NEXT: v_cvt_f64_u32_e32 v[6:7], s3373; SI-NEXT: v_cvt_f64_u32_e32 v[4:5], s2374; SI-NEXT: s_add_u32 s0, s4, 16375; SI-NEXT: v_cvt_f64_u32_e32 v[2:3], s1376; SI-NEXT: s_addc_u32 s1, s5, 0377; SI-NEXT: v_mov_b32_e32 v9, s1378; SI-NEXT: v_mov_b32_e32 v8, s0379; SI-NEXT: flat_store_dwordx4 v[8:9], v[4:7]380; SI-NEXT: s_nop 0381; SI-NEXT: v_mov_b32_e32 v4, s4382; SI-NEXT: v_mov_b32_e32 v5, s5383; SI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]384; SI-NEXT: s_endpgm385;386; VI-LABEL: s_uint_to_fp_v4i32_to_v4f64:387; VI: ; %bb.0:388; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10389; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0390; VI-NEXT: s_add_i32 s12, s12, s17391; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8392; VI-NEXT: s_mov_b32 flat_scratch_lo, s13393; VI-NEXT: s_waitcnt lgkmcnt(0)394; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s0395; VI-NEXT: v_cvt_f64_u32_e32 v[6:7], s3396; VI-NEXT: v_cvt_f64_u32_e32 v[4:5], s2397; VI-NEXT: s_add_u32 s0, s4, 16398; VI-NEXT: v_cvt_f64_u32_e32 v[2:3], s1399; VI-NEXT: s_addc_u32 s1, s5, 0400; VI-NEXT: v_mov_b32_e32 v9, s1401; VI-NEXT: v_mov_b32_e32 v8, s0402; VI-NEXT: flat_store_dwordx4 v[8:9], v[4:7]403; VI-NEXT: s_nop 0404; VI-NEXT: v_mov_b32_e32 v4, s4405; VI-NEXT: v_mov_b32_e32 v5, s5406; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]407; VI-NEXT: s_endpgm408;409; GFX942-LABEL: s_uint_to_fp_v4i32_to_v4f64:410; GFX942: ; %bb.0:411; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x10412; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0413; GFX942-NEXT: v_mov_b32_e32 v8, 0414; GFX942-NEXT: s_waitcnt lgkmcnt(0)415; GFX942-NEXT: v_cvt_f64_u32_e32 v[6:7], s3416; GFX942-NEXT: v_cvt_f64_u32_e32 v[4:5], s2417; GFX942-NEXT: v_cvt_f64_u32_e32 v[2:3], s1418; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s0419; GFX942-NEXT: global_store_dwordx4 v8, v[4:7], s[6:7] offset:16420; GFX942-NEXT: global_store_dwordx4 v8, v[0:3], s[6:7]421; GFX942-NEXT: s_endpgm422 %cast = uitofp <4 x i32> %in to <4 x double>423 store <4 x double> %cast, ptr addrspace(1) %out, align 16424 ret void425}426 427; We can't fold the SGPRs into v_cndmask_b32_e32, because it already428; uses an SGPR (implicit vcc).429define amdgpu_kernel void @uint_to_fp_i1_to_f64(ptr addrspace(1) %out, i32 %in) {430; SI-LABEL: uint_to_fp_i1_to_f64:431; SI: ; %bb.0:432; SI-NEXT: s_load_dword s2, s[8:9], 0x2433; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0434; SI-NEXT: s_add_i32 s12, s12, s17435; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8436; SI-NEXT: s_mov_b32 flat_scratch_lo, s13437; SI-NEXT: s_waitcnt lgkmcnt(0)438; SI-NEXT: s_cmp_eq_u32 s2, 0439; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0440; SI-NEXT: v_mov_b32_e32 v3, s1441; SI-NEXT: v_mov_b32_e32 v0, 0442; SI-NEXT: v_mov_b32_e32 v1, s2443; SI-NEXT: v_mov_b32_e32 v2, s0444; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]445; SI-NEXT: s_endpgm446;447; VI-LABEL: uint_to_fp_i1_to_f64:448; VI: ; %bb.0:449; VI-NEXT: s_load_dword s2, s[8:9], 0x8450; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0451; VI-NEXT: s_add_i32 s12, s12, s17452; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8453; VI-NEXT: s_mov_b32 flat_scratch_lo, s13454; VI-NEXT: s_waitcnt lgkmcnt(0)455; VI-NEXT: s_cmp_eq_u32 s2, 0456; VI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0457; VI-NEXT: v_mov_b32_e32 v3, s1458; VI-NEXT: v_mov_b32_e32 v0, 0459; VI-NEXT: v_mov_b32_e32 v1, s2460; VI-NEXT: v_mov_b32_e32 v2, s0461; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]462; VI-NEXT: s_endpgm463;464; GFX942-LABEL: uint_to_fp_i1_to_f64:465; GFX942: ; %bb.0:466; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8467; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0468; GFX942-NEXT: v_mov_b32_e32 v0, 0469; GFX942-NEXT: s_waitcnt lgkmcnt(0)470; GFX942-NEXT: s_cmp_eq_u32 s2, 0471; GFX942-NEXT: s_cselect_b32 s2, 0x3ff00000, 0472; GFX942-NEXT: v_mov_b32_e32 v1, s2473; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]474; GFX942-NEXT: s_endpgm475 %cmp = icmp eq i32 %in, 0476 %fp = uitofp i1 %cmp to double477 store double %fp, ptr addrspace(1) %out, align 4478 ret void479}480 481define amdgpu_kernel void @uint_to_fp_i1_to_f64_load(ptr addrspace(1) %out, i1 %in) {482; SI-LABEL: uint_to_fp_i1_to_f64_load:483; SI: ; %bb.0:484; SI-NEXT: s_load_dword s2, s[8:9], 0x2485; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0486; SI-NEXT: s_add_i32 s12, s12, s17487; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8488; SI-NEXT: s_mov_b32 flat_scratch_lo, s13489; SI-NEXT: s_waitcnt lgkmcnt(0)490; SI-NEXT: s_bitcmp1_b32 s2, 0491; SI-NEXT: s_cselect_b64 s[2:3], -1, 0492; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]493; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0494; SI-NEXT: v_mov_b32_e32 v3, s1495; SI-NEXT: v_mov_b32_e32 v2, s0496; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]497; SI-NEXT: s_endpgm498;499; VI-LABEL: uint_to_fp_i1_to_f64_load:500; VI: ; %bb.0:501; VI-NEXT: s_load_dword s2, s[8:9], 0x8502; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0503; VI-NEXT: s_add_i32 s12, s12, s17504; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8505; VI-NEXT: s_mov_b32 flat_scratch_lo, s13506; VI-NEXT: s_waitcnt lgkmcnt(0)507; VI-NEXT: s_bitcmp1_b32 s2, 0508; VI-NEXT: s_cselect_b64 s[2:3], -1, 0509; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]510; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0511; VI-NEXT: v_mov_b32_e32 v3, s1512; VI-NEXT: v_mov_b32_e32 v2, s0513; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]514; VI-NEXT: s_endpgm515;516; GFX942-LABEL: uint_to_fp_i1_to_f64_load:517; GFX942: ; %bb.0:518; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8519; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0520; GFX942-NEXT: v_mov_b32_e32 v2, 0521; GFX942-NEXT: s_waitcnt lgkmcnt(0)522; GFX942-NEXT: s_bitcmp1_b32 s2, 0523; GFX942-NEXT: s_cselect_b64 s[2:3], -1, 0524; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]525; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], v0526; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]527; GFX942-NEXT: s_endpgm528 %fp = uitofp i1 %in to double529 store double %fp, ptr addrspace(1) %out, align 8530 ret void531}532 533define amdgpu_kernel void @s_uint_to_fp_i8_to_f64(ptr addrspace(1) %out, i8 %in) {534; SI-LABEL: s_uint_to_fp_i8_to_f64:535; SI: ; %bb.0:536; SI-NEXT: s_load_dword s2, s[8:9], 0x2537; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0538; SI-NEXT: s_add_i32 s12, s12, s17539; SI-NEXT: s_mov_b32 flat_scratch_lo, s13540; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8541; SI-NEXT: s_waitcnt lgkmcnt(0)542; SI-NEXT: s_and_b32 s2, s2, 0xff543; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], s2544; SI-NEXT: v_mov_b32_e32 v3, s1545; SI-NEXT: v_mov_b32_e32 v2, s0546; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]547; SI-NEXT: s_endpgm548;549; VI-LABEL: s_uint_to_fp_i8_to_f64:550; VI: ; %bb.0:551; VI-NEXT: s_load_dword s2, s[8:9], 0x8552; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0553; VI-NEXT: s_add_i32 s12, s12, s17554; VI-NEXT: s_mov_b32 flat_scratch_lo, s13555; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8556; VI-NEXT: s_waitcnt lgkmcnt(0)557; VI-NEXT: s_and_b32 s2, s2, 0xff558; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], s2559; VI-NEXT: v_mov_b32_e32 v3, s1560; VI-NEXT: v_mov_b32_e32 v2, s0561; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]562; VI-NEXT: s_endpgm563;564; GFX942-LABEL: s_uint_to_fp_i8_to_f64:565; GFX942: ; %bb.0:566; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8567; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0568; GFX942-NEXT: v_mov_b32_e32 v2, 0569; GFX942-NEXT: s_waitcnt lgkmcnt(0)570; GFX942-NEXT: s_and_b32 s2, s2, 0xff571; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], s2572; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]573; GFX942-NEXT: s_endpgm574 %fp = uitofp i8 %in to double575 store double %fp, ptr addrspace(1) %out576 ret void577}578 579; FIXME: Worse on VI580define double @v_uint_to_fp_i8_to_f64(i8 %in) {581; SI-LABEL: v_uint_to_fp_i8_to_f64:582; SI: ; %bb.0:583; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)584; SI-NEXT: v_and_b32_e32 v0, 0xff, v0585; SI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0586; SI-NEXT: s_setpc_b64 s[30:31]587;588; VI-LABEL: v_uint_to_fp_i8_to_f64:589; VI: ; %bb.0:590; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)591; VI-NEXT: v_mov_b32_e32 v1, 0xffff592; VI-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0593; VI-NEXT: v_cvt_f64_u32_e32 v[0:1], v0594; VI-NEXT: s_setpc_b64 s[30:31]595;596; GFX942-LABEL: v_uint_to_fp_i8_to_f64:597; GFX942: ; %bb.0:598; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)599; GFX942-NEXT: s_mov_b32 s0, 0xffff600; GFX942-NEXT: v_and_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0601; GFX942-NEXT: v_cvt_f64_u32_e32 v[0:1], v0602; GFX942-NEXT: s_setpc_b64 s[30:31]603 %fp = uitofp i8 %in to double604 ret double %fp605}606 607define amdgpu_kernel void @s_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {608; SI-LABEL: s_select_uint_to_fp_i1_vals_f64:609; SI: ; %bb.0:610; SI-NEXT: s_load_dword s2, s[8:9], 0x2611; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0612; SI-NEXT: s_add_i32 s12, s12, s17613; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8614; SI-NEXT: s_mov_b32 flat_scratch_lo, s13615; SI-NEXT: s_waitcnt lgkmcnt(0)616; SI-NEXT: s_cmp_eq_u32 s2, 0617; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0618; SI-NEXT: v_mov_b32_e32 v3, s1619; SI-NEXT: v_mov_b32_e32 v0, 0620; SI-NEXT: v_mov_b32_e32 v1, s2621; SI-NEXT: v_mov_b32_e32 v2, s0622; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]623; SI-NEXT: s_endpgm624;625; VI-LABEL: s_select_uint_to_fp_i1_vals_f64:626; VI: ; %bb.0:627; VI-NEXT: s_load_dword s2, s[8:9], 0x8628; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0629; VI-NEXT: s_add_i32 s12, s12, s17630; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8631; VI-NEXT: s_mov_b32 flat_scratch_lo, s13632; VI-NEXT: s_waitcnt lgkmcnt(0)633; VI-NEXT: s_cmp_eq_u32 s2, 0634; VI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0635; VI-NEXT: v_mov_b32_e32 v3, s1636; VI-NEXT: v_mov_b32_e32 v0, 0637; VI-NEXT: v_mov_b32_e32 v1, s2638; VI-NEXT: v_mov_b32_e32 v2, s0639; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]640; VI-NEXT: s_endpgm641;642; GFX942-LABEL: s_select_uint_to_fp_i1_vals_f64:643; GFX942: ; %bb.0:644; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8645; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0646; GFX942-NEXT: v_mov_b32_e32 v0, 0647; GFX942-NEXT: s_waitcnt lgkmcnt(0)648; GFX942-NEXT: s_cmp_eq_u32 s2, 0649; GFX942-NEXT: s_cselect_b32 s2, 0x3ff00000, 0650; GFX942-NEXT: v_mov_b32_e32 v1, s2651; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]652; GFX942-NEXT: s_endpgm653 %cmp = icmp eq i32 %in, 0654 %select = select i1 %cmp, double 1.0, double 0.0655 store double %select, ptr addrspace(1) %out, align 8656 ret void657}658 659define void @v_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {660; GCN-LABEL: v_select_uint_to_fp_i1_vals_f64:661; GCN: ; %bb.0:662; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)663; GCN-NEXT: v_mov_b32_e32 v4, 0x3ff00000664; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2665; GCN-NEXT: v_mov_b32_e32 v3, 0666; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc667; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]668; GCN-NEXT: s_waitcnt vmcnt(0)669; GCN-NEXT: s_setpc_b64 s[30:31]670;671; GFX942-LABEL: v_select_uint_to_fp_i1_vals_f64:672; GFX942: ; %bb.0:673; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)674; GFX942-NEXT: v_mov_b32_e32 v3, 0x3ff00000675; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2676; GFX942-NEXT: v_mov_b32_e32 v4, 0677; GFX942-NEXT: s_nop 0678; GFX942-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc679; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off680; GFX942-NEXT: s_waitcnt vmcnt(0)681; GFX942-NEXT: s_setpc_b64 s[30:31]682 %cmp = icmp eq i32 %in, 0683 %select = select i1 %cmp, double 1.0, double 0.0684 store double %select, ptr addrspace(1) %out, align 8685 ret void686}687 688define amdgpu_kernel void @s_select_uint_to_fp_i1_vals_i64(ptr addrspace(1) %out, i32 %in) {689; SI-LABEL: s_select_uint_to_fp_i1_vals_i64:690; SI: ; %bb.0:691; SI-NEXT: s_load_dword s2, s[8:9], 0x2692; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0693; SI-NEXT: s_add_i32 s12, s12, s17694; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8695; SI-NEXT: s_mov_b32 flat_scratch_lo, s13696; SI-NEXT: s_waitcnt lgkmcnt(0)697; SI-NEXT: s_cmp_eq_u32 s2, 0698; SI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0699; SI-NEXT: v_mov_b32_e32 v3, s1700; SI-NEXT: v_mov_b32_e32 v0, 0701; SI-NEXT: v_mov_b32_e32 v1, s2702; SI-NEXT: v_mov_b32_e32 v2, s0703; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]704; SI-NEXT: s_endpgm705;706; VI-LABEL: s_select_uint_to_fp_i1_vals_i64:707; VI: ; %bb.0:708; VI-NEXT: s_load_dword s2, s[8:9], 0x8709; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0710; VI-NEXT: s_add_i32 s12, s12, s17711; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8712; VI-NEXT: s_mov_b32 flat_scratch_lo, s13713; VI-NEXT: s_waitcnt lgkmcnt(0)714; VI-NEXT: s_cmp_eq_u32 s2, 0715; VI-NEXT: s_cselect_b32 s2, 0x3ff00000, 0716; VI-NEXT: v_mov_b32_e32 v3, s1717; VI-NEXT: v_mov_b32_e32 v0, 0718; VI-NEXT: v_mov_b32_e32 v1, s2719; VI-NEXT: v_mov_b32_e32 v2, s0720; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]721; VI-NEXT: s_endpgm722;723; GFX942-LABEL: s_select_uint_to_fp_i1_vals_i64:724; GFX942: ; %bb.0:725; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8726; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0727; GFX942-NEXT: v_mov_b32_e32 v0, 0728; GFX942-NEXT: s_waitcnt lgkmcnt(0)729; GFX942-NEXT: s_cmp_eq_u32 s2, 0730; GFX942-NEXT: s_cselect_b32 s2, 0x3ff00000, 0731; GFX942-NEXT: v_mov_b32_e32 v1, s2732; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]733; GFX942-NEXT: s_endpgm734 %cmp = icmp eq i32 %in, 0735 %select = select i1 %cmp, i64 u0x3ff0000000000000, i64 0736 store i64 %select, ptr addrspace(1) %out, align 8737 ret void738}739 740define void @v_select_uint_to_fp_i1_vals_i64(ptr addrspace(1) %out, i32 %in) {741; GCN-LABEL: v_select_uint_to_fp_i1_vals_i64:742; GCN: ; %bb.0:743; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)744; GCN-NEXT: v_mov_b32_e32 v4, 0x3ff00000745; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2746; GCN-NEXT: v_mov_b32_e32 v3, 0747; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc748; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]749; GCN-NEXT: s_waitcnt vmcnt(0)750; GCN-NEXT: s_setpc_b64 s[30:31]751;752; GFX942-LABEL: v_select_uint_to_fp_i1_vals_i64:753; GFX942: ; %bb.0:754; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)755; GFX942-NEXT: v_mov_b32_e32 v3, 0x3ff00000756; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2757; GFX942-NEXT: v_mov_b32_e32 v4, 0758; GFX942-NEXT: s_nop 0759; GFX942-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc760; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off761; GFX942-NEXT: s_waitcnt vmcnt(0)762; GFX942-NEXT: s_setpc_b64 s[30:31]763 %cmp = icmp eq i32 %in, 0764 %select = select i1 %cmp, i64 u0x3ff0000000000000, i64 0765 store i64 %select, ptr addrspace(1) %out, align 8766 ret void767}768 769; TODO: This should swap the selected order / invert the compare and do it.770define amdgpu_kernel void @s_swap_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {771; SI-LABEL: s_swap_select_uint_to_fp_i1_vals_f64:772; SI: ; %bb.0:773; SI-NEXT: s_load_dword s2, s[8:9], 0x2774; SI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0775; SI-NEXT: s_add_i32 s12, s12, s17776; SI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8777; SI-NEXT: s_mov_b32 flat_scratch_lo, s13778; SI-NEXT: s_waitcnt lgkmcnt(0)779; SI-NEXT: s_cmp_eq_u32 s2, 0780; SI-NEXT: s_cselect_b32 s2, 0, 0x3ff00000781; SI-NEXT: v_mov_b32_e32 v3, s1782; SI-NEXT: v_mov_b32_e32 v0, 0783; SI-NEXT: v_mov_b32_e32 v1, s2784; SI-NEXT: v_mov_b32_e32 v2, s0785; SI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]786; SI-NEXT: s_endpgm787;788; VI-LABEL: s_swap_select_uint_to_fp_i1_vals_f64:789; VI: ; %bb.0:790; VI-NEXT: s_load_dword s2, s[8:9], 0x8791; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0792; VI-NEXT: s_add_i32 s12, s12, s17793; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8794; VI-NEXT: s_mov_b32 flat_scratch_lo, s13795; VI-NEXT: s_waitcnt lgkmcnt(0)796; VI-NEXT: s_cmp_eq_u32 s2, 0797; VI-NEXT: s_cselect_b32 s2, 0, 0x3ff00000798; VI-NEXT: v_mov_b32_e32 v3, s1799; VI-NEXT: v_mov_b32_e32 v0, 0800; VI-NEXT: v_mov_b32_e32 v1, s2801; VI-NEXT: v_mov_b32_e32 v2, s0802; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]803; VI-NEXT: s_endpgm804;805; GFX942-LABEL: s_swap_select_uint_to_fp_i1_vals_f64:806; GFX942: ; %bb.0:807; GFX942-NEXT: s_load_dword s2, s[4:5], 0x8808; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0809; GFX942-NEXT: v_mov_b32_e32 v0, 0810; GFX942-NEXT: s_waitcnt lgkmcnt(0)811; GFX942-NEXT: s_cmp_eq_u32 s2, 0812; GFX942-NEXT: s_cselect_b32 s2, 0, 0x3ff00000813; GFX942-NEXT: v_mov_b32_e32 v1, s2814; GFX942-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1]815; GFX942-NEXT: s_endpgm816 %cmp = icmp eq i32 %in, 0817 %select = select i1 %cmp, double 0.0, double 1.0818 store double %select, ptr addrspace(1) %out, align 8819 ret void820}821 822define void @v_swap_select_uint_to_fp_i1_vals_f64(ptr addrspace(1) %out, i32 %in) {823; GCN-LABEL: v_swap_select_uint_to_fp_i1_vals_f64:824; GCN: ; %bb.0:825; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)826; GCN-NEXT: v_mov_b32_e32 v4, 0x3ff00000827; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2828; GCN-NEXT: v_mov_b32_e32 v3, 0829; GCN-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc830; GCN-NEXT: flat_store_dwordx2 v[0:1], v[3:4]831; GCN-NEXT: s_waitcnt vmcnt(0)832; GCN-NEXT: s_setpc_b64 s[30:31]833;834; GFX942-LABEL: v_swap_select_uint_to_fp_i1_vals_f64:835; GFX942: ; %bb.0:836; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)837; GFX942-NEXT: v_mov_b32_e32 v3, 0x3ff00000838; GFX942-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2839; GFX942-NEXT: v_mov_b32_e32 v4, 0840; GFX942-NEXT: s_nop 0841; GFX942-NEXT: v_cndmask_b32_e64 v5, v3, 0, vcc842; GFX942-NEXT: global_store_dwordx2 v[0:1], v[4:5], off843; GFX942-NEXT: s_waitcnt vmcnt(0)844; GFX942-NEXT: s_setpc_b64 s[30:31]845 %cmp = icmp eq i32 %in, 0846 %select = select i1 %cmp, double 0.0, double 1.0847 store double %select, ptr addrspace(1) %out, align 8848 ret void849}850