713 lines · plain
1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI,MUBUF,ALIGNED %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire -mattr=+unaligned-access-mode < %s | FileCheck -check-prefixes=SI,MUBUF,UNALIGNED %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=SI,MUBUF,ALIGNED %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=SI,FLATSCR,ALIGNED %s5 6; SI-LABEL: {{^}}local_unaligned_load_store_i16:7; SI: ds_read_u88; SI: ds_read_u89; SI: ds_write_b810; SI: ds_write_b811; SI: s_endpgm12define amdgpu_kernel void @local_unaligned_load_store_i16(ptr addrspace(3) %p, ptr addrspace(3) %r) #0 {13 %v = load i16, ptr addrspace(3) %p, align 114 store i16 %v, ptr addrspace(3) %r, align 115 ret void16}17 18; SI-LABEL: {{^}}global_unaligned_load_store_i16:19; ALIGNED: buffer_load_ubyte20; ALIGNED: buffer_load_ubyte21; ALIGNED: buffer_store_byte22; ALIGNED: buffer_store_byte23 24; UNALIGNED: buffer_load_ushort25; UNALIGNED: buffer_store_short26; SI: s_endpgm27define amdgpu_kernel void @global_unaligned_load_store_i16(ptr addrspace(1) %p, ptr addrspace(1) %r) #0 {28 %v = load i16, ptr addrspace(1) %p, align 129 store i16 %v, ptr addrspace(1) %r, align 130 ret void31}32 33; SI-LABEL: {{^}}local_unaligned_load_store_i32:34 35; SI: ds_read_u836; SI: ds_read_u837; SI: ds_read_u838; SI: ds_read_u839; SI-NOT: v_or40; SI-NOT: v_lshl41; SI: ds_write_b842; SI: ds_write_b843; SI: ds_write_b844; SI: ds_write_b845; SI: s_endpgm46define amdgpu_kernel void @local_unaligned_load_store_i32(ptr addrspace(3) %p, ptr addrspace(3) %r) #0 {47 %v = load i32, ptr addrspace(3) %p, align 148 store i32 %v, ptr addrspace(3) %r, align 149 ret void50}51 52; SI-LABEL: {{^}}global_unaligned_load_store_i32:53; ALIGNED: buffer_load_ubyte54; ALIGNED: buffer_load_ubyte55; ALIGNED: buffer_load_ubyte56; ALIGNED: buffer_load_ubyte57; ALIGNED: buffer_store_byte58; ALIGNED: buffer_store_byte59; ALIGNED: buffer_store_byte60; ALIGNED: buffer_store_byte61 62; UNALIGNED: buffer_load_dword63; UNALIGNED: buffer_store_dword64define amdgpu_kernel void @global_unaligned_load_store_i32(ptr addrspace(1) %p, ptr addrspace(1) %r) #0 {65 %v = load i32, ptr addrspace(1) %p, align 166 store i32 %v, ptr addrspace(1) %r, align 167 ret void68}69 70; SI-LABEL: {{^}}global_align2_load_store_i32:71; ALIGNED: buffer_load_ushort72; ALIGNED: buffer_load_ushort73; ALIGNED: buffer_store_short74; ALIGNED: buffer_store_short75 76; UNALIGNED: buffer_load_dword77; UNALIGNED: buffer_store_dword78define amdgpu_kernel void @global_align2_load_store_i32(ptr addrspace(1) %p, ptr addrspace(1) %r) #0 {79 %v = load i32, ptr addrspace(1) %p, align 280 store i32 %v, ptr addrspace(1) %r, align 281 ret void82}83 84; GCN-LABEL: {{^}}local_align2_load_store_i32:85; GCN: ds_read_u1686; GCN: ds_read_u1687; GCN: ds_write_b1688; GCN: ds_write_b1689define amdgpu_kernel void @local_align2_load_store_i32(ptr addrspace(3) %p, ptr addrspace(3) %r) #0 {90 %v = load i32, ptr addrspace(3) %p, align 291 store i32 %v, ptr addrspace(3) %r, align 292 ret void93}94 95; SI-LABEL: {{^}}local_unaligned_load_store_i64:96; SI: ds_read_u897; SI: ds_read_u898; SI: ds_read_u899; SI: ds_read_u8100; SI: ds_read_u8101; SI: ds_read_u8102; SI: ds_read_u8103; SI: ds_read_u8104 105; SI-NOT: v_or_b32106; SI-NOT: v_lshl107; SI: ds_write_b8108; SI-NOT: v_or_b32109; SI-NOT: v_lshl110 111; SI: ds_write_b8112; SI-NOT: v_or_b32113; SI-NOT: v_lshl114 115; SI: ds_write_b8116; SI-NOT: v_or_b32117; SI-NOT: v_lshl118 119; SI: ds_write_b8120; SI-NOT: v_or_b32121; SI-NOT: v_lshl122 123; SI: ds_write_b8124; SI-NOT: v_or_b32125; SI-NOT: v_lshl126 127; SI: ds_write_b8128; SI-NOT: v_or_b32129; SI-NOT: v_lshl130 131; SI: ds_write_b8132; SI-NOT: v_or_b32133; SI-NOT: v_lshl134; SI: ds_write_b8135; SI: s_endpgm136define amdgpu_kernel void @local_unaligned_load_store_i64(ptr addrspace(3) %p, ptr addrspace(3) %r) #0 {137 %v = load i64, ptr addrspace(3) %p, align 1138 store i64 %v, ptr addrspace(3) %r, align 1139 ret void140}141 142; SI-LABEL: {{^}}local_unaligned_load_store_v2i32:143; SI: ds_read_u8144; SI: ds_read_u8145; SI: ds_read_u8146; SI: ds_read_u8147; SI: ds_read_u8148; SI: ds_read_u8149; SI: ds_read_u8150; SI: ds_read_u8151 152; SI-NOT: v_or_b32153; SI-NOT: v_lshl154; SI: ds_write_b8155; SI-NOT: v_or_b32156; SI-NOT: v_lshl157 158; SI: ds_write_b8159; SI-NOT: v_or_b32160; SI-NOT: v_lshl161 162; SI: ds_write_b8163; SI-NOT: v_or_b32164; SI-NOT: v_lshl165 166; SI: ds_write_b8167; SI-NOT: v_or_b32168; SI-NOT: v_lshl169 170; SI: ds_write_b8171; SI-NOT: v_or_b32172; SI-NOT: v_lshl173 174; SI: ds_write_b8175; SI-NOT: v_or_b32176; SI-NOT: v_lshl177 178; SI: ds_write_b8179; SI-NOT: v_or_b32180; SI-NOT: v_lshl181; SI: ds_write_b8182; SI: s_endpgm183define amdgpu_kernel void @local_unaligned_load_store_v2i32(ptr addrspace(3) %p, ptr addrspace(3) %r) #0 {184 %v = load <2 x i32>, ptr addrspace(3) %p, align 1185 store <2 x i32> %v, ptr addrspace(3) %r, align 1186 ret void187}188 189; SI-LABEL: {{^}}global_align2_load_store_i64:190; ALIGNED: buffer_load_ushort191; ALIGNED: buffer_load_ushort192 193; ALIGNED-NOT: v_or_194; ALIGNED-NOT: v_lshl195 196; ALIGNED: buffer_load_ushort197 198; ALIGNED-NOT: v_or_199; ALIGNED-NOT: v_lshl200 201; ALIGNED: buffer_load_ushort202 203; ALIGNED-NOT: v_or_204; ALIGNED-NOT: v_lshl205 206; ALIGNED: buffer_store_short207; ALIGNED: buffer_store_short208; ALIGNED: buffer_store_short209; ALIGNED: buffer_store_short210 211; UNALIGNED: buffer_load_dwordx2212; UNALIGNED: buffer_store_dwordx2213define amdgpu_kernel void @global_align2_load_store_i64(ptr addrspace(1) %p, ptr addrspace(1) %r) #0 {214 %v = load i64, ptr addrspace(1) %p, align 2215 store i64 %v, ptr addrspace(1) %r, align 2216 ret void217}218 219; SI-LABEL: {{^}}unaligned_load_store_i64_global:220; ALIGNED: buffer_load_ubyte221; ALIGNED: buffer_load_ubyte222; ALIGNED: buffer_load_ubyte223; ALIGNED: buffer_load_ubyte224; ALIGNED: buffer_load_ubyte225; ALIGNED: buffer_load_ubyte226; ALIGNED: buffer_load_ubyte227; ALIGNED: buffer_load_ubyte228 229; ALIGNED-NOT: v_or_230; ALIGNED-NOT: v_lshl231 232; ALIGNED: buffer_store_byte233; ALIGNED: buffer_store_byte234; ALIGNED: buffer_store_byte235; ALIGNED: buffer_store_byte236; ALIGNED: buffer_store_byte237; ALIGNED: buffer_store_byte238; ALIGNED: buffer_store_byte239; ALIGNED: buffer_store_byte240 241; UNALIGNED: buffer_load_dwordx2242; UNALIGNED: buffer_store_dwordx2243define amdgpu_kernel void @unaligned_load_store_i64_global(ptr addrspace(1) %p, ptr addrspace(1) %r) #0 {244 %v = load i64, ptr addrspace(1) %p, align 1245 store i64 %v, ptr addrspace(1) %r, align 1246 ret void247}248 249; GCN-LABEL: {{^}}local_unaligned_load_store_v4i32:250; GCN: ds_read_u8251; GCN: ds_read_u8252; GCN: ds_read_u8253; GCN: ds_read_u8254 255; GCN: ds_read_u8256; GCN: ds_read_u8257; GCN: ds_read_u8258; GCN: ds_read_u8259 260; GCN: ds_read_u8261; GCN: ds_read_u8262; GCN: ds_read_u8263; GCN: ds_read_u8264 265; GCN: ds_read_u8266; GCN: ds_read_u8267; GCN: ds_read_u8268; GCN: ds_read_u8269 270; GCN: ds_write_b8271; GCN: ds_write_b8272; GCN: ds_write_b8273; GCN: ds_write_b8274 275; GCN: ds_write_b8276; GCN: ds_write_b8277; GCN: ds_write_b8278; GCN: ds_write_b8279 280; GCN: ds_write_b8281; GCN: ds_write_b8282; GCN: ds_write_b8283; GCN: ds_write_b8284 285; GCN: ds_write_b8286; GCN: ds_write_b8287; GCN: ds_write_b8288; GCN: ds_write_b8289; GCN: s_endpgm290define amdgpu_kernel void @local_unaligned_load_store_v4i32(ptr addrspace(3) %p, ptr addrspace(3) %r) #0 {291 %v = load <4 x i32>, ptr addrspace(3) %p, align 1292 store <4 x i32> %v, ptr addrspace(3) %r, align 1293 ret void294}295 296; SI-LABEL: {{^}}global_unaligned_load_store_v4i32297; ALIGNED: buffer_load_ubyte298; ALIGNED: buffer_load_ubyte299; ALIGNED: buffer_load_ubyte300; ALIGNED: buffer_load_ubyte301; ALIGNED: buffer_load_ubyte302; ALIGNED: buffer_load_ubyte303; ALIGNED: buffer_load_ubyte304; ALIGNED: buffer_load_ubyte305; ALIGNED: buffer_load_ubyte306; ALIGNED: buffer_load_ubyte307; ALIGNED: buffer_load_ubyte308; ALIGNED: buffer_load_ubyte309; ALIGNED: buffer_load_ubyte310; ALIGNED: buffer_load_ubyte311; ALIGNED: buffer_load_ubyte312; ALIGNED: buffer_load_ubyte313 314; ALIGNED: buffer_store_byte315; ALIGNED: buffer_store_byte316; ALIGNED: buffer_store_byte317; ALIGNED: buffer_store_byte318; ALIGNED: buffer_store_byte319; ALIGNED: buffer_store_byte320; ALIGNED: buffer_store_byte321; ALIGNED: buffer_store_byte322; ALIGNED: buffer_store_byte323; ALIGNED: buffer_store_byte324; ALIGNED: buffer_store_byte325; ALIGNED: buffer_store_byte326; ALIGNED: buffer_store_byte327; ALIGNED: buffer_store_byte328; ALIGNED: buffer_store_byte329; ALIGNED: buffer_store_byte330 331; UNALIGNED: buffer_load_dwordx4332; UNALIGNED: buffer_store_dwordx4333define amdgpu_kernel void @global_unaligned_load_store_v4i32(ptr addrspace(1) %p, ptr addrspace(1) %r) #0 {334 %v = load <4 x i32>, ptr addrspace(1) %p, align 1335 store <4 x i32> %v, ptr addrspace(1) %r, align 1336 ret void337}338 339; GCN-LABEL: {{^}}local_load_i64_align_4:340; GCN: ds_read2_b32341define amdgpu_kernel void @local_load_i64_align_4(ptr addrspace(1) nocapture %out, ptr addrspace(3) %in) #0 {342 %val = load i64, ptr addrspace(3) %in, align 4343 store i64 %val, ptr addrspace(1) %out, align 8344 ret void345}346 347; GCN-LABEL: {{^}}local_load_i64_align_4_with_offset348; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9349define amdgpu_kernel void @local_load_i64_align_4_with_offset(ptr addrspace(1) nocapture %out, ptr addrspace(3) %in) #0 {350 %ptr = getelementptr i64, ptr addrspace(3) %in, i32 4351 %val = load i64, ptr addrspace(3) %ptr, align 4352 store i64 %val, ptr addrspace(1) %out, align 8353 ret void354}355 356; GCN-LABEL: {{^}}local_load_i64_align_4_with_split_offset:357; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits358; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset1:1359; GCN: s_endpgm360define amdgpu_kernel void @local_load_i64_align_4_with_split_offset(ptr addrspace(1) nocapture %out, ptr addrspace(3) %in) #0 {361 %ptr255 = getelementptr i32, ptr addrspace(3) %in, i32 255362 %val = load i64, ptr addrspace(3) %ptr255, align 4363 store i64 %val, ptr addrspace(1) %out, align 8364 ret void365}366 367; GCN-LABEL: {{^}}local_load_i64_align_1:368; GCN: ds_read_u8369; GCN: ds_read_u8370; GCN: ds_read_u8371; GCN: ds_read_u8372; GCN: ds_read_u8373; GCN: ds_read_u8374; GCN: ds_read_u8375; GCN: ds_read_u8376; GCN: store_dwordx2377define amdgpu_kernel void @local_load_i64_align_1(ptr addrspace(1) nocapture %out, ptr addrspace(3) %in) #0 {378 %val = load i64, ptr addrspace(3) %in, align 1379 store i64 %val, ptr addrspace(1) %out, align 8380 ret void381}382 383; GCN-LABEL: {{^}}local_store_i64_align_4:384; GCN: ds_write2_b32385define amdgpu_kernel void @local_store_i64_align_4(ptr addrspace(3) %out, i64 %val) #0 {386 store i64 %val, ptr addrspace(3) %out, align 4387 ret void388}389 390; GCN-LABEL: {{^}}local_store_i64_align_4_with_offset391; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9392; GCN: s_endpgm393define amdgpu_kernel void @local_store_i64_align_4_with_offset(ptr addrspace(3) %out) #0 {394 %ptr = getelementptr i64, ptr addrspace(3) %out, i32 4395 store i64 0, ptr addrspace(3) %ptr, align 4396 ret void397}398 399; GCN-LABEL: {{^}}local_store_i64_align_4_with_split_offset:400; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits401; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1402; GCN: s_endpgm403define amdgpu_kernel void @local_store_i64_align_4_with_split_offset(ptr addrspace(3) %out) #0 {404 %ptr255 = getelementptr i32, ptr addrspace(3) %out, i32 255405 store i64 0, ptr addrspace(3) %out, align 4406 ret void407}408 409; SI-LABEL: {{^}}constant_unaligned_load_i32:410; ALIGNED: buffer_load_ubyte411; ALIGNED: buffer_load_ubyte412; ALIGNED: buffer_load_ubyte413; ALIGNED: buffer_load_ubyte414 415; UNALIGNED: s_load_dword416 417; SI: buffer_store_dword418define amdgpu_kernel void @constant_unaligned_load_i32(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {419 %v = load i32, ptr addrspace(4) %p, align 1420 store i32 %v, ptr addrspace(1) %r, align 4421 ret void422}423 424; SI-LABEL: {{^}}constant_align2_load_i32:425; ALIGNED: buffer_load_ushort426; ALIGNED: buffer_load_ushort427 428; UNALIGNED: s_load_dword429; UNALIGNED: buffer_store_dword430define amdgpu_kernel void @constant_align2_load_i32(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {431 %v = load i32, ptr addrspace(4) %p, align 2432 store i32 %v, ptr addrspace(1) %r, align 4433 ret void434}435 436; SI-LABEL: {{^}}constant_align2_load_i64:437; ALIGNED: buffer_load_ushort438; ALIGNED: buffer_load_ushort439; ALIGNED: buffer_load_ushort440; ALIGNED: buffer_load_ushort441 442; UNALIGNED: s_load_dwordx4443; UNALIGNED: buffer_store_dwordx2444define amdgpu_kernel void @constant_align2_load_i64(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {445 %v = load i64, ptr addrspace(4) %p, align 2446 store i64 %v, ptr addrspace(1) %r, align 4447 ret void448}449 450; SI-LABEL: {{^}}constant_align4_load_i64:451; SI: s_load_dwordx2452; SI: buffer_store_dwordx2453define amdgpu_kernel void @constant_align4_load_i64(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {454 %v = load i64, ptr addrspace(4) %p, align 4455 store i64 %v, ptr addrspace(1) %r, align 4456 ret void457}458 459; SI-LABEL: {{^}}constant_align4_load_v4i32:460; SI: s_load_dwordx4461; SI: buffer_store_dwordx4462define amdgpu_kernel void @constant_align4_load_v4i32(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {463 %v = load <4 x i32>, ptr addrspace(4) %p, align 4464 store <4 x i32> %v, ptr addrspace(1) %r, align 4465 ret void466}467 468; SI-LABEL: {{^}}constant_unaligned_load_v2i32:469; ALIGNED: buffer_load_ubyte470; ALIGNED: buffer_load_ubyte471; ALIGNED: buffer_load_ubyte472; ALIGNED: buffer_load_ubyte473 474; ALIGNED: buffer_load_ubyte475; ALIGNED: buffer_load_ubyte476; ALIGNED: buffer_load_ubyte477; ALIGNED: buffer_load_ubyte478 479; UNALIGNED: buffer_load_dwordx2480 481; SI: buffer_store_dwordx2482define amdgpu_kernel void @constant_unaligned_load_v2i32(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {483 %v = load <2 x i32>, ptr addrspace(4) %p, align 1484 store <2 x i32> %v, ptr addrspace(1) %r, align 4485 ret void486}487 488; SI-LABEL: {{^}}constant_unaligned_load_v4i32:489; ALIGNED: buffer_load_ubyte490; ALIGNED: buffer_load_ubyte491; ALIGNED: buffer_load_ubyte492; ALIGNED: buffer_load_ubyte493 494; ALIGNED: buffer_load_ubyte495; ALIGNED: buffer_load_ubyte496; ALIGNED: buffer_load_ubyte497; ALIGNED: buffer_load_ubyte498 499; ALIGNED: buffer_load_ubyte500; ALIGNED: buffer_load_ubyte501; ALIGNED: buffer_load_ubyte502; ALIGNED: buffer_load_ubyte503 504; ALIGNED: buffer_load_ubyte505; ALIGNED: buffer_load_ubyte506; ALIGNED: buffer_load_ubyte507; ALIGNED: buffer_load_ubyte508 509; UNALIGNED: buffer_load_dwordx4510 511; SI: buffer_store_dwordx4512define amdgpu_kernel void @constant_unaligned_load_v4i32(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {513 %v = load <4 x i32>, ptr addrspace(4) %p, align 1514 store <4 x i32> %v, ptr addrspace(1) %r, align 4515 ret void516}517 518; SI-LABEL: {{^}}constant_align4_load_i8:519; SI: s_load_dword520; SI: buffer_store_byte521define amdgpu_kernel void @constant_align4_load_i8(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {522 %v = load i8, ptr addrspace(4) %p, align 4523 store i8 %v, ptr addrspace(1) %r, align 4524 ret void525}526 527; SI-LABEL: {{^}}constant_align2_load_i8:528; SI: buffer_load_ubyte529; SI: buffer_store_byte530define amdgpu_kernel void @constant_align2_load_i8(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {531 %v = load i8, ptr addrspace(4) %p, align 2532 store i8 %v, ptr addrspace(1) %r, align 2533 ret void534}535 536; SI-LABEL: {{^}}constant_align4_merge_load_2_i32:537; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}538; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[LO]]539; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HI]]540; SI: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]541define amdgpu_kernel void @constant_align4_merge_load_2_i32(ptr addrspace(4) %p, ptr addrspace(1) %r) #0 {542 %gep0 = getelementptr i32, ptr addrspace(4) %p, i64 1543 %v0 = load i32, ptr addrspace(4) %p, align 4544 %v1 = load i32, ptr addrspace(4) %gep0, align 4545 546 %gep1 = getelementptr i32, ptr addrspace(1) %r, i64 1547 store i32 %v0, ptr addrspace(1) %r, align 4548 store i32 %v1, ptr addrspace(1) %gep1, align 4549 ret void550}551 552; SI-LABEL: {{^}}local_load_align1_v16i8:553; SI: ds_read_u8554; SI: ds_read_u8555; SI: ds_read_u8556; SI: ds_read_u8557; SI: ds_read_u8558; SI: ds_read_u8559; SI: ds_read_u8560; SI: ds_read_u8561; SI: ds_read_u8562; SI: ds_read_u8563; SI: ds_read_u8564; SI: ds_read_u8565; SI: ds_read_u8566; SI: ds_read_u8567; SI: ds_read_u8568; SI: ds_read_u8569 570; SI: ScratchSize: 0{{$}}571define amdgpu_kernel void @local_load_align1_v16i8(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {572 %ld = load <16 x i8>, ptr addrspace(3) %in, align 1573 store <16 x i8> %ld, ptr addrspace(1) %out574 ret void575}576 577; SI-LABEL: {{^}}local_store_align1_v16i8:578; SI: ds_write_b8579; SI: ds_write_b8580; SI: ds_write_b8581; SI: ds_write_b8582; SI: ds_write_b8583; SI: ds_write_b8584; SI: ds_write_b8585; SI: ds_write_b8586; SI: ds_write_b8587; SI: ds_write_b8588; SI: ds_write_b8589; SI: ds_write_b8590; SI: ds_write_b8591; SI: ds_write_b8592; SI: ds_write_b8593; SI: ds_write_b8594 595; SI: ScratchSize: 0{{$}}596define amdgpu_kernel void @local_store_align1_v16i8(ptr addrspace(3) %out) #0 {597 store <16 x i8> zeroinitializer, ptr addrspace(3) %out, align 1598 ret void599}600 601; SI-LABEL: {{^}}private_load_align1_f64:602; MUBUF: buffer_load_ubyte603; MUBUF: buffer_load_ubyte604; MUBUF: buffer_load_ubyte605; MUBUF: buffer_load_ubyte606; MUBUF: buffer_load_ubyte607; MUBUF: buffer_load_ubyte608; MUBUF: buffer_load_ubyte609; MUBUF: buffer_load_ubyte610; FLATSCR: scratch_load_ubyte611; FLATSCR: scratch_load_ubyte612; FLATSCR: scratch_load_ubyte613; FLATSCR: scratch_load_ubyte614; FLATSCR: scratch_load_ubyte615; FLATSCR: scratch_load_ubyte616; FLATSCR: scratch_load_ubyte617; FLATSCR: scratch_load_ubyte618define double @private_load_align1_f64(ptr addrspace(5) %in) {619 %x = load double, ptr addrspace(5) %in, align 1620 ret double %x621}622 623; SI-LABEL: {{^}}private_store_align1_f64:624; MUBUF: buffer_store_byte625; MUBUF: buffer_store_byte626; MUBUF: buffer_store_byte627; MUBUF: buffer_store_byte628; MUBUF: buffer_store_byte629; MUBUF: buffer_store_byte630; MUBUF: buffer_store_byte631; MUBUF: buffer_store_byte632; FLATSCR: scratch_store_byte633; FLATSCR: scratch_store_byte634; FLATSCR: scratch_store_byte635; FLATSCR: scratch_store_byte636; FLATSCR: scratch_store_byte637; FLATSCR: scratch_store_byte638; FLATSCR: scratch_store_byte639; FLATSCR: scratch_store_byte640define void @private_store_align1_f64(ptr addrspace(5) %out, double %x) #0 {641 store double %x, ptr addrspace(5) %out, align 1642 ret void643}644 645; SI-LABEL: {{^}}private_load_align4_f64:646; MUBUF: buffer_load_dword647; MUBUF: buffer_load_dword648; FLATSCR: scratch_load_dwordx2649define double @private_load_align4_f64(ptr addrspace(5) %in) {650 %x = load double, ptr addrspace(5) %in, align 4651 ret double %x652}653 654; SI-LABEL: {{^}}private_store_align4_f64:655; MUBUF: buffer_store_dword656; MUBUF: buffer_store_dword657; FLATSCR: scratch_store_dwordx2658define void @private_store_align4_f64(ptr addrspace(5) %out, double %x) #0 {659 store double %x, ptr addrspace(5) %out, align 4660 ret void661}662 663; SI-LABEL: {{^}}private_load_align2_f64:664; MUBUF: buffer_load_ushort665; MUBUF: buffer_load_ushort666; MUBUF: buffer_load_ushort667; MUBUF: buffer_load_ushort668; FLATSCR: scratch_load_ushort669; FLATSCR: scratch_load_ushort670; FLATSCR: scratch_load_ushort671; FLATSCR: scratch_load_ushort672define double @private_load_align2_f64(ptr addrspace(5) %in) {673 %x = load double, ptr addrspace(5) %in, align 2674 ret double %x675}676 677; SI-LABEL: {{^}}private_store_align2_f64:678; MUBUF: buffer_store_short679; MUBUF: buffer_store_short680; MUBUF: buffer_store_short681; MUBUF: buffer_store_short682; FLATSCR: scratch_store_short683; FLATSCR: scratch_store_short684; FLATSCR: scratch_store_short685; FLATSCR: scratch_store_short686define void @private_store_align2_f64(ptr addrspace(5) %out, double %x) #0 {687 store double %x, ptr addrspace(5) %out, align 2688 ret void689}690 691; Should not merge this to a dword store692define amdgpu_kernel void @global_store_2xi16_align2(ptr addrspace(1) %p, ptr addrspace(1) %r) #0 {693 %gep.r = getelementptr i16, ptr addrspace(1) %r, i64 1694 %v = load i16, ptr addrspace(1) %p, align 2695 store i16 1, ptr addrspace(1) %r, align 2696 store i16 2, ptr addrspace(1) %gep.r, align 2697 ret void698}699 700; Should not merge this to a word load701define i32 @load_2xi16_align2(ptr addrspace(1) %p) #0 {702 %gep.p = getelementptr i16, ptr addrspace(1) %p, i64 1703 %p.0 = load i16, ptr addrspace(1) %p, align 2704 %p.1 = load i16, ptr addrspace(1) %gep.p, align 2705 %zext.0 = zext i16 %p.0 to i32706 %zext.1 = zext i16 %p.1 to i32707 %shl.1 = shl i32 %zext.1, 16708 %or = or i32 %zext.0, %shl.1709 ret i32 %or710}711 712attributes #0 = { nounwind }713