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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck %s3; RUN: llc -mtriple=amdgcn -early-live-intervals < %s | FileCheck %s4 5; We may have subregister live ranges that are undefined on some paths. The6; verifier should not complain about this.7 8define amdgpu_kernel void @func() #0 {9; CHECK-LABEL: func:10; CHECK: ; %bb.0: ; %B011; CHECK-NEXT: s_cmp_lg_u32 s8, 012; CHECK-NEXT: s_mov_b32 s0, 013; CHECK-NEXT: s_cbranch_scc1 .LBB0_214; CHECK-NEXT: ; %bb.1: ; %B30.115; CHECK-NEXT: s_mov_b32 s0, 0x7fc0000016; CHECK-NEXT: .LBB0_2: ; %B30.217; CHECK-NEXT: v_mov_b32_e32 v0, s018; CHECK-NEXT: s_mov_b32 m0, -119; CHECK-NEXT: ds_write_b32 v0, v020; CHECK-NEXT: s_endpgm21B0:22 %id = call i32 @llvm.amdgcn.workgroup.id.x()23 %cmp = icmp eq i32 %id, 024 br i1 %cmp, label %B1, label %B225 26B1:27 br label %B228 29B2:30 %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ <float 0.0, float 0.0, float 0.0, float poison>, %B0 ]31 br i1 %cmp, label %B30.1, label %B30.232 33B30.1:34 %sub = fsub <4 x float> %v0, splat (float 0x7FF8000000000000)35 br label %B30.236 37B30.2:38 %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ]39 %ve0 = extractelement <4 x float> %v3, i32 040 store float %ve0, ptr addrspace(3) poison, align 441 ret void42}43 44; FIXME: Extra undef subregister copy should be removed before45; overwritten with defined copy46define amdgpu_ps float @valley_partially_undef_copy() #0 {47; CHECK-LABEL: valley_partially_undef_copy:48; CHECK: ; %bb.0: ; %bb49; CHECK-NEXT: s_mov_b32 s3, 0xf00050; CHECK-NEXT: s_mov_b32 s2, -151; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc52; CHECK-NEXT: s_waitcnt vmcnt(0)53; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc54; CHECK-NEXT: s_waitcnt vmcnt(0)55; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc0000056; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 057; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 058; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v159; CHECK-NEXT: s_waitcnt expcnt(1)60; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc61; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v162; CHECK-NEXT: .LBB1_1: ; %bb963; CHECK-NEXT: ; =>This Inner Loop Header: Depth=164; CHECK-NEXT: s_and_b64 vcc, exec, s[0:1]65; CHECK-NEXT: s_cbranch_vccnz .LBB1_166; CHECK-NEXT: ; %bb.2: ; %bb1167; CHECK-NEXT: s_mov_b32 s3, 0xf00068; CHECK-NEXT: s_mov_b32 s2, -169; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 070; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0)71; CHECK-NEXT: ; return to shader part epilog72bb:73 %tmp = load volatile i32, ptr addrspace(1) poison, align 474 %tmp1 = load volatile i32, ptr addrspace(1) poison, align 475 %tmp2 = insertelement <4 x i32> poison, i32 %tmp1, i32 076 %tmp3 = bitcast i32 %tmp1 to float77 %tmp4 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp3, float %tmp3, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)78 %tmp5 = extractelement <4 x float> %tmp4, i32 079 %tmp6 = fmul float %tmp5, 0x7FF800000000000080 %tmp7 = fadd float %tmp6, %tmp681 %tmp8 = insertelement <4 x i32> %tmp2, i32 %tmp, i32 182 store <4 x i32> %tmp8, ptr addrspace(1) poison, align 1683 store float %tmp7, ptr addrspace(1) poison, align 484 br label %bb985 86bb9: ; preds = %bb9, %bb87 %tmp10 = icmp eq i32 %tmp, 088 br i1 %tmp10, label %bb9, label %bb1189 90bb11: ; preds = %bb991 store <4 x i32> %tmp2, ptr addrspace(1) poison, align 1692 ret float poison93}94 95; FIXME: Should be able to remove the undef copies96define amdgpu_kernel void @partially_undef_copy() #0 {97; CHECK-LABEL: partially_undef_copy:98; CHECK: ; %bb.0:99; CHECK-NEXT: ;;#ASMSTART100; CHECK-NEXT: v_mov_b32_e32 v5, 5101; CHECK-NEXT: ;;#ASMEND102; CHECK-NEXT: ;;#ASMSTART103; CHECK-NEXT: v_mov_b32_e32 v6, 6104; CHECK-NEXT: ;;#ASMEND105; CHECK-NEXT: v_mov_b32_e32 v0, v5106; CHECK-NEXT: v_mov_b32_e32 v1, v6107; CHECK-NEXT: v_mov_b32_e32 v2, v7108; CHECK-NEXT: v_mov_b32_e32 v3, v8109; CHECK-NEXT: s_mov_b32 s3, 0xf000110; CHECK-NEXT: s_mov_b32 s2, -1111; CHECK-NEXT: v_mov_b32_e32 v0, v6112; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0113; CHECK-NEXT: s_waitcnt vmcnt(0)114; CHECK-NEXT: ;;#ASMSTART115; CHECK-NEXT: v_nop116; CHECK-NEXT: ;;#ASMEND117; CHECK-NEXT: s_endpgm118 %tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()119 %tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()120 121 %partially.undef.0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0122 %partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0123 124 store volatile <4 x i32> %partially.undef.1, ptr addrspace(1) poison, align 16125 tail call void asm sideeffect "v_nop", "v={v[5:8]}"(<4 x i32> %partially.undef.0)126 ret void127}128 129declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1130 131attributes #0 = { nounwind }132attributes #1 = { nounwind readonly }133