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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GCN %s3 4define amdgpu_kernel void @uniform_build_vector(i64 %in, ptr addrspace(1) %out) {5; GCN-LABEL: uniform_build_vector:6; GCN: ; %bb.0: ; %entry7; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x08; GCN-NEXT: s_waitcnt lgkmcnt(0)9; GCN-NEXT: s_lshr_b64 s[4:5], s[0:1], 110; GCN-NEXT: s_mov_b32 s5, 011; GCN-NEXT: s_mov_b32 s6, s512; GCN-NEXT: s_mov_b32 s7, s513; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 014; GCN-NEXT: s_waitcnt vmcnt(0)15; GCN-NEXT: v_mov_b32_e32 v1, 016; GCN-NEXT: ; sched_barrier mask(0x00000000)17; GCN-NEXT: v_and_b32_e32 v0, 1, v018; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v019; GCN-NEXT: global_store_dword v1, v0, s[2:3]20; GCN-NEXT: s_endpgm21entry:22 %shifted = lshr i64 %in, 123 %trunc = trunc i64 %shifted to i3224 %insert = insertelement <4 x i32> zeroinitializer, i32 %trunc, i64 025 %load = tail call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %insert, i32 0, i32 0, i32 0)26 tail call void @llvm.amdgcn.sched.barrier(i32 0)27 %extract = extractelement <4 x i32> %load, i64 028 %and = and i32 %extract, 129 %convert = sitofp i32 %and to float30 store float %convert, ptr addrspace(1) %out31 ret void32}33 34; Function Attrs: convergent nocallback nofree nounwind willreturn35declare void @llvm.amdgcn.sched.barrier(i32 immarg) #036 37; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)38declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32 immarg) #1