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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=verde -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-early-ifcvt=0 -machine-sink-split-probability-threshold=0 -structurizecfg-skip-uniform-regions < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s4 5define amdgpu_kernel void @uniform_if_scc(i32 %cond, ptr addrspace(1) %out) {6; SI-LABEL: uniform_if_scc:7; SI: ; %bb.0: ; %entry8; SI-NEXT: s_load_dword s0, s[4:5], 0x99; SI-NEXT: s_waitcnt lgkmcnt(0)10; SI-NEXT: s_cmp_eq_u32 s0, 011; SI-NEXT: s_mov_b32 s0, 012; SI-NEXT: s_cbranch_scc1 .LBB0_213; SI-NEXT: ; %bb.1: ; %else14; SI-NEXT: s_mov_b32 s0, 115; SI-NEXT: .LBB0_2: ; %done16; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xb17; SI-NEXT: s_mov_b32 s7, 0xf00018; SI-NEXT: s_mov_b32 s6, -119; SI-NEXT: v_mov_b32_e32 v0, s020; SI-NEXT: s_waitcnt lgkmcnt(0)21; SI-NEXT: buffer_store_dword v0, off, s[4:7], 022; SI-NEXT: s_endpgm23;24; VI-LABEL: uniform_if_scc:25; VI: ; %bb.0: ; %entry26; VI-NEXT: s_load_dword s0, s[4:5], 0x2427; VI-NEXT: s_waitcnt lgkmcnt(0)28; VI-NEXT: s_cmp_eq_u32 s0, 029; VI-NEXT: s_mov_b32 s0, 030; VI-NEXT: s_cbranch_scc1 .LBB0_231; VI-NEXT: ; %bb.1: ; %else32; VI-NEXT: s_mov_b32 s0, 133; VI-NEXT: .LBB0_2: ; %done34; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c35; VI-NEXT: s_mov_b32 s7, 0xf00036; VI-NEXT: s_mov_b32 s6, -137; VI-NEXT: v_mov_b32_e32 v0, s038; VI-NEXT: s_waitcnt lgkmcnt(0)39; VI-NEXT: buffer_store_dword v0, off, s[4:7], 040; VI-NEXT: s_endpgm41entry:42 %cmp0 = icmp eq i32 %cond, 043 br i1 %cmp0, label %if, label %else44 45if:46 br label %done47 48else:49 br label %done50 51done:52 %value = phi i32 [0, %if], [1, %else]53 store i32 %value, ptr addrspace(1) %out54 ret void55}56 57define amdgpu_kernel void @uniform_if_vcc(float %cond, ptr addrspace(1) %out) {58; SI-LABEL: uniform_if_vcc:59; SI: ; %bb.0: ; %entry60; SI-NEXT: s_load_dword s1, s[4:5], 0x961; SI-NEXT: s_mov_b32 s0, 062; SI-NEXT: s_waitcnt lgkmcnt(0)63; SI-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, 064; SI-NEXT: s_and_b64 vcc, exec, s[2:3]65; SI-NEXT: s_cbranch_vccnz .LBB1_266; SI-NEXT: ; %bb.1: ; %else67; SI-NEXT: s_mov_b32 s0, 168; SI-NEXT: .LBB1_2: ; %done69; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xb70; SI-NEXT: s_mov_b32 s7, 0xf00071; SI-NEXT: s_mov_b32 s6, -172; SI-NEXT: v_mov_b32_e32 v0, s073; SI-NEXT: s_waitcnt lgkmcnt(0)74; SI-NEXT: buffer_store_dword v0, off, s[4:7], 075; SI-NEXT: s_endpgm76;77; VI-LABEL: uniform_if_vcc:78; VI: ; %bb.0: ; %entry79; VI-NEXT: s_load_dword s1, s[4:5], 0x2480; VI-NEXT: s_mov_b32 s0, 081; VI-NEXT: s_waitcnt lgkmcnt(0)82; VI-NEXT: v_cmp_eq_f32_e64 s[2:3], s1, 083; VI-NEXT: s_and_b64 vcc, exec, s[2:3]84; VI-NEXT: s_cbranch_vccnz .LBB1_285; VI-NEXT: ; %bb.1: ; %else86; VI-NEXT: s_mov_b32 s0, 187; VI-NEXT: .LBB1_2: ; %done88; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c89; VI-NEXT: s_mov_b32 s7, 0xf00090; VI-NEXT: s_mov_b32 s6, -191; VI-NEXT: v_mov_b32_e32 v0, s092; VI-NEXT: s_waitcnt lgkmcnt(0)93; VI-NEXT: buffer_store_dword v0, off, s[4:7], 094; VI-NEXT: s_endpgm95entry:96 %cmp0 = fcmp oeq float %cond, 0.097 br i1 %cmp0, label %if, label %else98 99if:100 br label %done101 102else:103 br label %done104 105done:106 %value = phi i32 [0, %if], [1, %else]107 store i32 %value, ptr addrspace(1) %out108 ret void109}110 111define amdgpu_kernel void @uniform_if_swap_br_targets_scc(i32 %cond, ptr addrspace(1) %out) {112; SI-LABEL: uniform_if_swap_br_targets_scc:113; SI: ; %bb.0: ; %entry114; SI-NEXT: s_load_dword s0, s[4:5], 0x9115; SI-NEXT: s_waitcnt lgkmcnt(0)116; SI-NEXT: s_cmp_lg_u32 s0, 0117; SI-NEXT: s_mov_b32 s0, 0118; SI-NEXT: s_cbranch_scc1 .LBB2_2119; SI-NEXT: ; %bb.1: ; %else120; SI-NEXT: s_mov_b32 s0, 1121; SI-NEXT: .LBB2_2: ; %done122; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xb123; SI-NEXT: s_mov_b32 s7, 0xf000124; SI-NEXT: s_mov_b32 s6, -1125; SI-NEXT: v_mov_b32_e32 v0, s0126; SI-NEXT: s_waitcnt lgkmcnt(0)127; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0128; SI-NEXT: s_endpgm129;130; VI-LABEL: uniform_if_swap_br_targets_scc:131; VI: ; %bb.0: ; %entry132; VI-NEXT: s_load_dword s0, s[4:5], 0x24133; VI-NEXT: s_waitcnt lgkmcnt(0)134; VI-NEXT: s_cmp_lg_u32 s0, 0135; VI-NEXT: s_mov_b32 s0, 0136; VI-NEXT: s_cbranch_scc1 .LBB2_2137; VI-NEXT: ; %bb.1: ; %else138; VI-NEXT: s_mov_b32 s0, 1139; VI-NEXT: .LBB2_2: ; %done140; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c141; VI-NEXT: s_mov_b32 s7, 0xf000142; VI-NEXT: s_mov_b32 s6, -1143; VI-NEXT: v_mov_b32_e32 v0, s0144; VI-NEXT: s_waitcnt lgkmcnt(0)145; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0146; VI-NEXT: s_endpgm147entry:148 %cmp0 = icmp eq i32 %cond, 0149 br i1 %cmp0, label %else, label %if150 151if:152 br label %done153 154else:155 br label %done156 157done:158 %value = phi i32 [0, %if], [1, %else]159 store i32 %value, ptr addrspace(1) %out160 ret void161}162 163define amdgpu_kernel void @uniform_if_swap_br_targets_vcc(float %cond, ptr addrspace(1) %out) {164; SI-LABEL: uniform_if_swap_br_targets_vcc:165; SI: ; %bb.0: ; %entry166; SI-NEXT: s_load_dword s1, s[4:5], 0x9167; SI-NEXT: s_mov_b32 s0, 0168; SI-NEXT: s_waitcnt lgkmcnt(0)169; SI-NEXT: v_cmp_neq_f32_e64 s[2:3], s1, 0170; SI-NEXT: s_and_b64 vcc, exec, s[2:3]171; SI-NEXT: s_cbranch_vccnz .LBB3_2172; SI-NEXT: ; %bb.1: ; %else173; SI-NEXT: s_mov_b32 s0, 1174; SI-NEXT: .LBB3_2: ; %done175; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xb176; SI-NEXT: s_mov_b32 s7, 0xf000177; SI-NEXT: s_mov_b32 s6, -1178; SI-NEXT: v_mov_b32_e32 v0, s0179; SI-NEXT: s_waitcnt lgkmcnt(0)180; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0181; SI-NEXT: s_endpgm182;183; VI-LABEL: uniform_if_swap_br_targets_vcc:184; VI: ; %bb.0: ; %entry185; VI-NEXT: s_load_dword s1, s[4:5], 0x24186; VI-NEXT: s_mov_b32 s0, 0187; VI-NEXT: s_waitcnt lgkmcnt(0)188; VI-NEXT: v_cmp_neq_f32_e64 s[2:3], s1, 0189; VI-NEXT: s_and_b64 vcc, exec, s[2:3]190; VI-NEXT: s_cbranch_vccnz .LBB3_2191; VI-NEXT: ; %bb.1: ; %else192; VI-NEXT: s_mov_b32 s0, 1193; VI-NEXT: .LBB3_2: ; %done194; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2c195; VI-NEXT: s_mov_b32 s7, 0xf000196; VI-NEXT: s_mov_b32 s6, -1197; VI-NEXT: v_mov_b32_e32 v0, s0198; VI-NEXT: s_waitcnt lgkmcnt(0)199; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0200; VI-NEXT: s_endpgm201entry:202 %cmp0 = fcmp oeq float %cond, 0.0203 br i1 %cmp0, label %else, label %if204 205if:206 br label %done207 208else:209 br label %done210 211done:212 %value = phi i32 [0, %if], [1, %else]213 store i32 %value, ptr addrspace(1) %out214 ret void215}216 217; Using a floating-point value in an integer compare will cause the compare to218; be selected for the SALU and then later moved to the VALU.219define amdgpu_kernel void @uniform_if_move_valu(ptr addrspace(1) %out, float %a) {220; SI-LABEL: uniform_if_move_valu:221; SI: ; %bb.0: ; %entry222; SI-NEXT: s_load_dword s0, s[4:5], 0xb223; SI-NEXT: v_mov_b32_e32 v0, 0x41200000224; SI-NEXT: s_waitcnt lgkmcnt(0)225; SI-NEXT: v_add_f32_e32 v0, s0, v0226; SI-NEXT: v_cmp_ne_u32_e32 vcc, 5, v0227; SI-NEXT: s_cbranch_vccnz .LBB4_2228; SI-NEXT: ; %bb.1: ; %if229; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9230; SI-NEXT: s_mov_b32 s3, 0xf000231; SI-NEXT: s_mov_b32 s2, -1232; SI-NEXT: v_mov_b32_e32 v0, 0233; SI-NEXT: s_waitcnt lgkmcnt(0)234; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0235; SI-NEXT: .LBB4_2: ; %endif236; SI-NEXT: s_endpgm237;238; VI-LABEL: uniform_if_move_valu:239; VI: ; %bb.0: ; %entry240; VI-NEXT: s_load_dword s0, s[4:5], 0x2c241; VI-NEXT: v_mov_b32_e32 v0, 0x41200000242; VI-NEXT: s_waitcnt lgkmcnt(0)243; VI-NEXT: v_add_f32_e32 v0, s0, v0244; VI-NEXT: v_cmp_ne_u32_e32 vcc, 5, v0245; VI-NEXT: s_cbranch_vccnz .LBB4_2246; VI-NEXT: ; %bb.1: ; %if247; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24248; VI-NEXT: s_mov_b32 s3, 0xf000249; VI-NEXT: s_mov_b32 s2, -1250; VI-NEXT: v_mov_b32_e32 v0, 0251; VI-NEXT: s_waitcnt lgkmcnt(0)252; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0253; VI-NEXT: .LBB4_2: ; %endif254; VI-NEXT: s_endpgm255entry:256 %a.0 = fadd float %a, 10.0257 %cond = bitcast float %a.0 to i32258 %cmp = icmp eq i32 %cond, 5259 br i1 %cmp, label %if, label %endif260 261if:262 store i32 0, ptr addrspace(1) %out263 br label %endif264 265endif:266 ret void267}268 269; Using a floating-point value in an integer compare will cause the compare to270; be selected for the SALU and then later moved to the VALU.271define amdgpu_kernel void @uniform_if_move_valu_commute(ptr addrspace(1) %out, float %a) {272; SI-LABEL: uniform_if_move_valu_commute:273; SI: ; %bb.0: ; %entry274; SI-NEXT: s_load_dword s0, s[4:5], 0xb275; SI-NEXT: v_mov_b32_e32 v0, 0x41200000276; SI-NEXT: s_waitcnt lgkmcnt(0)277; SI-NEXT: v_add_f32_e32 v0, s0, v0278; SI-NEXT: v_cmp_gt_u32_e32 vcc, 6, v0279; SI-NEXT: s_cbranch_vccnz .LBB5_2280; SI-NEXT: ; %bb.1: ; %if281; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9282; SI-NEXT: s_mov_b32 s3, 0xf000283; SI-NEXT: s_mov_b32 s2, -1284; SI-NEXT: v_mov_b32_e32 v0, 0285; SI-NEXT: s_waitcnt lgkmcnt(0)286; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0287; SI-NEXT: .LBB5_2: ; %endif288; SI-NEXT: s_endpgm289;290; VI-LABEL: uniform_if_move_valu_commute:291; VI: ; %bb.0: ; %entry292; VI-NEXT: s_load_dword s0, s[4:5], 0x2c293; VI-NEXT: v_mov_b32_e32 v0, 0x41200000294; VI-NEXT: s_waitcnt lgkmcnt(0)295; VI-NEXT: v_add_f32_e32 v0, s0, v0296; VI-NEXT: v_cmp_gt_u32_e32 vcc, 6, v0297; VI-NEXT: s_cbranch_vccnz .LBB5_2298; VI-NEXT: ; %bb.1: ; %if299; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24300; VI-NEXT: s_mov_b32 s3, 0xf000301; VI-NEXT: s_mov_b32 s2, -1302; VI-NEXT: v_mov_b32_e32 v0, 0303; VI-NEXT: s_waitcnt lgkmcnt(0)304; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0305; VI-NEXT: .LBB5_2: ; %endif306; VI-NEXT: s_endpgm307entry:308 %a.0 = fadd float %a, 10.0309 %cond = bitcast float %a.0 to i32310 %cmp = icmp ugt i32 %cond, 5311 br i1 %cmp, label %if, label %endif312 313if:314 store i32 0, ptr addrspace(1) %out315 br label %endif316 317endif:318 ret void319}320 321 322define amdgpu_kernel void @uniform_if_else_ret(ptr addrspace(1) nocapture %out, i32 %a) {323; SI-LABEL: uniform_if_else_ret:324; SI: ; %bb.0: ; %entry325; SI-NEXT: s_load_dword s2, s[4:5], 0xb326; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9327; SI-NEXT: s_mov_b32 s3, 0xf000328; SI-NEXT: s_waitcnt lgkmcnt(0)329; SI-NEXT: s_cmp_lg_u32 s2, 0330; SI-NEXT: s_cbranch_scc0 .LBB6_2331; SI-NEXT: ; %bb.1: ; %if.else332; SI-NEXT: s_mov_b32 s2, -1333; SI-NEXT: v_mov_b32_e32 v0, 2334; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0335; SI-NEXT: s_endpgm336; SI-NEXT: .LBB6_2: ; %if.then337; SI-NEXT: s_mov_b32 s2, -1338; SI-NEXT: v_mov_b32_e32 v0, 1339; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0340; SI-NEXT: s_endpgm341;342; VI-LABEL: uniform_if_else_ret:343; VI: ; %bb.0: ; %entry344; VI-NEXT: s_load_dword s2, s[4:5], 0x2c345; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24346; VI-NEXT: s_mov_b32 s3, 0xf000347; VI-NEXT: s_waitcnt lgkmcnt(0)348; VI-NEXT: s_cmp_lg_u32 s2, 0349; VI-NEXT: s_cbranch_scc0 .LBB6_2350; VI-NEXT: ; %bb.1: ; %if.else351; VI-NEXT: s_mov_b32 s2, -1352; VI-NEXT: v_mov_b32_e32 v0, 2353; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0354; VI-NEXT: s_endpgm355; VI-NEXT: .LBB6_2: ; %if.then356; VI-NEXT: s_mov_b32 s2, -1357; VI-NEXT: v_mov_b32_e32 v0, 1358; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0359; VI-NEXT: s_endpgm360entry:361 %cmp = icmp eq i32 %a, 0362 br i1 %cmp, label %if.then, label %if.else363 364if.then: ; preds = %entry365 store i32 1, ptr addrspace(1) %out366 br label %if.end367 368if.else: ; preds = %entry369 store i32 2, ptr addrspace(1) %out370 br label %if.end371 372if.end: ; preds = %if.else, %if.then373 ret void374}375 376define amdgpu_kernel void @uniform_if_else(ptr addrspace(1) nocapture %out0, ptr addrspace(1) nocapture %out1, i32 %a) {377; SI-LABEL: uniform_if_else:378; SI: ; %bb.0: ; %entry379; SI-NEXT: s_load_dword s6, s[4:5], 0xd380; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9381; SI-NEXT: s_mov_b32 s7, 0xf000382; SI-NEXT: s_waitcnt lgkmcnt(0)383; SI-NEXT: s_cmp_lg_u32 s6, 0384; SI-NEXT: s_cbranch_scc0 .LBB7_2385; SI-NEXT: ; %bb.1: ; %if.else386; SI-NEXT: s_mov_b32 s6, -1387; SI-NEXT: s_mov_b32 s4, s0388; SI-NEXT: s_mov_b32 s5, s1389; SI-NEXT: v_mov_b32_e32 v0, 2390; SI-NEXT: s_branch .LBB7_3391; SI-NEXT: .LBB7_2: ; %if.then392; SI-NEXT: s_mov_b32 s6, -1393; SI-NEXT: s_mov_b32 s4, s0394; SI-NEXT: s_mov_b32 s5, s1395; SI-NEXT: v_mov_b32_e32 v0, 1396; SI-NEXT: .LBB7_3: ; %if.end397; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0398; SI-NEXT: s_mov_b32 s4, s2399; SI-NEXT: s_mov_b32 s5, s3400; SI-NEXT: s_waitcnt expcnt(0)401; SI-NEXT: v_mov_b32_e32 v0, 3402; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0403; SI-NEXT: s_endpgm404;405; VI-LABEL: uniform_if_else:406; VI: ; %bb.0: ; %entry407; VI-NEXT: s_load_dword s6, s[4:5], 0x34408; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24409; VI-NEXT: s_mov_b32 s7, 0xf000410; VI-NEXT: s_waitcnt lgkmcnt(0)411; VI-NEXT: s_cmp_lg_u32 s6, 0412; VI-NEXT: s_cbranch_scc0 .LBB7_2413; VI-NEXT: ; %bb.1: ; %if.else414; VI-NEXT: s_mov_b32 s6, -1415; VI-NEXT: s_mov_b32 s4, s0416; VI-NEXT: s_mov_b32 s5, s1417; VI-NEXT: v_mov_b32_e32 v0, 2418; VI-NEXT: s_branch .LBB7_3419; VI-NEXT: .LBB7_2: ; %if.then420; VI-NEXT: s_mov_b32 s6, -1421; VI-NEXT: s_mov_b32 s4, s0422; VI-NEXT: s_mov_b32 s5, s1423; VI-NEXT: v_mov_b32_e32 v0, 1424; VI-NEXT: .LBB7_3: ; %if.end425; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0426; VI-NEXT: s_mov_b32 s4, s2427; VI-NEXT: s_mov_b32 s5, s3428; VI-NEXT: v_mov_b32_e32 v0, 3429; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0430; VI-NEXT: s_endpgm431entry:432 %cmp = icmp eq i32 %a, 0433 br i1 %cmp, label %if.then, label %if.else434 435if.then: ; preds = %entry436 store i32 1, ptr addrspace(1) %out0437 br label %if.end438 439if.else: ; preds = %entry440 store i32 2, ptr addrspace(1) %out0441 br label %if.end442 443if.end: ; preds = %if.else, %if.then444 store i32 3, ptr addrspace(1) %out1445 ret void446}447 448define amdgpu_kernel void @icmp_2_users(ptr addrspace(1) %out, i32 %cond) {449; SI-LABEL: icmp_2_users:450; SI: ; %bb.0: ; %main_body451; SI-NEXT: s_load_dword s2, s[4:5], 0xb452; SI-NEXT: s_waitcnt lgkmcnt(0)453; SI-NEXT: s_cmp_gt_i32 s2, 0454; SI-NEXT: s_cselect_b64 s[0:1], -1, 0455; SI-NEXT: s_cmp_lt_i32 s2, 1456; SI-NEXT: s_cbranch_scc1 .LBB8_2457; SI-NEXT: ; %bb.1: ; %IF458; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9459; SI-NEXT: s_mov_b32 s7, 0xf000460; SI-NEXT: s_mov_b32 s6, -1461; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]462; SI-NEXT: s_waitcnt lgkmcnt(0)463; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0464; SI-NEXT: .LBB8_2: ; %ENDIF465; SI-NEXT: s_endpgm466;467; VI-LABEL: icmp_2_users:468; VI: ; %bb.0: ; %main_body469; VI-NEXT: s_load_dword s2, s[4:5], 0x2c470; VI-NEXT: s_waitcnt lgkmcnt(0)471; VI-NEXT: s_cmp_gt_i32 s2, 0472; VI-NEXT: s_cselect_b64 s[0:1], -1, 0473; VI-NEXT: s_cmp_lt_i32 s2, 1474; VI-NEXT: s_cbranch_scc1 .LBB8_2475; VI-NEXT: ; %bb.1: ; %IF476; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24477; VI-NEXT: s_mov_b32 s7, 0xf000478; VI-NEXT: s_mov_b32 s6, -1479; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]480; VI-NEXT: s_waitcnt lgkmcnt(0)481; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0482; VI-NEXT: .LBB8_2: ; %ENDIF483; VI-NEXT: s_endpgm484main_body:485 %0 = icmp sgt i32 %cond, 0486 %1 = sext i1 %0 to i32487 br i1 %0, label %IF, label %ENDIF488 489IF:490 store i32 %1, ptr addrspace(1) %out491 br label %ENDIF492 493ENDIF: ; preds = %IF, %main_body494 ret void495}496 497define amdgpu_kernel void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, ptr addrspace(1) %out) {498; SI-LABEL: icmp_users_different_blocks:499; SI: ; %bb.0: ; %bb500; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9501; SI-NEXT: s_waitcnt lgkmcnt(0)502; SI-NEXT: s_cmp_lt_i32 s0, 1503; SI-NEXT: s_cbranch_scc1 .LBB9_2504; SI-NEXT: ; %bb.1: ; %bb2505; SI-NEXT: s_cmp_gt_i32 s1, 0506; SI-NEXT: s_cselect_b64 s[0:1], -1, 0507; SI-NEXT: s_and_b64 vcc, exec, s[0:1]508; SI-NEXT: s_cbranch_vccz .LBB9_3509; SI-NEXT: .LBB9_2: ; %bb9510; SI-NEXT: s_endpgm511; SI-NEXT: .LBB9_3: ; %bb7512; SI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]513; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb514; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1515; SI-NEXT: s_mov_b32 s3, 0xf000516; SI-NEXT: s_mov_b32 s2, -1517; SI-NEXT: s_waitcnt lgkmcnt(0)518; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0519; SI-NEXT: s_endpgm520;521; VI-LABEL: icmp_users_different_blocks:522; VI: ; %bb.0: ; %bb523; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24524; VI-NEXT: s_waitcnt lgkmcnt(0)525; VI-NEXT: s_cmp_lt_i32 s0, 1526; VI-NEXT: s_cbranch_scc1 .LBB9_2527; VI-NEXT: ; %bb.1: ; %bb2528; VI-NEXT: s_cmp_gt_i32 s1, 0529; VI-NEXT: s_cselect_b64 s[0:1], -1, 0530; VI-NEXT: s_and_b64 vcc, exec, s[0:1]531; VI-NEXT: s_cbranch_vccz .LBB9_3532; VI-NEXT: .LBB9_2: ; %bb9533; VI-NEXT: s_endpgm534; VI-NEXT: .LBB9_3: ; %bb7535; VI-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]536; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c537; VI-NEXT: v_sub_u32_e32 v0, vcc, v0, v1538; VI-NEXT: s_mov_b32 s3, 0xf000539; VI-NEXT: s_mov_b32 s2, -1540; VI-NEXT: s_waitcnt lgkmcnt(0)541; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0542; VI-NEXT: s_endpgm543bb:544 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0545 %cmp0 = icmp sgt i32 %cond0, 0546 br i1 %cmp0, label %bb2, label %bb9547 548bb2: ; preds = %bb549 %cmp1 = icmp sgt i32 %cond1, 0550 %tmp2 = sext i1 %cmp1 to i32551 %tmp3 = add i32 %tmp2, %tmp552 br i1 %cmp1, label %bb9, label %bb7553 554bb7: ; preds = %bb5555 store i32 %tmp3, ptr addrspace(1) %out556 br label %bb9557 558bb9: ; preds = %bb8, %bb4559 ret void560}561 562define amdgpu_kernel void @uniform_loop(ptr addrspace(1) %out, i32 %a) {563; SI-LABEL: uniform_loop:564; SI: ; %bb.0: ; %entry565; SI-NEXT: s_load_dword s0, s[4:5], 0xb566; SI-NEXT: .LBB10_1: ; %loop567; SI-NEXT: ; =>This Inner Loop Header: Depth=1568; SI-NEXT: s_waitcnt lgkmcnt(0)569; SI-NEXT: s_add_i32 s0, s0, -1570; SI-NEXT: s_cmp_lg_u32 s0, 0571; SI-NEXT: s_cbranch_scc1 .LBB10_1572; SI-NEXT: ; %bb.2: ; %done573; SI-NEXT: s_endpgm574;575; VI-LABEL: uniform_loop:576; VI: ; %bb.0: ; %entry577; VI-NEXT: s_load_dword s0, s[4:5], 0x2c578; VI-NEXT: .LBB10_1: ; %loop579; VI-NEXT: ; =>This Inner Loop Header: Depth=1580; VI-NEXT: s_waitcnt lgkmcnt(0)581; VI-NEXT: s_add_i32 s0, s0, -1582; VI-NEXT: s_cmp_lg_u32 s0, 0583; VI-NEXT: s_cbranch_scc1 .LBB10_1584; VI-NEXT: ; %bb.2: ; %done585; VI-NEXT: s_endpgm586entry:587 br label %loop588 589loop:590 %i = phi i32 [0, %entry], [%i.i, %loop]591 %i.i = add i32 %i, 1592 %cmp = icmp eq i32 %a, %i.i593 br i1 %cmp, label %done, label %loop594 595done:596 ret void597}598 599; Test uniform and divergent.600 601define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 %cond) {602; SI-LABEL: uniform_inside_divergent:603; SI: ; %bb.0: ; %entry604; SI-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0605; SI-NEXT: s_and_saveexec_b64 s[0:1], vcc606; SI-NEXT: s_cbranch_execz .LBB11_2607; SI-NEXT: ; %bb.1: ; %if608; SI-NEXT: s_load_dword s6, s[4:5], 0xb609; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9610; SI-NEXT: s_mov_b32 s3, 0xf000611; SI-NEXT: s_mov_b32 s2, -1612; SI-NEXT: v_mov_b32_e32 v0, 0613; SI-NEXT: s_waitcnt lgkmcnt(0)614; SI-NEXT: s_cmp_lg_u32 s6, 0615; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0616; SI-NEXT: s_cbranch_scc0 .LBB11_3617; SI-NEXT: .LBB11_2: ; %endif618; SI-NEXT: s_endpgm619; SI-NEXT: .LBB11_3: ; %if_uniform620; SI-NEXT: s_waitcnt expcnt(0)621; SI-NEXT: v_mov_b32_e32 v0, 1622; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0623; SI-NEXT: s_endpgm624;625; VI-LABEL: uniform_inside_divergent:626; VI: ; %bb.0: ; %entry627; VI-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0628; VI-NEXT: s_and_saveexec_b64 s[0:1], vcc629; VI-NEXT: s_cbranch_execz .LBB11_2630; VI-NEXT: ; %bb.1: ; %if631; VI-NEXT: s_load_dword s6, s[4:5], 0x2c632; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24633; VI-NEXT: s_mov_b32 s3, 0xf000634; VI-NEXT: s_mov_b32 s2, -1635; VI-NEXT: v_mov_b32_e32 v0, 0636; VI-NEXT: s_waitcnt lgkmcnt(0)637; VI-NEXT: s_cmp_lg_u32 s6, 0638; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0639; VI-NEXT: s_cbranch_scc0 .LBB11_3640; VI-NEXT: .LBB11_2: ; %endif641; VI-NEXT: s_endpgm642; VI-NEXT: .LBB11_3: ; %if_uniform643; VI-NEXT: v_mov_b32_e32 v0, 1644; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0645; VI-NEXT: s_endpgm646entry:647 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0648 %d_cmp = icmp ult i32 %tid, 16649 br i1 %d_cmp, label %if, label %endif650 651if:652 store i32 0, ptr addrspace(1) %out653 %u_cmp = icmp eq i32 %cond, 0654 br i1 %u_cmp, label %if_uniform, label %endif655 656if_uniform:657 store i32 1, ptr addrspace(1) %out658 br label %endif659 660endif:661 ret void662}663 664define amdgpu_kernel void @divergent_inside_uniform(ptr addrspace(1) %out, i32 %cond) {665; SI-LABEL: divergent_inside_uniform:666; SI: ; %bb.0: ; %entry667; SI-NEXT: s_load_dword s0, s[4:5], 0xb668; SI-NEXT: s_waitcnt lgkmcnt(0)669; SI-NEXT: s_cmp_lg_u32 s0, 0670; SI-NEXT: s_cbranch_scc0 .LBB12_2671; SI-NEXT: .LBB12_1: ; %endif672; SI-NEXT: s_endpgm673; SI-NEXT: .LBB12_2: ; %if674; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9675; SI-NEXT: s_mov_b32 s3, 0xf000676; SI-NEXT: s_mov_b32 s2, -1677; SI-NEXT: v_mov_b32_e32 v1, 0678; SI-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0679; SI-NEXT: s_waitcnt lgkmcnt(0)680; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0681; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc682; SI-NEXT: s_cbranch_execz .LBB12_1683; SI-NEXT: ; %bb.3: ; %if_uniform684; SI-NEXT: v_mov_b32_e32 v0, 1685; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0686; SI-NEXT: s_endpgm687;688; VI-LABEL: divergent_inside_uniform:689; VI: ; %bb.0: ; %entry690; VI-NEXT: s_load_dword s0, s[4:5], 0x2c691; VI-NEXT: s_waitcnt lgkmcnt(0)692; VI-NEXT: s_cmp_lg_u32 s0, 0693; VI-NEXT: s_cbranch_scc0 .LBB12_2694; VI-NEXT: .LBB12_1: ; %endif695; VI-NEXT: s_endpgm696; VI-NEXT: .LBB12_2: ; %if697; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24698; VI-NEXT: s_mov_b32 s3, 0xf000699; VI-NEXT: s_mov_b32 s2, -1700; VI-NEXT: v_mov_b32_e32 v1, 0701; VI-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0702; VI-NEXT: s_waitcnt lgkmcnt(0)703; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0704; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc705; VI-NEXT: s_cbranch_execz .LBB12_1706; VI-NEXT: ; %bb.3: ; %if_uniform707; VI-NEXT: v_mov_b32_e32 v0, 1708; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0709; VI-NEXT: s_endpgm710entry:711 %u_cmp = icmp eq i32 %cond, 0712 br i1 %u_cmp, label %if, label %endif713 714if:715 store i32 0, ptr addrspace(1) %out716 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0717 %d_cmp = icmp ult i32 %tid, 16718 br i1 %d_cmp, label %if_uniform, label %endif719 720if_uniform:721 store i32 1, ptr addrspace(1) %out722 br label %endif723 724endif:725 ret void726}727 728define amdgpu_kernel void @divergent_if_uniform_if(ptr addrspace(1) %out, i32 %cond) {729; SI-LABEL: divergent_if_uniform_if:730; SI: ; %bb.0: ; %entry731; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9732; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0733; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc734; SI-NEXT: s_cbranch_execz .LBB13_2735; SI-NEXT: ; %bb.1: ; %if736; SI-NEXT: s_mov_b32 s3, 0xf000737; SI-NEXT: s_mov_b32 s2, -1738; SI-NEXT: v_mov_b32_e32 v0, 1739; SI-NEXT: s_waitcnt lgkmcnt(0)740; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0741; SI-NEXT: .LBB13_2: ; %endif742; SI-NEXT: s_or_b64 exec, exec, s[6:7]743; SI-NEXT: s_load_dword s2, s[4:5], 0xb744; SI-NEXT: s_waitcnt lgkmcnt(0)745; SI-NEXT: s_cmp_lg_u32 s2, 0746; SI-NEXT: s_cbranch_scc0 .LBB13_4747; SI-NEXT: ; %bb.3: ; %exit748; SI-NEXT: s_endpgm749; SI-NEXT: .LBB13_4: ; %if_uniform750; SI-NEXT: s_mov_b32 s3, 0xf000751; SI-NEXT: s_mov_b32 s2, -1752; SI-NEXT: s_waitcnt expcnt(0)753; SI-NEXT: v_mov_b32_e32 v0, 2754; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0755; SI-NEXT: s_endpgm756;757; VI-LABEL: divergent_if_uniform_if:758; VI: ; %bb.0: ; %entry759; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24760; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0761; VI-NEXT: s_and_saveexec_b64 s[6:7], vcc762; VI-NEXT: s_cbranch_execz .LBB13_2763; VI-NEXT: ; %bb.1: ; %if764; VI-NEXT: s_mov_b32 s3, 0xf000765; VI-NEXT: s_mov_b32 s2, -1766; VI-NEXT: v_mov_b32_e32 v0, 1767; VI-NEXT: s_waitcnt lgkmcnt(0)768; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0769; VI-NEXT: .LBB13_2: ; %endif770; VI-NEXT: s_or_b64 exec, exec, s[6:7]771; VI-NEXT: s_load_dword s2, s[4:5], 0x2c772; VI-NEXT: s_waitcnt lgkmcnt(0)773; VI-NEXT: s_cmp_lg_u32 s2, 0774; VI-NEXT: s_cbranch_scc0 .LBB13_4775; VI-NEXT: ; %bb.3: ; %exit776; VI-NEXT: s_endpgm777; VI-NEXT: .LBB13_4: ; %if_uniform778; VI-NEXT: s_mov_b32 s3, 0xf000779; VI-NEXT: s_mov_b32 s2, -1780; VI-NEXT: v_mov_b32_e32 v0, 2781; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0782; VI-NEXT: s_endpgm783entry:784 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0785 %d_cmp = icmp eq i32 %tid, 0786 br i1 %d_cmp, label %if, label %endif787 788if:789 store i32 1, ptr addrspace(1) %out790 br label %endif791 792endif:793 %u_cmp = icmp eq i32 %cond, 0794 br i1 %u_cmp, label %if_uniform, label %exit795 796if_uniform:797 store i32 2, ptr addrspace(1) %out798 br label %exit799 800exit:801 ret void802}803 804; The condition of the branches in the two blocks are805; uniform. MachineCSE replaces the 2nd condition with the inverse of806; the first, leaving an scc use in a different block than it was807; defed.808 809define amdgpu_kernel void @cse_uniform_condition_different_blocks(i32 %cond, ptr addrspace(1) %out) {810; SI-LABEL: cse_uniform_condition_different_blocks:811; SI: ; %bb.0: ; %bb812; SI-NEXT: s_load_dword s0, s[4:5], 0x9813; SI-NEXT: s_waitcnt lgkmcnt(0)814; SI-NEXT: s_cmp_lt_i32 s0, 1815; SI-NEXT: s_cbranch_scc1 .LBB14_2816; SI-NEXT: ; %bb.1: ; %bb2817; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb818; SI-NEXT: s_mov_b32 s3, 0xf000819; SI-NEXT: s_mov_b32 s2, -1820; SI-NEXT: v_mov_b32_e32 v1, 0821; SI-NEXT: s_waitcnt lgkmcnt(0)822; SI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc823; SI-NEXT: s_waitcnt vmcnt(0)824; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0825; SI-NEXT: s_waitcnt vmcnt(0)826; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0827; SI-NEXT: .LBB14_2: ; %bb9828; SI-NEXT: s_endpgm829;830; VI-LABEL: cse_uniform_condition_different_blocks:831; VI: ; %bb.0: ; %bb832; VI-NEXT: s_load_dword s0, s[4:5], 0x24833; VI-NEXT: s_waitcnt lgkmcnt(0)834; VI-NEXT: s_cmp_lt_i32 s0, 1835; VI-NEXT: s_cbranch_scc1 .LBB14_2836; VI-NEXT: ; %bb.1: ; %bb2837; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c838; VI-NEXT: s_mov_b32 s3, 0xf000839; VI-NEXT: s_mov_b32 s2, -1840; VI-NEXT: v_mov_b32_e32 v1, 0841; VI-NEXT: s_waitcnt lgkmcnt(0)842; VI-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc843; VI-NEXT: s_waitcnt vmcnt(0)844; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0845; VI-NEXT: s_waitcnt vmcnt(0)846; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0847; VI-NEXT: .LBB14_2: ; %bb9848; VI-NEXT: s_endpgm849bb:850 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0851 %tmp1 = icmp sgt i32 %cond, 0852 br i1 %tmp1, label %bb2, label %bb9853 854bb2: ; preds = %bb855 %tmp3 = load volatile i32, ptr addrspace(1) poison856 store volatile i32 0, ptr addrspace(1) poison857 %tmp9 = icmp sle i32 %cond, 0858 br i1 %tmp9, label %bb9, label %bb7859 860bb7: ; preds = %bb5861 store i32 %tmp3, ptr addrspace(1) %out862 br label %bb9863 864bb9: ; preds = %bb8, %bb4865 ret void866}867 868; Fall-through to the else869define amdgpu_kernel void @uniform_if_scc_i64_eq(i64 %cond, ptr addrspace(1) %out) {870; SI-LABEL: uniform_if_scc_i64_eq:871; SI: ; %bb.0: ; %entry872; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9873; SI-NEXT: s_waitcnt lgkmcnt(0)874; SI-NEXT: v_cmp_eq_u64_e64 s[4:5], s[0:1], 0875; SI-NEXT: s_mov_b32 s0, 0876; SI-NEXT: s_and_b64 vcc, exec, s[4:5]877; SI-NEXT: s_cbranch_vccnz .LBB15_2878; SI-NEXT: ; %bb.1: ; %else879; SI-NEXT: s_mov_b32 s0, 1880; SI-NEXT: .LBB15_2: ; %done881; SI-NEXT: s_mov_b32 s7, 0xf000882; SI-NEXT: s_mov_b32 s6, -1883; SI-NEXT: s_mov_b32 s4, s2884; SI-NEXT: s_mov_b32 s5, s3885; SI-NEXT: v_mov_b32_e32 v0, s0886; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0887; SI-NEXT: s_endpgm888;889; VI-LABEL: uniform_if_scc_i64_eq:890; VI: ; %bb.0: ; %entry891; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24892; VI-NEXT: s_waitcnt lgkmcnt(0)893; VI-NEXT: s_cmp_eq_u64 s[0:1], 0894; VI-NEXT: s_mov_b32 s0, 0895; VI-NEXT: s_cbranch_scc1 .LBB15_2896; VI-NEXT: ; %bb.1: ; %else897; VI-NEXT: s_mov_b32 s0, 1898; VI-NEXT: .LBB15_2: ; %done899; VI-NEXT: s_mov_b32 s7, 0xf000900; VI-NEXT: s_mov_b32 s6, -1901; VI-NEXT: s_mov_b32 s4, s2902; VI-NEXT: s_mov_b32 s5, s3903; VI-NEXT: v_mov_b32_e32 v0, s0904; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0905; VI-NEXT: s_endpgm906entry:907 %cmp0 = icmp eq i64 %cond, 0908 br i1 %cmp0, label %if, label %else909 910if:911 br label %done912 913else:914 br label %done915 916done:917 %value = phi i32 [0, %if], [1, %else]918 store i32 %value, ptr addrspace(1) %out919 ret void920}921 922; Fall-through to the else923define amdgpu_kernel void @uniform_if_scc_i64_ne(i64 %cond, ptr addrspace(1) %out) {924; SI-LABEL: uniform_if_scc_i64_ne:925; SI: ; %bb.0: ; %entry926; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9927; SI-NEXT: s_waitcnt lgkmcnt(0)928; SI-NEXT: v_cmp_ne_u64_e64 s[4:5], s[0:1], 0929; SI-NEXT: s_mov_b32 s0, 0930; SI-NEXT: s_and_b64 vcc, exec, s[4:5]931; SI-NEXT: s_cbranch_vccnz .LBB16_2932; SI-NEXT: ; %bb.1: ; %else933; SI-NEXT: s_mov_b32 s0, 1934; SI-NEXT: .LBB16_2: ; %done935; SI-NEXT: s_mov_b32 s7, 0xf000936; SI-NEXT: s_mov_b32 s6, -1937; SI-NEXT: s_mov_b32 s4, s2938; SI-NEXT: s_mov_b32 s5, s3939; SI-NEXT: v_mov_b32_e32 v0, s0940; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0941; SI-NEXT: s_endpgm942;943; VI-LABEL: uniform_if_scc_i64_ne:944; VI: ; %bb.0: ; %entry945; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24946; VI-NEXT: s_waitcnt lgkmcnt(0)947; VI-NEXT: s_cmp_lg_u64 s[0:1], 0948; VI-NEXT: s_mov_b32 s0, 0949; VI-NEXT: s_cbranch_scc1 .LBB16_2950; VI-NEXT: ; %bb.1: ; %else951; VI-NEXT: s_mov_b32 s0, 1952; VI-NEXT: .LBB16_2: ; %done953; VI-NEXT: s_mov_b32 s7, 0xf000954; VI-NEXT: s_mov_b32 s6, -1955; VI-NEXT: s_mov_b32 s4, s2956; VI-NEXT: s_mov_b32 s5, s3957; VI-NEXT: v_mov_b32_e32 v0, s0958; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0959; VI-NEXT: s_endpgm960entry:961 %cmp0 = icmp ne i64 %cond, 0962 br i1 %cmp0, label %if, label %else963 964if:965 br label %done966 967else:968 br label %done969 970done:971 %value = phi i32 [0, %if], [1, %else]972 store i32 %value, ptr addrspace(1) %out973 ret void974}975 976; Fall-through to the else977define amdgpu_kernel void @uniform_if_scc_i64_sgt(i64 %cond, ptr addrspace(1) %out) {978; SI-LABEL: uniform_if_scc_i64_sgt:979; SI: ; %bb.0: ; %entry980; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9981; SI-NEXT: s_waitcnt lgkmcnt(0)982; SI-NEXT: v_cmp_gt_i64_e64 s[4:5], s[0:1], 0983; SI-NEXT: s_mov_b32 s0, 0984; SI-NEXT: s_and_b64 vcc, exec, s[4:5]985; SI-NEXT: s_cbranch_vccnz .LBB17_2986; SI-NEXT: ; %bb.1: ; %else987; SI-NEXT: s_mov_b32 s0, 1988; SI-NEXT: .LBB17_2: ; %done989; SI-NEXT: s_mov_b32 s7, 0xf000990; SI-NEXT: s_mov_b32 s6, -1991; SI-NEXT: s_mov_b32 s4, s2992; SI-NEXT: s_mov_b32 s5, s3993; SI-NEXT: v_mov_b32_e32 v0, s0994; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0995; SI-NEXT: s_endpgm996;997; VI-LABEL: uniform_if_scc_i64_sgt:998; VI: ; %bb.0: ; %entry999; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241000; VI-NEXT: s_waitcnt lgkmcnt(0)1001; VI-NEXT: v_cmp_gt_i64_e64 s[4:5], s[0:1], 01002; VI-NEXT: s_mov_b32 s0, 01003; VI-NEXT: s_and_b64 vcc, exec, s[4:5]1004; VI-NEXT: s_cbranch_vccnz .LBB17_21005; VI-NEXT: ; %bb.1: ; %else1006; VI-NEXT: s_mov_b32 s0, 11007; VI-NEXT: .LBB17_2: ; %done1008; VI-NEXT: s_mov_b32 s7, 0xf0001009; VI-NEXT: s_mov_b32 s6, -11010; VI-NEXT: s_mov_b32 s4, s21011; VI-NEXT: s_mov_b32 s5, s31012; VI-NEXT: v_mov_b32_e32 v0, s01013; VI-NEXT: buffer_store_dword v0, off, s[4:7], 01014; VI-NEXT: s_endpgm1015entry:1016 %cmp0 = icmp sgt i64 %cond, 01017 br i1 %cmp0, label %if, label %else1018 1019if:1020 br label %done1021 1022else:1023 br label %done1024 1025done:1026 %value = phi i32 [0, %if], [1, %else]1027 store i32 %value, ptr addrspace(1) %out1028 ret void1029}1030 1031define amdgpu_kernel void @move_to_valu_i64_eq(ptr addrspace(1) %out) {1032; SI-LABEL: move_to_valu_i64_eq:1033; SI: ; %bb.0:1034; SI-NEXT: s_mov_b32 m0, -11035; SI-NEXT: ds_read_b64 v[0:1], v01036; SI-NEXT: s_mov_b32 s0, 01037; SI-NEXT: s_waitcnt lgkmcnt(0)1038; SI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]1039; SI-NEXT: s_cbranch_vccnz .LBB18_21040; SI-NEXT: ; %bb.1: ; %else1041; SI-NEXT: s_mov_b32 s0, 11042; SI-NEXT: .LBB18_2: ; %done1043; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91044; SI-NEXT: s_mov_b32 s7, 0xf0001045; SI-NEXT: s_mov_b32 s6, -11046; SI-NEXT: v_mov_b32_e32 v0, s01047; SI-NEXT: s_waitcnt lgkmcnt(0)1048; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01049; SI-NEXT: s_endpgm1050;1051; VI-LABEL: move_to_valu_i64_eq:1052; VI: ; %bb.0:1053; VI-NEXT: s_mov_b32 m0, -11054; VI-NEXT: ds_read_b64 v[0:1], v01055; VI-NEXT: s_mov_b32 s0, 01056; VI-NEXT: s_waitcnt lgkmcnt(0)1057; VI-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]1058; VI-NEXT: s_cbranch_vccnz .LBB18_21059; VI-NEXT: ; %bb.1: ; %else1060; VI-NEXT: s_mov_b32 s0, 11061; VI-NEXT: .LBB18_2: ; %done1062; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241063; VI-NEXT: s_mov_b32 s7, 0xf0001064; VI-NEXT: s_mov_b32 s6, -11065; VI-NEXT: v_mov_b32_e32 v0, s01066; VI-NEXT: s_waitcnt lgkmcnt(0)1067; VI-NEXT: buffer_store_dword v0, off, s[4:7], 01068; VI-NEXT: s_endpgm1069 %cond = load volatile i64, ptr addrspace(3) poison1070 %cmp0 = icmp eq i64 %cond, 01071 br i1 %cmp0, label %if, label %else1072 1073if:1074 br label %done1075 1076else:1077 br label %done1078 1079done:1080 %value = phi i32 [0, %if], [1, %else]1081 store i32 %value, ptr addrspace(1) %out1082 ret void1083}1084 1085define amdgpu_kernel void @move_to_valu_i64_ne(ptr addrspace(1) %out) {1086; SI-LABEL: move_to_valu_i64_ne:1087; SI: ; %bb.0:1088; SI-NEXT: s_mov_b32 m0, -11089; SI-NEXT: ds_read_b64 v[0:1], v01090; SI-NEXT: s_mov_b32 s0, 01091; SI-NEXT: s_waitcnt lgkmcnt(0)1092; SI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]1093; SI-NEXT: s_cbranch_vccnz .LBB19_21094; SI-NEXT: ; %bb.1: ; %else1095; SI-NEXT: s_mov_b32 s0, 11096; SI-NEXT: .LBB19_2: ; %done1097; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x91098; SI-NEXT: s_mov_b32 s7, 0xf0001099; SI-NEXT: s_mov_b32 s6, -11100; SI-NEXT: v_mov_b32_e32 v0, s01101; SI-NEXT: s_waitcnt lgkmcnt(0)1102; SI-NEXT: buffer_store_dword v0, off, s[4:7], 01103; SI-NEXT: s_endpgm1104;1105; VI-LABEL: move_to_valu_i64_ne:1106; VI: ; %bb.0:1107; VI-NEXT: s_mov_b32 m0, -11108; VI-NEXT: ds_read_b64 v[0:1], v01109; VI-NEXT: s_mov_b32 s0, 01110; VI-NEXT: s_waitcnt lgkmcnt(0)1111; VI-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1]1112; VI-NEXT: s_cbranch_vccnz .LBB19_21113; VI-NEXT: ; %bb.1: ; %else1114; VI-NEXT: s_mov_b32 s0, 11115; VI-NEXT: .LBB19_2: ; %done1116; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x241117; VI-NEXT: s_mov_b32 s7, 0xf0001118; VI-NEXT: s_mov_b32 s6, -11119; VI-NEXT: v_mov_b32_e32 v0, s01120; VI-NEXT: s_waitcnt lgkmcnt(0)1121; VI-NEXT: buffer_store_dword v0, off, s[4:7], 01122; VI-NEXT: s_endpgm1123 %cond = load volatile i64, ptr addrspace(3) poison1124 %cmp0 = icmp ne i64 %cond, 01125 br i1 %cmp0, label %if, label %else1126 1127if:1128 br label %done1129 1130else:1131 br label %done1132 1133done:1134 %value = phi i32 [0, %if], [1, %else]1135 store i32 %value, ptr addrspace(1) %out1136 ret void1137}1138 1139define void @move_to_valu_vgpr_operand_phi(ptr addrspace(3) %out) {1140; SI-LABEL: move_to_valu_vgpr_operand_phi:1141; SI: ; %bb.0: ; %bb01142; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1143; SI-NEXT: v_add_i32_e32 v0, vcc, 28, v01144; SI-NEXT: v_mov_b32_e32 v1, 11145; SI-NEXT: s_and_b64 vcc, exec, 01146; SI-NEXT: s_mov_b32 m0, -11147; SI-NEXT: s_branch .LBB20_21148; SI-NEXT: .LBB20_1: ; %bb31149; SI-NEXT: ; in Loop: Header=BB20_2 Depth=11150; SI-NEXT: v_add_i32_e64 v0, s[4:5], 8, v01151; SI-NEXT: .LBB20_2: ; %bb11152; SI-NEXT: ; =>This Inner Loop Header: Depth=11153; SI-NEXT: ;;#ASMSTART1154; SI-NEXT: ; def s41155; SI-NEXT: ;;#ASMEND1156; SI-NEXT: s_cmp_lg_u32 s4, 01157; SI-NEXT: s_cbranch_scc1 .LBB20_11158; SI-NEXT: ; %bb.3: ; %bb21159; SI-NEXT: ; in Loop: Header=BB20_2 Depth=11160; SI-NEXT: ds_write_b32 v0, v11161; SI-NEXT: s_mov_b64 vcc, vcc1162; SI-NEXT: s_cbranch_vccz .LBB20_11163; SI-NEXT: ; %bb.4: ; %DummyReturnBlock1164; SI-NEXT: s_waitcnt lgkmcnt(0)1165; SI-NEXT: s_setpc_b64 s[30:31]1166;1167; VI-LABEL: move_to_valu_vgpr_operand_phi:1168; VI: ; %bb.0: ; %bb01169; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1170; VI-NEXT: v_add_u32_e32 v0, vcc, 28, v01171; VI-NEXT: v_mov_b32_e32 v1, 11172; VI-NEXT: s_and_b64 vcc, exec, 01173; VI-NEXT: s_mov_b32 m0, -11174; VI-NEXT: s_branch .LBB20_21175; VI-NEXT: .LBB20_1: ; %bb31176; VI-NEXT: ; in Loop: Header=BB20_2 Depth=11177; VI-NEXT: v_add_u32_e64 v0, s[4:5], 8, v01178; VI-NEXT: .LBB20_2: ; %bb11179; VI-NEXT: ; =>This Inner Loop Header: Depth=11180; VI-NEXT: ;;#ASMSTART1181; VI-NEXT: ; def s41182; VI-NEXT: ;;#ASMEND1183; VI-NEXT: s_cmp_lg_u32 s4, 01184; VI-NEXT: s_cbranch_scc1 .LBB20_11185; VI-NEXT: ; %bb.3: ; %bb21186; VI-NEXT: ; in Loop: Header=BB20_2 Depth=11187; VI-NEXT: ds_write_b32 v0, v11188; VI-NEXT: s_mov_b64 vcc, vcc1189; VI-NEXT: s_cbranch_vccz .LBB20_11190; VI-NEXT: ; %bb.4: ; %DummyReturnBlock1191; VI-NEXT: s_waitcnt lgkmcnt(0)1192; VI-NEXT: s_setpc_b64 s[30:31]1193bb0:1194 br label %bb11195 1196bb1: ; preds = %bb3, %bb01197 %tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ]1198 %tmp1 = add nsw i32 %tmp0, -11199 %tmp2 = getelementptr inbounds i32, ptr addrspace(3) %out, i32 %tmp11200 %cond = call i32 asm "; def $0","=s"()1201 %cmp = icmp eq i32 %cond, 01202 br i1 %cmp, label %bb2, label %bb31203 1204bb2: ; preds = %bb11205 store volatile i32 1, ptr addrspace(3) %tmp2, align 41206 br label %bb31207 1208bb3: ; preds = %bb2, %bb11209 %tmp4 = add nsw i32 %tmp0, 21210 br label %bb11211}1212 1213declare i32 @llvm.amdgcn.workitem.id.x() #01214 1215attributes #0 = { nounwind readnone }1216;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1217; GCN: {{.*}}1218