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1; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GCN,W32 --enable-var-scope %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GCN,W64 --enable-var-scope %s3; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -S -amdgpu-annotate-uniform < %s | FileCheck --check-prefixes=OPT,OPT-W32 --enable-var-scope %s4; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 -S -amdgpu-annotate-uniform < %s | FileCheck --check-prefixes=OPT,OPT-W64 --enable-var-scope %s5 6; GCN-LABEL: {{^}}lshr_threadid:7; W64: global_load_dword8; W32: v_readfirstlane_b32 [[OFFSET:s[0-9]+]], v09; W32: s_load_dword s{{[0-9]+}}, s[{{[0-9:]+}}], [[OFFSET]]10 11; OPT-LABEL: @lshr_threadid12; OPT-W64: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}13; OPT-W32: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4, !amdgpu.uniform14define amdgpu_kernel void @lshr_threadid(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !0 {15entry:16 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()17 %div = lshr i32 %lid, 518 %div4 = zext i32 %div to i6419 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div420 %load = load i32, ptr addrspace(1) %arrayidx, align 421 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div422 store i32 %load, ptr addrspace(1) %arrayidx2, align 423 ret void24}25 26; GCN-LABEL: {{^}}ashr_threadid:27; W64: global_load_dword28; W32: v_readfirstlane_b32 [[OFFSET:s[0-9]+]], v029; W32: s_load_dword s{{[0-9]+}}, s[{{[0-9:]+}}], [[OFFSET]]30 31; OPT-LABEL: @ashr_threadid32; OPT-W64: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}33; OPT-W32: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4, !amdgpu.uniform34define amdgpu_kernel void @ashr_threadid(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !0 {35entry:36 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()37 %div = ashr i32 %lid, 538 %div4 = zext i32 %div to i6439 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div440 %load = load i32, ptr addrspace(1) %arrayidx, align 441 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div442 store i32 %load, ptr addrspace(1) %arrayidx2, align 443 ret void44}45 46; GCN-LABEL: {{^}}and_threadid:47; W64: global_load_dword48; W32: v_readfirstlane_b32 [[OFFSET:s[0-9]+]], v049; W32: s_load_dword s{{[0-9]+}}, s[{{[0-9:]+}}], [[OFFSET]]50 51; OPT-LABEL: @and_threadid52; OPT-W64: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}53; OPT-W32: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4, !amdgpu.uniform54define amdgpu_kernel void @and_threadid(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !0 {55entry:56 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()57 %and = and i32 %lid, -3258 %div4 = zext i32 %and to i6459 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div460 %load = load i32, ptr addrspace(1) %arrayidx, align 461 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div462 store i32 %load, ptr addrspace(1) %arrayidx2, align 463 ret void64}65 66; GCN-LABEL: {{^}}lshr_threadid_no_dim_info:67; GCN: global_load_dword68 69; OPT-LABEL: @lshr_threadid_no_dim_info70; OPT: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}71define amdgpu_kernel void @lshr_threadid_no_dim_info(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) {72entry:73 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()74 %div = lshr i32 %lid, 575 %div4 = zext i32 %div to i6476 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div477 %load = load i32, ptr addrspace(1) %arrayidx, align 478 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div479 store i32 %load, ptr addrspace(1) %arrayidx2, align 480 ret void81}82 83; GCN-LABEL: {{^}}lshr_threadid_2d:84; GCN: global_load_dword85 86; OPT-LABEL: @lshr_threadid_2d87; OPT: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}88define amdgpu_kernel void @lshr_threadid_2d(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !1 {89entry:90 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()91 %div = lshr i32 %lid, 592 %div4 = zext i32 %div to i6493 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div494 %load = load i32, ptr addrspace(1) %arrayidx, align 495 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div496 store i32 %load, ptr addrspace(1) %arrayidx2, align 497 ret void98}99 100; GCN-LABEL: {{^}}lshr_threadid_3d:101; W64: global_load_dword102; W32: v_readfirstlane_b32 [[OFFSET:s[0-9]+]], v0103; W32: s_load_dword s{{[0-9]+}}, s[{{[0-9:]+}}], [[OFFSET]]104 105; OPT-LABEL: @lshr_threadid_3d106; OPT-W64: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}107; OPT-W32: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4, !amdgpu.uniform108define amdgpu_kernel void @lshr_threadid_3d(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !2 {109entry:110 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()111 %div = lshr i32 %lid, 5112 %div4 = zext i32 %div to i64113 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4114 %load = load i32, ptr addrspace(1) %arrayidx, align 4115 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div4116 store i32 %load, ptr addrspace(1) %arrayidx2, align 4117 ret void118}119 120; GCN-LABEL: {{^}}high_id_uniform:121; GCN: v_lshlrev_b32_e32 v0, 2, v2122; GCN: v_readfirstlane_b32 [[OFFSET:s[0-9]+]], v0123; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9:]+}}], [[OFFSET]]124 125; OPT-LABEL: @high_id_uniform126; OPT: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %zid.zext, !amdgpu.uniform127define amdgpu_kernel void @high_id_uniform(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !2 {128entry:129 %zid = tail call i32 @llvm.amdgcn.workitem.id.z()130 %zid.zext = zext nneg i32 %zid to i64131 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %zid.zext132 %load = load i32, ptr addrspace(1) %arrayidx, align 4133 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %zid.zext134 store i32 %load, ptr addrspace(1) %arrayidx2, align 4135 ret void136}137 138; GCN-LABEL: {{^}}lshr_threadid_1d_uneven:139; W64: global_load_dword140; W32: v_readfirstlane_b32 [[OFFSET:s[0-9]+]], v0141; W32: s_load_dword s{{[0-9]+}}, s[{{[0-9:]+}}], [[OFFSET]]142 143; OPT-LABEL: @lshr_threadid_1d_uneven144; OPT-W64: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}145; OPT-W32: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4, !amdgpu.uniform146define amdgpu_kernel void @lshr_threadid_1d_uneven(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !3 {147entry:148 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()149 %div = lshr i32 %lid, 5150 %div4 = zext i32 %div to i64151 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4152 %load = load i32, ptr addrspace(1) %arrayidx, align 4153 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div4154 store i32 %load, ptr addrspace(1) %arrayidx2, align 4155 ret void156}157 158; GCN-LABEL: {{^}}and_threadid_2d:159; GCN: global_load_dword160 161; OPT-LABEL: @and_threadid_2d162; OPT: %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4{{$}}163define amdgpu_kernel void @and_threadid_2d(ptr addrspace(1) align 4 %in, ptr addrspace(1) align 4 %out) !reqd_work_group_size !1 {164entry:165 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()166 %and = and i32 %lid, -32167 %div4 = zext i32 %and to i64168 %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %in, i64 %div4169 %load = load i32, ptr addrspace(1) %arrayidx, align 4170 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %div4171 store i32 %load, ptr addrspace(1) %arrayidx2, align 4172 ret void173}174 175declare i32 @llvm.amdgcn.workitem.id.x()176 177!0 = !{i32 64, i32 1, i32 1}178!1 = !{i32 65, i32 2, i32 1}179!2 = !{i32 64, i32 1, i32 2}180!3 = !{i32 65, i32 1, i32 1}181