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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -o - %s | FileCheck --check-prefix=GCN %s3;4; This test shows a typical case that a PHI(%c2) in join block was treated as uniform5; as it has one unique uniform incoming value plus one additional undef incoming6; value. This case might suffer from correctness issue if %c2 was assigned a scalar7; register but meanwhile dead in %if. The problem is solved by replacing the %undef8; with %c (thus replacing %c2 with %c in this example).9 10 11define amdgpu_ps float @uniform_phi_with_undef(float inreg %c, float %v, i32 %x, i32 %y) #0 {12; GCN-LABEL: uniform_phi_with_undef:13; GCN: ; %bb.0: ; %entry14; GCN-NEXT: v_cmp_lt_i32_e64 s2, v2, v115; GCN-NEXT: s_mov_b32 s1, exec_lo16; GCN-NEXT: s_and_b32 s2, s1, s217; GCN-NEXT: s_mov_b32 exec_lo, s218; GCN-NEXT: s_cbranch_execz .LBB0_219; GCN-NEXT: ; %bb.1: ; %if20; GCN-NEXT: s_mov_b32 s2, 0x4040000021; GCN-NEXT: v_div_scale_f32 v1, s3, s2, s2, v022; GCN-NEXT: v_rcp_f32_e64 v2, v123; GCN-NEXT: s_mov_b32 s3, 1.024; GCN-NEXT: v_fma_f32 v3, -v1, v2, s325; GCN-NEXT: v_fmac_f32_e64 v2, v3, v226; GCN-NEXT: v_div_scale_f32 v3, vcc_lo, v0, s2, v027; GCN-NEXT: v_mul_f32_e64 v4, v3, v228; GCN-NEXT: v_fma_f32 v5, -v1, v4, v329; GCN-NEXT: v_fmac_f32_e64 v4, v5, v230; GCN-NEXT: v_fma_f32 v1, -v1, v4, v331; GCN-NEXT: v_div_fmas_f32 v1, v1, v2, v432; GCN-NEXT: v_div_fixup_f32 v0, v1, s2, v033; GCN-NEXT: .LBB0_2: ; %end34; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s135; GCN-NEXT: v_add_f32_e64 v0, v0, s036; GCN-NEXT: ; return to shader part epilog37entry:38 %cc = icmp slt i32 %y, %x39 br i1 %cc, label %if, label %end40 41if:42 %v.if = fdiv float %v, 3.043 br label %end44 45end:46 %v2 = phi float [ %v.if, %if ], [ %v, %entry ]47 %c2 = phi float [ poison, %if ], [ %c, %entry ]48 %r = fadd float %v2, %c249 ret float %r50}51 52attributes #0 = { nounwind optnone noinline }53