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1; RUN: llc -mtriple=amdgcn -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s2;3; This test used to crash with the following assertion:4; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode<llvm::SlotIndex, llvm::LiveInterval *, 8, llvm::IntervalMapInfo<llvm::SlotIndex> >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo<llvm::SlotIndex>]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed.5;6; This was related to incorrectly calculating subregister live ranges7; (i.e. live interval subranges): subregister defs are not uses for that8; purpose.9;10; Check for a valid output.11; CHECK: image_sample_c12define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main(ptr addrspace(4) inreg dereferenceable(18446744073709551615) %arg, ptr addrspace(4) inreg dereferenceable(18446744073709551615) %arg1, ptr addrspace(4) inreg dereferenceable(18446744073709551615) %arg2, ptr addrspace(4) inreg dereferenceable(18446744073709551615) %arg3, ptr addrspace(4) inreg dereferenceable(18446744073709551615) %arg4, float inreg %arg5, i32 inreg %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <3 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, <2 x i32> %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, i32 %arg20, float %arg21, i32 %arg22) #0 {13main_body:14 %i.i = extractelement <2 x i32> %arg8, i32 015 %j.i = extractelement <2 x i32> %arg8, i32 116 %i.f.i = bitcast i32 %i.i to float17 %j.f.i = bitcast i32 %j.i to float18 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 3, i32 4, i32 %arg6) #219 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 3, i32 4, i32 %arg6) #220 %tmp23 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)21 22 %tmp24 = extractelement <4 x float> %tmp23, i32 323 %tmp25 = fmul float %tmp24, %tmp2424 %tmp26 = fmul float %p2.i, %p2.i25 %tmp27 = fadd float %tmp26, %tmp2626 %tmp32 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %tmp27, float 0.0, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)27 %tmp33 = extractelement <4 x float> %tmp32, i32 028 %tmp34 = fadd float %tmp33, %tmp3329 %tmp35 = fadd float %tmp34, %tmp3430 %tmp36 = fadd float %tmp35, %tmp3531 %tmp37 = fadd float %tmp36, %tmp3632 %tmp38 = fadd float %tmp37, %tmp3733 %tmp39 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)34 %tmp40 = extractelement <4 x float> %tmp39, i32 035 %tmp41 = extractelement <4 x float> %tmp39, i32 136 %tmp42 = extractelement <4 x float> %tmp39, i32 237 %tmp43 = extractelement <4 x float> %tmp39, i32 338 %tmp44 = fmul float %tmp40, %tmp4039 %tmp45 = fmul float %tmp41, %tmp4140 %tmp46 = fmul float %tmp42, %tmp4141 %tmp47 = fmul float %tmp43, %tmp4342 %tmp48 = fadd float %tmp44, %tmp4443 %tmp49 = fadd float %tmp45, %tmp4544 %tmp50 = bitcast float %tmp27 to i3245 %tmp51 = bitcast float %tmp48 to i3246 %tmp52 = bitcast float %tmp49 to i3247 %tmp53 = insertelement <4 x i32> poison, i32 %tmp50, i32 048 %tmp54 = insertelement <4 x i32> %tmp53, i32 %tmp51, i32 149 %tmp55 = insertelement <4 x i32> %tmp54, i32 %tmp52, i32 250 %tmp55.cast = bitcast <4 x i32> %tmp55 to <4 x float>51 %tmp56 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %tmp27, float %tmp48, float %tmp49, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)52 %tmp57 = extractelement <4 x float> %tmp56, i32 053 %tmp58 = fadd float %tmp38, %tmp5754 %tmp59 = fadd float %tmp46, %tmp4655 %tmp60 = fadd float %tmp47, %tmp4756 %tmp65 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float poison, float %tmp59, float %tmp60, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)57 %tmp66 = extractelement <4 x float> %tmp65, i32 058 %tmp67 = fadd float %tmp58, %tmp6659 %tmp68 = fmul float %tmp67, 1.250000e-0160 %tmp69 = fmul float %tmp68, %tmp6861 %tmp70 = fcmp une float %tmp69, 0.000000e+0062 br i1 %tmp70, label %IF26, label %ENDIF2563 64IF26: ; preds = %main_body65 %tmp71 = bitcast float %tmp27 to i3266 %tmp72 = insertelement <4 x i32> poison, i32 %tmp71, i32 067 br label %LOOP68 69ENDIF25: ; preds = %IF29, %main_body70 %.4 = phi float [ %tmp84, %IF29 ], [ %tmp68, %main_body ]71 %tmp73 = fadd float %.4, %.472 %max.0.i = call float @llvm.maxnum.f32(float %tmp73, float 0.000000e+00)73 %clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)74 %tmp75 = fmul float %clamp.i, %clamp.i75 %tmp76 = fmul float %tmp75, %tmp7576 %tmp77 = fadd float %tmp76, %tmp7677 %tmp78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, float %tmp77, 1178 %tmp79 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp78, float poison, 1279 %tmp80 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp79, float poison, 1380 %tmp81 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp80, float %tmp25, 1481 %tmp82 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp81, float poison, 1582 %tmp83 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp82, float %arg21, 2483 ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp8384 85LOOP: ; preds = %ENDIF28, %IF2686 %.5 = phi float [ poison, %IF26 ], [ %tmp89, %ENDIF28 ]87 br i1 false, label %IF29, label %ENDIF2888 89IF29: ; preds = %LOOP90 %tmp84 = fmul float %.5, 3.125000e-0291 br label %ENDIF2592 93ENDIF28: ; preds = %LOOP94 %tmp87 = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32 15, float %tmp27, float poison, float poison, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)95 %tmp88 = extractelement <4 x float> %tmp87, i32 096 %tmp89 = fadd float %tmp88, %tmp8897 br label %LOOP98}99 100declare float @llvm.minnum.f32(float, float) #1101declare float @llvm.maxnum.f32(float, float) #1102declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1103declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1104declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2105declare <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2106 107attributes #0 = { nounwind "InitialPSInputAddr"="36983" "target-cpu"="tonga" }108attributes #1 = { nounwind readnone }109attributes #2 = { nounwind readonly }110attributes #3 = { nounwind }111