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1; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s2 3; These tests are for condition codes that are not supported by the hardware4 5; CHECK-LABEL: {{^}}slt:6; CHECK: LSHR7; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z8; CHECK-NEXT: 5(7.006492e-45)9define amdgpu_kernel void @slt(ptr addrspace(1) %out, i32 %in) {10entry:11 %0 = icmp slt i32 %in, 512 %1 = select i1 %0, i32 -1, i32 013 store i32 %1, ptr addrspace(1) %out14 ret void15}16 17; CHECK-LABEL: {{^}}ult_i32:18; CHECK: LSHR19; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z20; CHECK-NEXT: 5(7.006492e-45)21define amdgpu_kernel void @ult_i32(ptr addrspace(1) %out, i32 %in) {22entry:23 %0 = icmp ult i32 %in, 524 %1 = select i1 %0, i32 -1, i32 025 store i32 %1, ptr addrspace(1) %out26 ret void27}28 29; CHECK-LABEL: {{^}}ult_float:30; CHECK: SETGE * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x31; CHECK-NEXT: 1084227584(5.000000e+00)32; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.033; CHECK-NEXT: LSHR *34define amdgpu_kernel void @ult_float(ptr addrspace(1) %out, float %in) {35entry:36 %0 = fcmp ult float %in, 5.037 %1 = select i1 %0, float 1.0, float 0.038 store float %1, ptr addrspace(1) %out39 ret void40}41 42; CHECK-LABEL: {{^}}ult_float_native:43; CHECK: LSHR44; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}45; CHECK-NEXT: 1084227584(5.000000e+00)46define amdgpu_kernel void @ult_float_native(ptr addrspace(1) %out, float %in) {47entry:48 %0 = fcmp ult float %in, 5.049 %1 = select i1 %0, float 0.0, float 1.050 store float %1, ptr addrspace(1) %out51 ret void52}53 54; CHECK-LABEL: {{^}}olt:55; CHECK: LSHR56; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z57; CHECK-NEXT: 1084227584(5.000000e+00)58define amdgpu_kernel void @olt(ptr addrspace(1) %out, float %in) {59entry:60 %0 = fcmp olt float %in, 5.061 %1 = select i1 %0, float 1.0, float 0.062 store float %1, ptr addrspace(1) %out63 ret void64}65 66; CHECK-LABEL: {{^}}sle:67; CHECK: LSHR68; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z69; CHECK-NEXT: 6(8.407791e-45)70define amdgpu_kernel void @sle(ptr addrspace(1) %out, i32 %in) {71entry:72 %0 = icmp sle i32 %in, 573 %1 = select i1 %0, i32 -1, i32 074 store i32 %1, ptr addrspace(1) %out75 ret void76}77 78; CHECK-LABEL: {{^}}ule_i32:79; CHECK: LSHR80; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z81; CHECK-NEXT: 6(8.407791e-45)82define amdgpu_kernel void @ule_i32(ptr addrspace(1) %out, i32 %in) {83entry:84 %0 = icmp ule i32 %in, 585 %1 = select i1 %0, i32 -1, i32 086 store i32 %1, ptr addrspace(1) %out87 ret void88}89 90; CHECK-LABEL: {{^}}ule_float:91; CHECK: SETGT * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x92; CHECK-NEXT: 1084227584(5.000000e+00)93; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.094; CHECK-NEXT: LSHR *95define amdgpu_kernel void @ule_float(ptr addrspace(1) %out, float %in) {96entry:97 %0 = fcmp ule float %in, 5.098 %1 = select i1 %0, float 1.0, float 0.099 store float %1, ptr addrspace(1) %out100 ret void101}102 103; CHECK-LABEL: {{^}}ule_float_native:104; CHECK: LSHR105; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}106; CHECK-NEXT: 1084227584(5.000000e+00)107define amdgpu_kernel void @ule_float_native(ptr addrspace(1) %out, float %in) {108entry:109 %0 = fcmp ule float %in, 5.0110 %1 = select i1 %0, float 0.0, float 1.0111 store float %1, ptr addrspace(1) %out112 ret void113}114 115; CHECK-LABEL: {{^}}ole:116; CHECK: LSHR117; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z118; CHECK-NEXT:1084227584(5.000000e+00)119define amdgpu_kernel void @ole(ptr addrspace(1) %out, float %in) {120entry:121 %0 = fcmp ole float %in, 5.0122 %1 = select i1 %0, float 1.0, float 0.0123 store float %1, ptr addrspace(1) %out124 ret void125}126