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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s3 4declare float @llvm.fma.f32(float, float, float) #15declare double @llvm.fma.f64(double, double, double) #16declare float @llvm.fmuladd.f32(float, float, float) #17declare float @llvm.amdgcn.div.fixup.f32(float, float, float) #18 9 10; GCN-LABEL: {{^}}test_sgpr_use_twice_binop:11; GCN: s_load_dword [[SGPR:s[0-9]+]],12; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]13; GCN: buffer_store_dword [[RESULT]]14define amdgpu_kernel void @test_sgpr_use_twice_binop(ptr addrspace(1) %out, float %a) #0 {15 %dbl = fadd float %a, %a16 store float %dbl, ptr addrspace(1) %out, align 417 ret void18}19 20; GCN-LABEL: {{^}}test_sgpr_use_three_ternary_op:21; GCN: s_load_dword [[SGPR:s[0-9]+]],22; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]23; GCN: buffer_store_dword [[RESULT]]24define amdgpu_kernel void @test_sgpr_use_three_ternary_op(ptr addrspace(1) %out, float %a) #0 {25 %fma = call float @llvm.fma.f32(float %a, float %a, float %a) #126 store float %fma, ptr addrspace(1) %out, align 427 ret void28}29 30; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b:31; SI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x932; VI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x2433; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[#LOAD + 3]]34; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[#LOAD + 2]], s[[#LOAD + 2]], [[VGPR1]]35; GCN: buffer_store_dword [[RESULT]]36define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_b(ptr addrspace(1) %out, float %a, float %b) #0 {37 %fma = call float @llvm.fma.f32(float %a, float %a, float %b) #138 store float %fma, ptr addrspace(1) %out, align 439 ret void40}41 42; GCN-LABEL: {{^}}test_use_s_v_s:43; SI: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}44; SI: buffer_load_dword [[VA0:v[0-9]+]]45; SI-NEXT: s_waitcnt vmcnt(0)46; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]47; SI-NEXT: s_waitcnt vmcnt(0)48 49; GCN-NOT: v_mov_b3250 51; VI: buffer_load_dword [[VA0:v[0-9]+]]52; VI-NEXT: s_waitcnt vmcnt(0)53; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]54; VI-NEXT: s_waitcnt vmcnt(0)55; VI: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}56 57; GCN-NOT: v_mov_b3258; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[#LOAD + 3]]59; GCN-NOT: v_mov_b3260 61; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[#LOAD + 2]], [[VA0]], [[VB]]62; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[#LOAD + 2]], [[VA1]], [[VB]]63; GCN: buffer_store_dword [[RESULT0]]64; GCN: buffer_store_dword [[RESULT1]]65define amdgpu_kernel void @test_use_s_v_s(ptr addrspace(1) %out, float %a, float %b, ptr addrspace(1) %in) #0 {66 %va0 = load volatile float, ptr addrspace(1) %in67 %va1 = load volatile float, ptr addrspace(1) %in68 %fma0 = call float @llvm.fma.f32(float %a, float %va0, float %b) #169 %fma1 = call float @llvm.fma.f32(float %a, float %va1, float %b) #170 store volatile float %fma0, ptr addrspace(1) %out71 store volatile float %fma1, ptr addrspace(1) %out72 ret void73}74 75; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a:76; SI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x977; VI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x2478; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[#LOAD + 3]]79; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[#LOAD + 2]], [[VGPR1]], s[[#LOAD + 2]]80; GCN: buffer_store_dword [[RESULT]]81define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_b_a(ptr addrspace(1) %out, float %a, float %b) #0 {82 %fma = call float @llvm.fma.f32(float %a, float %b, float %a) #183 store float %fma, ptr addrspace(1) %out, align 484 ret void85}86 87; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a:88; SI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x989; VI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x2490; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[#LOAD + 3]]91; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], s[[#LOAD + 2]], s[[#LOAD + 2]]92; GCN: buffer_store_dword [[RESULT]]93define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_b_a_a(ptr addrspace(1) %out, float %a, float %b) #0 {94 %fma = call float @llvm.fma.f32(float %b, float %a, float %a) #195 store float %fma, ptr addrspace(1) %out, align 496 ret void97}98 99; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm:100; GCN: s_load_dword [[SGPR:s[0-9]+]]101; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0102; GCN: buffer_store_dword [[RESULT]]103define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_imm(ptr addrspace(1) %out, float %a) #0 {104 %fma = call float @llvm.fma.f32(float %a, float %a, float 2.0) #1105 store float %fma, ptr addrspace(1) %out, align 4106 ret void107}108 109; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a:110; GCN: s_load_dword [[SGPR:s[0-9]+]]111; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]]112; GCN: buffer_store_dword [[RESULT]]113define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_imm_a(ptr addrspace(1) %out, float %a) #0 {114 %fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1115 store float %fma, ptr addrspace(1) %out, align 4116 ret void117}118 119; Don't use fma since fma c, x, y is canonicalized to fma x, c, y120; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a:121; GCN: s_load_dword [[SGPR:s[0-9]+]]122; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]123; GCN: buffer_store_dword [[RESULT]]124define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_imm_a_a(ptr addrspace(1) %out, float %a) #0 {125 %val = call float @llvm.amdgcn.div.fixup.f32(float 2.0, float %a, float %a) #1126 store float %val, ptr addrspace(1) %out, align 4127 ret void128}129 130; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_kimm:131; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]132; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000133; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[VK]]134; GCN: buffer_store_dword [[RESULT]]135define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_kimm(ptr addrspace(1) %out, float %a) #0 {136 %fma = call float @llvm.fma.f32(float %a, float %a, float 1024.0) #1137 store float %fma, ptr addrspace(1) %out, align 4138 ret void139}140 141; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s:142; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]143; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]144; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000145; GCN: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR]]146; GCN: buffer_store_dword [[RESULT0]]147define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s(ptr addrspace(1) %out, float %a) #0 {148 %fma = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1149 store float %fma, ptr addrspace(1) %out150 ret void151}152 153; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s_x2:154; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}155; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[#LOAD + 2]]156; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[#LOAD + 3]]157; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000158; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR0]]159; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SK]], [[SK]], [[VGPR1]]160; GCN: buffer_store_dword [[RESULT0]]161; GCN: buffer_store_dword [[RESULT1]]162; GCN: s_endpgm163define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s_x2(ptr addrspace(1) %out, float %a, float %b) #0 {164 %fma0 = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1165 %fma1 = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %b) #1166 store volatile float %fma0, ptr addrspace(1) %out167 store volatile float %fma1, ptr addrspace(1) %out168 ret void169}170 171; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k:172; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]173; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]174; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000175; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]176; GCN: buffer_store_dword [[RESULT]]177define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k(ptr addrspace(1) %out, float %a) #0 {178 %fma = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1179 store float %fma, ptr addrspace(1) %out180 ret void181}182 183; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k_x2:184; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}185; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[#LOAD + 2]]186; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[#LOAD + 3]]187; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000188; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]189; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]]190; GCN: buffer_store_dword [[RESULT0]]191; GCN: buffer_store_dword [[RESULT1]]192; GCN: s_endpgm193define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k_x2(ptr addrspace(1) %out, float %a, float %b) #0 {194 %fma0 = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1195 %fma1 = call float @llvm.fma.f32(float 1024.0, float %b, float 1024.0) #1196 store volatile float %fma0, ptr addrspace(1) %out197 store volatile float %fma1, ptr addrspace(1) %out198 ret void199}200 201; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k:202; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]203; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]204; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000205; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]206; GCN: buffer_store_dword [[RESULT]]207define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k(ptr addrspace(1) %out, float %a) #0 {208 %fma = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1209 store float %fma, ptr addrspace(1) %out210 ret void211}212 213; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k_x2:214; GCN-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}}215; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[#LOAD + 2]]216; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[#LOAD + 3]]217; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000218; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]219; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]]220; GCN: buffer_store_dword [[RESULT0]]221; GCN: buffer_store_dword [[RESULT1]]222; GCN: s_endpgm223define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k_x2(ptr addrspace(1) %out, float %a, float %b) #0 {224 %fma0 = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1225 %fma1 = call float @llvm.fma.f32(float %b, float 1024.0, float 1024.0) #1226 store volatile float %fma0, ptr addrspace(1) %out227 store volatile float %fma1, ptr addrspace(1) %out228 ret void229}230 231; GCN-LABEL: {{^}}test_s0_s1_k_f32:232; SI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x9233; VI-DAG: s_load_dwordx4 s[[[#LOAD:]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x24234; GCN-DAG: v_mov_b32_e32 [[VK0:v[0-9]+]], 0x44800000235; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], s[[#LOAD + 3]]236 237; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[#LOAD + 2]], [[VS1]], [[VK0]]238; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000239; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[#LOAD + 2]], [[VS1]], [[VK1]]240 241; GCN: buffer_store_dword [[RESULT0]]242; GCN: buffer_store_dword [[RESULT1]]243define amdgpu_kernel void @test_s0_s1_k_f32(ptr addrspace(1) %out, float %a, float %b) #0 {244 %fma0 = call float @llvm.fma.f32(float %a, float %b, float 1024.0) #1245 %fma1 = call float @llvm.fma.f32(float %a, float %b, float 4096.0) #1246 store volatile float %fma0, ptr addrspace(1) %out247 store volatile float %fma1, ptr addrspace(1) %out248 ret void249}250 251; FIXME: Immediate in SGPRs just copied to VGPRs252; GCN-LABEL: {{^}}test_s0_s1_k_f64:253; GCN-DAG: s_load_dwordx2 [[SGPR0:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}254; GCN-DAG: s_load_dwordx2 s[[[SGPR1_SUB0:[0-9]+]]:[[SGPR1_SUB1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x1d|0x74}}255; GCN-DAG: v_mov_b32_e32 v[[VK0_SUB1:[0-9]+]], 0x40900000256; GCN-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0{{$}}257 258; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB0:[0-9]+]], s[[SGPR1_SUB0]]259; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB1:[0-9]+]], s[[SGPR1_SUB1]]260; GCN-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v[[[VS1_SUB0]]:[[VS1_SUB1]]], v[[[VZERO]]:[[VK0_SUB1]]]261 262; GCN-DAG: v_mov_b32_e32 v[[VK1_SUB1:[0-9]+]], 0x40b00000263; GCN-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v[[[VS1_SUB0]]:[[VS1_SUB1]]], v[{{[0-9]+}}:[[VK1_SUB1]]]264 265; GCN: buffer_store_dwordx2 [[RESULT0]]266; GCN: buffer_store_dwordx2 [[RESULT1]]267define amdgpu_kernel void @test_s0_s1_k_f64(ptr addrspace(1) %out, [8 x i32], double %a, [8 x i32], double %b) #0 {268 %fma0 = call double @llvm.fma.f64(double %a, double %b, double 1024.0) #1269 %fma1 = call double @llvm.fma.f64(double %a, double %b, double 4096.0) #1270 store volatile double %fma0, ptr addrspace(1) %out271 store volatile double %fma1, ptr addrspace(1) %out272 ret void273}274 275attributes #0 = { nounwind }276attributes #1 = { nounwind readnone }277