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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s -debugify-and-strip-all-safe | FileCheck -check-prefixes=GFX9 %s4 5define amdgpu_kernel void @sdwa_test() local_unnamed_addr #0 {6; GFX9-LABEL: sdwa_test:7; GFX9:       ; %bb.0: ; %bb8; GFX9-NEXT:    v_add_u32_e32 v1, 20, v09; GFX9-NEXT:    v_and_b32_e32 v1, 0xff, v110; GFX9-NEXT:    v_add3_u32 v0, v0, v1, 1011; GFX9-NEXT:    v_mov_b32_e32 v1, 012; GFX9-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off13; GFX9-NEXT:    s_endpgm14bb:15  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()16  %v0 = add i32 %tid, 1017  %v1 = add i32 %tid, 2018  %v2 = zext i32 %v0 to i6419  %v3 = zext i32 %v1 to i6420  %v.t = and i64 %v3, 25521  %v4 = add i64 %v2, %v.t22  store i64 %v4, ptr addrspace(1) poison23  ret void24}25 26define amdgpu_kernel void @test_add_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {27; GFX9-LABEL: test_add_co_sdwa:28; GFX9:       ; %bb.0: ; %bb29; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2430; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 2, v031; GFX9-NEXT:    v_lshlrev_b32_e32 v3, 3, v032; GFX9-NEXT:    s_waitcnt lgkmcnt(0)33; GFX9-NEXT:    global_load_dword v4, v2, s[2:3]34; GFX9-NEXT:    global_load_dwordx2 v[0:1], v3, s[0:1]35; GFX9-NEXT:    s_waitcnt vmcnt(0)36; GFX9-NEXT:    v_add_co_u32_sdwa v0, vcc, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_037; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc38; GFX9-NEXT:    global_store_dwordx2 v3, v[0:1], s[0:1]39; GFX9-NEXT:    s_endpgm40bb:41  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()42  %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp43  %tmp4 = load i32, ptr addrspace(1) %tmp3, align 444  %tmp5 = and i32 %tmp4, 25545  %tmp6 = zext i32 %tmp5 to i6446  %tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp47  %tmp8 = load i64, ptr addrspace(1) %tmp7, align 848  %tmp9 = add nsw i64 %tmp8, %tmp649  store i64 %tmp9, ptr addrspace(1) %tmp7, align 850  ret void51}52