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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s4define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {5; GFX950-LABEL: v_ashr_pk_i8_i32:6; GFX950: ; %bb.0:7; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c8; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x249; GFX950-NEXT: v_mov_b32_e32 v0, 010; GFX950-NEXT: s_waitcnt lgkmcnt(0)11; GFX950-NEXT: s_and_b32 s2, s2, 3112; GFX950-NEXT: v_mov_b32_e32 v1, s113; GFX950-NEXT: v_mov_b32_e32 v2, s214; GFX950-NEXT: v_ashr_pk_i8_i32 v1, s0, v1, v215; GFX950-NEXT: global_store_short v0, v1, s[6:7]16; GFX950-NEXT: s_endpgm17;18; GFX1250-LABEL: v_ashr_pk_i8_i32:19; GFX1250: ; %bb.0:20; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 121; GFX1250-NEXT: s_clause 0x122; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c23; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x2424; GFX1250-NEXT: v_mov_b32_e32 v1, 025; GFX1250-NEXT: s_wait_kmcnt 0x026; GFX1250-NEXT: s_and_b32 s2, s2, 3127; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)28; GFX1250-NEXT: v_mov_b32_e32 v0, s229; GFX1250-NEXT: v_ashr_pk_i8_i32 v0, s0, s1, v030; GFX1250-NEXT: global_store_b16 v1, v0, s[6:7]31; GFX1250-NEXT: s_endpgm32 %insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 033 %build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 134 %src2.clamp = and i32 %src2, 3135 %insert.1 = insertelement <2 x i32> poison, i32 %src2.clamp, i64 036 %src2.broadcast = shufflevector <2 x i32> %insert.1, <2 x i32> poison, <2 x i32> zeroinitializer37 %ashr = ashr <2 x i32> %build_vector, %src2.broadcast38 %sat.low = tail call <2 x i32> @llvm.smax.v2i32(<2 x i32> %ashr, <2 x i32> <i32 -128, i32 -128>)39 %sat.hi = tail call <2 x i32> @llvm.smin.v2i32(<2 x i32> %sat.low, <2 x i32> <i32 127, i32 127>)40 %trunc = trunc nsw <2 x i32> %sat.hi to <2 x i8>41 %ret = bitcast <2 x i8> %trunc to i1642 store i16 %ret, ptr addrspace(1) %out43 ret void44}45 46define amdgpu_kernel void @v_ashr_pk_u8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {47; GFX950-LABEL: v_ashr_pk_u8_i32:48; GFX950: ; %bb.0:49; GFX950-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c50; GFX950-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2451; GFX950-NEXT: v_mov_b32_e32 v0, 052; GFX950-NEXT: s_waitcnt lgkmcnt(0)53; GFX950-NEXT: s_and_b32 s2, s2, 3154; GFX950-NEXT: v_mov_b32_e32 v1, s155; GFX950-NEXT: v_mov_b32_e32 v2, s256; GFX950-NEXT: v_ashr_pk_u8_i32 v1, s0, v1, v257; GFX950-NEXT: global_store_short v0, v1, s[6:7]58; GFX950-NEXT: s_endpgm59;60; GFX1250-LABEL: v_ashr_pk_u8_i32:61; GFX1250: ; %bb.0:62; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 163; GFX1250-NEXT: s_clause 0x164; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c65; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x2466; GFX1250-NEXT: v_mov_b32_e32 v1, 067; GFX1250-NEXT: s_wait_kmcnt 0x068; GFX1250-NEXT: s_and_b32 s2, s2, 3169; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)70; GFX1250-NEXT: v_mov_b32_e32 v0, s271; GFX1250-NEXT: v_ashr_pk_u8_i32 v0, s0, s1, v072; GFX1250-NEXT: global_store_b16 v1, v0, s[6:7]73; GFX1250-NEXT: s_endpgm74 %insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 075 %build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 176 %src2.clamp = and i32 %src2, 3177 %insert.1 = insertelement <2 x i32> poison, i32 %src2.clamp, i64 078 %src2.broadcast = shufflevector <2 x i32> %insert.1, <2 x i32> poison, <2 x i32> zeroinitializer79 %ashr = ashr <2 x i32> %build_vector, %src2.broadcast80 %sat.low = tail call <2 x i32> @llvm.smax.v2i32(<2 x i32> %ashr, <2 x i32> <i32 0, i32 0>)81 %sat.hi = tail call <2 x i32> @llvm.smin.v2i32(<2 x i32> %sat.low, <2 x i32> <i32 255, i32 255>)82 %trunc = trunc nsw <2 x i32> %sat.hi to <2 x i8>83 %ret = bitcast <2 x i8> %trunc to i1684 store i16 %ret, ptr addrspace(1) %out85 ret void86}87