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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize64 --global-isel=0 -mcpu=gfx1100 < %s | FileCheck -check-prefixes=CHECK %s3 4define amdgpu_kernel void @icmp_test() {5; CHECK-LABEL: icmp_test:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: v_cmp_eq_u16_e64 s[0:1], 0, 08; CHECK-NEXT: v_mov_b32_e32 v1, 09; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 010; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 011; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)12; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]13; CHECK-NEXT: ds_store_b32 v1, v014; CHECK-NEXT: s_endpgm15entry:16 %icmp.intr = tail call i64 @llvm.amdgcn.icmp.i64.i16(i16 0, i16 0, i32 32)17 %cmp0 = icmp eq i64 %icmp.intr, 018 %zext0 = zext i1 %cmp0 to i3219 store i32 %zext0, ptr addrspace(3) null, align 214748364820 ret void21}22 23define amdgpu_kernel void @fcmp_test(half %x, half %y) {24; CHECK-LABEL: fcmp_test:25; CHECK: ; %bb.0: ; %entry26; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x027; CHECK-NEXT: v_mov_b32_e32 v1, 028; CHECK-NEXT: s_waitcnt lgkmcnt(0)29; CHECK-NEXT: s_lshr_b32 s1, s0, 1630; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)31; CHECK-NEXT: v_cmp_le_f16_e64 s[0:1], s0, s132; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 033; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 034; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]35; CHECK-NEXT: ds_store_b32 v1, v036; CHECK-NEXT: s_endpgm37entry:38 %fcmp.intr = tail call i64 @llvm.amdgcn.fcmp.i64.f16(half %x, half %y, i32 5)39 %cmp0 = icmp eq i64 %fcmp.intr, 040 %zext0 = zext i1 %cmp0 to i3241 store i32 %zext0, ptr addrspace(3) null, align 214748364842 ret void43}44 45define amdgpu_kernel void @ballot_test(half %x, half %y) {46; CHECK-LABEL: ballot_test:47; CHECK: ; %bb.0:48; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x049; CHECK-NEXT: v_mov_b32_e32 v2, 050; CHECK-NEXT: s_waitcnt lgkmcnt(0)51; CHECK-NEXT: s_lshr_b32 s1, s0, 1652; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)53; CHECK-NEXT: v_cmp_eq_f16_e64 s[0:1], s0, s154; CHECK-NEXT: v_mov_b32_e32 v0, s055; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)56; CHECK-NEXT: v_mov_b32_e32 v1, s157; CHECK-NEXT: ds_store_b64 v2, v[0:1]58; CHECK-NEXT: s_endpgm59 %cmp = fcmp oeq half %x, %y60 %ballot = tail call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)61 store i64 %ballot, ptr addrspace(3) null, align 214748364862 ret void63}64 65declare i64 @llvm.amdgcn.icmp.i64.i16(i16, i16, i32 immarg) #066 67declare i64 @llvm.amdgcn.fcmp.i64.f16(half, half, i32 immarg) #068 69declare i64 @llvm.amdgcn.ballot.i64(i1) #070 71attributes #0 = { convergent nounwind readnone willreturn }72