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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefixes=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefixes=GFX10 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-TRUE16 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-TRUE16 %s8; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-FAKE16 %s9 10declare i32 @llvm.amdgcn.workitem.id.x() #111declare half @llvm.fabs.f16(half)12declare float @llvm.fabs.f32(float)13declare double @llvm.fabs.f64(double)14 15; All nan values are converted to 0xffffffff16define amdgpu_kernel void @v_cnd_nan_nosgpr(ptr addrspace(1) %out, i32 %c, ptr addrspace(1) %fptr) #0 {17; SI-LABEL: v_cnd_nan_nosgpr:18; SI:       ; %bb.0:19; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x920; SI-NEXT:    s_load_dword s8, s[4:5], 0xb21; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd22; SI-NEXT:    s_mov_b32 s3, 0xf00023; SI-NEXT:    s_mov_b32 s6, 024; SI-NEXT:    s_mov_b32 s7, s325; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v026; SI-NEXT:    v_mov_b32_e32 v1, 027; SI-NEXT:    s_waitcnt lgkmcnt(0)28; SI-NEXT:    buffer_load_dword v0, v[0:1], s[4:7], 0 addr6429; SI-NEXT:    s_mov_b32 s2, -130; SI-NEXT:    s_cmp_eq_u32 s8, 031; SI-NEXT:    s_cselect_b64 vcc, -1, 032; SI-NEXT:    s_waitcnt vmcnt(0)33; SI-NEXT:    v_cndmask_b32_e32 v0, -1, v0, vcc34; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 035; SI-NEXT:    s_endpgm36;37; VI-LABEL: v_cnd_nan_nosgpr:38; VI:       ; %bb.0:39; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x3440; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v041; VI-NEXT:    s_waitcnt lgkmcnt(0)42; VI-NEXT:    v_mov_b32_e32 v1, s143; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v044; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc45; VI-NEXT:    flat_load_dword v0, v[0:1]46; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c47; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2448; VI-NEXT:    s_waitcnt lgkmcnt(0)49; VI-NEXT:    s_cmp_eq_u32 s2, 050; VI-NEXT:    s_cselect_b64 vcc, -1, 051; VI-NEXT:    s_waitcnt vmcnt(0)52; VI-NEXT:    v_cndmask_b32_e32 v2, -1, v0, vcc53; VI-NEXT:    v_mov_b32_e32 v0, s054; VI-NEXT:    v_mov_b32_e32 v1, s155; VI-NEXT:    flat_store_dword v[0:1], v256; VI-NEXT:    s_endpgm57;58; GFX10-LABEL: v_cnd_nan_nosgpr:59; GFX10:       ; %bb.0:60; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x3461; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v062; GFX10-NEXT:    v_mov_b32_e32 v1, 063; GFX10-NEXT:    s_waitcnt lgkmcnt(0)64; GFX10-NEXT:    global_load_dword v0, v0, s[0:1]65; GFX10-NEXT:    s_clause 0x166; GFX10-NEXT:    s_load_dword s2, s[4:5], 0x2c67; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)68; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2469; GFX10-NEXT:    s_waitcnt lgkmcnt(0)70; GFX10-NEXT:    s_cmp_eq_u32 s2, 071; GFX10-NEXT:    s_cselect_b64 vcc, -1, 072; GFX10-NEXT:    s_waitcnt vmcnt(0)73; GFX10-NEXT:    v_cndmask_b32_e32 v0, -1, v0, vcc74; GFX10-NEXT:    global_store_dword v1, v0, s[0:1]75; GFX10-NEXT:    s_endpgm76;77; GFX11-LABEL: v_cnd_nan_nosgpr:78; GFX11:       ; %bb.0:79; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x3480; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v081; GFX11-NEXT:    v_mov_b32_e32 v1, 082; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)83; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v084; GFX11-NEXT:    s_waitcnt lgkmcnt(0)85; GFX11-NEXT:    global_load_b32 v0, v0, s[0:1]86; GFX11-NEXT:    s_clause 0x187; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c88; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x2489; GFX11-NEXT:    s_waitcnt lgkmcnt(0)90; GFX11-NEXT:    s_cmp_eq_u32 s2, 091; GFX11-NEXT:    s_cselect_b64 vcc, -1, 092; GFX11-NEXT:    s_waitcnt vmcnt(0)93; GFX11-NEXT:    v_cndmask_b32_e32 v0, -1, v0, vcc94; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]95; GFX11-NEXT:    s_endpgm96;97; GFX12-LABEL: v_cnd_nan_nosgpr:98; GFX12:       ; %bb.0:99; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34100; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0101; GFX12-NEXT:    v_mov_b32_e32 v1, 0102; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)103; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0104; GFX12-NEXT:    s_wait_kmcnt 0x0105; GFX12-NEXT:    global_load_b32 v0, v0, s[0:1]106; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24107; GFX12-NEXT:    s_wait_kmcnt 0x0108; GFX12-NEXT:    s_cmp_eq_u32 s2, 0109; GFX12-NEXT:    s_cselect_b64 vcc, -1, 0110; GFX12-NEXT:    s_wait_loadcnt 0x0111; GFX12-NEXT:    v_cndmask_b32_e32 v0, -1, v0, vcc112; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]113; GFX12-NEXT:    s_endpgm114  %idx = call i32 @llvm.amdgcn.workitem.id.x() #1115  %f.gep = getelementptr float, ptr addrspace(1) %fptr, i32 %idx116  %f = load float, ptr addrspace(1) %f.gep117  %setcc = icmp ne i32 %c, 0118  %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f119  store float %select, ptr addrspace(1) %out120  ret void121}122 123; This requires slightly trickier SGPR operand legalization since the124; single constant bus SGPR usage is the last operand, and it should125; never be moved.126; However on GFX10 constant bus is limited to 2 scalar operands, not one.127; All nan values are converted to 0xffffffff128define amdgpu_kernel void @v_cnd_nan(ptr addrspace(1) %out, i32 %c, float %f) #0 {129; SI-LABEL: v_cnd_nan:130; SI:       ; %bb.0:131; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9132; SI-NEXT:    s_mov_b32 s7, 0xf000133; SI-NEXT:    s_mov_b32 s6, -1134; SI-NEXT:    s_waitcnt lgkmcnt(0)135; SI-NEXT:    s_mov_b32 s4, s0136; SI-NEXT:    s_mov_b32 s5, s1137; SI-NEXT:    s_cmp_eq_u32 s2, 0138; SI-NEXT:    v_mov_b32_e32 v0, s3139; SI-NEXT:    s_cselect_b64 vcc, -1, 0140; SI-NEXT:    v_cndmask_b32_e32 v0, -1, v0, vcc141; SI-NEXT:    buffer_store_dword v0, off, s[4:7], 0142; SI-NEXT:    s_endpgm143;144; VI-LABEL: v_cnd_nan:145; VI:       ; %bb.0:146; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24147; VI-NEXT:    s_waitcnt lgkmcnt(0)148; VI-NEXT:    s_cmp_eq_u32 s2, 0149; VI-NEXT:    v_mov_b32_e32 v0, s3150; VI-NEXT:    s_cselect_b64 vcc, -1, 0151; VI-NEXT:    v_cndmask_b32_e32 v2, -1, v0, vcc152; VI-NEXT:    v_mov_b32_e32 v0, s0153; VI-NEXT:    v_mov_b32_e32 v1, s1154; VI-NEXT:    flat_store_dword v[0:1], v2155; VI-NEXT:    s_endpgm156;157; GFX10-LABEL: v_cnd_nan:158; GFX10:       ; %bb.0:159; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24160; GFX10-NEXT:    v_mov_b32_e32 v0, 0161; GFX10-NEXT:    s_waitcnt lgkmcnt(0)162; GFX10-NEXT:    s_cmp_eq_u32 s2, 0163; GFX10-NEXT:    s_cselect_b64 s[4:5], -1, 0164; GFX10-NEXT:    v_cndmask_b32_e64 v1, -1, s3, s[4:5]165; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]166; GFX10-NEXT:    s_endpgm167;168; GFX11-LABEL: v_cnd_nan:169; GFX11:       ; %bb.0:170; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24171; GFX11-NEXT:    v_mov_b32_e32 v0, 0172; GFX11-NEXT:    s_waitcnt lgkmcnt(0)173; GFX11-NEXT:    s_cmp_eq_u32 s2, 0174; GFX11-NEXT:    s_cselect_b64 s[4:5], -1, 0175; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)176; GFX11-NEXT:    v_cndmask_b32_e64 v1, -1, s3, s[4:5]177; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]178; GFX11-NEXT:    s_endpgm179;180; GFX12-LABEL: v_cnd_nan:181; GFX12:       ; %bb.0:182; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24183; GFX12-NEXT:    v_mov_b32_e32 v0, 0184; GFX12-NEXT:    s_wait_kmcnt 0x0185; GFX12-NEXT:    s_cmp_eq_u32 s2, 0186; GFX12-NEXT:    s_cselect_b32 s2, s3, -1187; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)188; GFX12-NEXT:    v_mov_b32_e32 v1, s2189; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]190; GFX12-NEXT:    s_endpgm191  %setcc = icmp ne i32 %c, 0192  %select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f193  store float %select, ptr addrspace(1) %out194  ret void195}196 197; Test different compare and select operand types for optimal code198; shrinking.199; (select (cmp (sgprX, constant)), constant, sgprZ)200define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_sgprZ_f32(ptr addrspace(1) %out, [8 x i32], float %x, float %z) #0 {201; SI-LABEL: fcmp_sgprX_k0_select_k1_sgprZ_f32:202; SI:       ; %bb.0:203; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9204; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x13205; SI-NEXT:    s_mov_b32 s3, 0xf000206; SI-NEXT:    s_mov_b32 s2, 0207; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0208; SI-NEXT:    v_mov_b32_e32 v1, 0209; SI-NEXT:    s_waitcnt lgkmcnt(0)210; SI-NEXT:    v_mov_b32_e32 v2, s5211; SI-NEXT:    v_cmp_nlg_f32_e64 vcc, s4, 0212; SI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc213; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64214; SI-NEXT:    s_endpgm215;216; VI-LABEL: fcmp_sgprX_k0_select_k1_sgprZ_f32:217; VI:       ; %bb.0:218; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24219; VI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x4c220; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0221; VI-NEXT:    s_waitcnt lgkmcnt(0)222; VI-NEXT:    v_mov_b32_e32 v1, s1223; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v0224; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc225; VI-NEXT:    v_mov_b32_e32 v2, s3226; VI-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0227; VI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc228; VI-NEXT:    flat_store_dword v[0:1], v2229; VI-NEXT:    s_endpgm230;231; GFX10-LABEL: fcmp_sgprX_k0_select_k1_sgprZ_f32:232; GFX10:       ; %bb.0:233; GFX10-NEXT:    s_clause 0x1234; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c235; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24236; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0237; GFX10-NEXT:    s_waitcnt lgkmcnt(0)238; GFX10-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s0, 0239; GFX10-NEXT:    v_cndmask_b32_e64 v1, 1.0, s1, s[4:5]240; GFX10-NEXT:    global_store_dword v0, v1, s[2:3]241; GFX10-NEXT:    s_endpgm242;243; GFX11-LABEL: fcmp_sgprX_k0_select_k1_sgprZ_f32:244; GFX11:       ; %bb.0:245; GFX11-NEXT:    s_clause 0x1246; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x4c247; GFX11-NEXT:    s_load_b64 s[2:3], s[4:5], 0x24248; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0249; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)250; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0251; GFX11-NEXT:    s_waitcnt lgkmcnt(0)252; GFX11-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s0, 0253; GFX11-NEXT:    v_cndmask_b32_e64 v1, 1.0, s1, s[4:5]254; GFX11-NEXT:    global_store_b32 v0, v1, s[2:3]255; GFX11-NEXT:    s_endpgm256;257; GFX12-LABEL: fcmp_sgprX_k0_select_k1_sgprZ_f32:258; GFX12:       ; %bb.0:259; GFX12-NEXT:    s_clause 0x1260; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x4c261; GFX12-NEXT:    s_load_b64 s[2:3], s[4:5], 0x24262; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0263; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)264; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0265; GFX12-NEXT:    s_wait_kmcnt 0x0266; GFX12-NEXT:    s_cmp_nlg_f32 s0, 0267; GFX12-NEXT:    s_cselect_b32 s0, s1, 1.0268; GFX12-NEXT:    v_mov_b32_e32 v1, s0269; GFX12-NEXT:    global_store_b32 v0, v1, s[2:3]270; GFX12-NEXT:    s_endpgm271  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1272  %tid.ext = sext i32 %tid to i64273  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext274  %setcc = fcmp one float %x, 0.0275  %select = select i1 %setcc, float 1.0, float %z276  store float %select, ptr addrspace(1) %out.gep277  ret void278}279 280define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_sgprX_f32(ptr addrspace(1) %out, float %x) #0 {281; SI-LABEL: fcmp_sgprX_k0_select_k1_sgprX_f32:282; SI:       ; %bb.0:283; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9284; SI-NEXT:    s_load_dword s4, s[4:5], 0xb285; SI-NEXT:    s_mov_b32 s3, 0xf000286; SI-NEXT:    s_mov_b32 s2, 0287; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0288; SI-NEXT:    v_mov_b32_e32 v1, 0289; SI-NEXT:    s_waitcnt lgkmcnt(0)290; SI-NEXT:    v_mov_b32_e32 v2, s4291; SI-NEXT:    v_cmp_nlg_f32_e64 vcc, s4, 0292; SI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc293; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64294; SI-NEXT:    s_endpgm295;296; VI-LABEL: fcmp_sgprX_k0_select_k1_sgprX_f32:297; VI:       ; %bb.0:298; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24299; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c300; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0301; VI-NEXT:    s_waitcnt lgkmcnt(0)302; VI-NEXT:    v_mov_b32_e32 v1, s1303; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v0304; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc305; VI-NEXT:    v_mov_b32_e32 v2, s2306; VI-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0307; VI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc308; VI-NEXT:    flat_store_dword v[0:1], v2309; VI-NEXT:    s_endpgm310;311; GFX10-LABEL: fcmp_sgprX_k0_select_k1_sgprX_f32:312; GFX10:       ; %bb.0:313; GFX10-NEXT:    s_clause 0x1314; GFX10-NEXT:    s_load_dword s6, s[4:5], 0x2c315; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24316; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0317; GFX10-NEXT:    s_waitcnt lgkmcnt(0)318; GFX10-NEXT:    v_cmp_nlg_f32_e64 s[2:3], s6, 0319; GFX10-NEXT:    v_cndmask_b32_e64 v1, 1.0, s6, s[2:3]320; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]321; GFX10-NEXT:    s_endpgm322;323; GFX11-LABEL: fcmp_sgprX_k0_select_k1_sgprX_f32:324; GFX11:       ; %bb.0:325; GFX11-NEXT:    s_clause 0x1326; GFX11-NEXT:    s_load_b32 s6, s[4:5], 0x2c327; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24328; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0329; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)330; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0331; GFX11-NEXT:    s_waitcnt lgkmcnt(0)332; GFX11-NEXT:    v_cmp_nlg_f32_e64 s[2:3], s6, 0333; GFX11-NEXT:    v_cndmask_b32_e64 v1, 1.0, s6, s[2:3]334; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]335; GFX11-NEXT:    s_endpgm336;337; GFX12-LABEL: fcmp_sgprX_k0_select_k1_sgprX_f32:338; GFX12:       ; %bb.0:339; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24340; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0341; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)342; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0343; GFX12-NEXT:    s_wait_kmcnt 0x0344; GFX12-NEXT:    s_cmp_nlg_f32 s2, 0345; GFX12-NEXT:    s_cselect_b32 s2, s2, 1.0346; GFX12-NEXT:    v_mov_b32_e32 v1, s2347; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]348; GFX12-NEXT:    s_endpgm349  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1350  %tid.ext = sext i32 %tid to i64351  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext352  %setcc = fcmp one float %x, 0.0353  %select = select i1 %setcc, float 1.0, float %x354  store float %select, ptr addrspace(1) %out.gep355  ret void356}357 358define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_sgprZ_f32(ptr addrspace(1) %out, [8 x i32], float %x, float %z) #0 {359; SI-LABEL: fcmp_sgprX_k0_select_k0_sgprZ_f32:360; SI:       ; %bb.0:361; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9362; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x13363; SI-NEXT:    s_mov_b32 s3, 0xf000364; SI-NEXT:    s_mov_b32 s2, 0365; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0366; SI-NEXT:    v_mov_b32_e32 v1, 0367; SI-NEXT:    s_waitcnt lgkmcnt(0)368; SI-NEXT:    v_mov_b32_e32 v2, s5369; SI-NEXT:    v_cmp_nlg_f32_e64 vcc, s4, 0370; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc371; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64372; SI-NEXT:    s_endpgm373;374; VI-LABEL: fcmp_sgprX_k0_select_k0_sgprZ_f32:375; VI:       ; %bb.0:376; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24377; VI-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x4c378; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0379; VI-NEXT:    s_waitcnt lgkmcnt(0)380; VI-NEXT:    v_mov_b32_e32 v1, s1381; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v0382; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc383; VI-NEXT:    v_mov_b32_e32 v2, s3384; VI-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0385; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc386; VI-NEXT:    flat_store_dword v[0:1], v2387; VI-NEXT:    s_endpgm388;389; GFX10-LABEL: fcmp_sgprX_k0_select_k0_sgprZ_f32:390; GFX10:       ; %bb.0:391; GFX10-NEXT:    s_clause 0x1392; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x4c393; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24394; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0395; GFX10-NEXT:    s_waitcnt lgkmcnt(0)396; GFX10-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s0, 0397; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, s1, s[4:5]398; GFX10-NEXT:    global_store_dword v0, v1, s[2:3]399; GFX10-NEXT:    s_endpgm400;401; GFX11-LABEL: fcmp_sgprX_k0_select_k0_sgprZ_f32:402; GFX11:       ; %bb.0:403; GFX11-NEXT:    s_clause 0x1404; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x4c405; GFX11-NEXT:    s_load_b64 s[2:3], s[4:5], 0x24406; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0407; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)408; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0409; GFX11-NEXT:    s_waitcnt lgkmcnt(0)410; GFX11-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s0, 0411; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, s1, s[4:5]412; GFX11-NEXT:    global_store_b32 v0, v1, s[2:3]413; GFX11-NEXT:    s_endpgm414;415; GFX12-LABEL: fcmp_sgprX_k0_select_k0_sgprZ_f32:416; GFX12:       ; %bb.0:417; GFX12-NEXT:    s_clause 0x1418; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x4c419; GFX12-NEXT:    s_load_b64 s[2:3], s[4:5], 0x24420; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0421; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)422; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0423; GFX12-NEXT:    s_wait_kmcnt 0x0424; GFX12-NEXT:    s_cmp_nlg_f32 s0, 0425; GFX12-NEXT:    s_cselect_b32 s0, s1, 0426; GFX12-NEXT:    v_mov_b32_e32 v1, s0427; GFX12-NEXT:    global_store_b32 v0, v1, s[2:3]428; GFX12-NEXT:    s_endpgm429  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1430  %tid.ext = sext i32 %tid to i64431  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext432  %setcc = fcmp one float %x, 0.0433  %select = select i1 %setcc, float 0.0, float %z434  store float %select, ptr addrspace(1) %out.gep435  ret void436}437 438define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_sgprX_f32(ptr addrspace(1) %out, float %x) #0 {439; SI-LABEL: fcmp_sgprX_k0_select_k0_sgprX_f32:440; SI:       ; %bb.0:441; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9442; SI-NEXT:    s_load_dword s4, s[4:5], 0xb443; SI-NEXT:    s_mov_b32 s3, 0xf000444; SI-NEXT:    s_mov_b32 s2, 0445; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0446; SI-NEXT:    v_mov_b32_e32 v1, 0447; SI-NEXT:    s_waitcnt lgkmcnt(0)448; SI-NEXT:    v_mov_b32_e32 v2, s4449; SI-NEXT:    v_cmp_nlg_f32_e64 vcc, s4, 0450; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc451; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64452; SI-NEXT:    s_endpgm453;454; VI-LABEL: fcmp_sgprX_k0_select_k0_sgprX_f32:455; VI:       ; %bb.0:456; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24457; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c458; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0459; VI-NEXT:    s_waitcnt lgkmcnt(0)460; VI-NEXT:    v_mov_b32_e32 v1, s1461; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v0462; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc463; VI-NEXT:    v_mov_b32_e32 v2, s2464; VI-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0465; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc466; VI-NEXT:    flat_store_dword v[0:1], v2467; VI-NEXT:    s_endpgm468;469; GFX10-LABEL: fcmp_sgprX_k0_select_k0_sgprX_f32:470; GFX10:       ; %bb.0:471; GFX10-NEXT:    s_clause 0x1472; GFX10-NEXT:    s_load_dword s6, s[4:5], 0x2c473; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24474; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0475; GFX10-NEXT:    s_waitcnt lgkmcnt(0)476; GFX10-NEXT:    v_cmp_nlg_f32_e64 s[2:3], s6, 0477; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, s6, s[2:3]478; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]479; GFX10-NEXT:    s_endpgm480;481; GFX11-LABEL: fcmp_sgprX_k0_select_k0_sgprX_f32:482; GFX11:       ; %bb.0:483; GFX11-NEXT:    s_clause 0x1484; GFX11-NEXT:    s_load_b32 s6, s[4:5], 0x2c485; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24486; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0487; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)488; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0489; GFX11-NEXT:    s_waitcnt lgkmcnt(0)490; GFX11-NEXT:    v_cmp_nlg_f32_e64 s[2:3], s6, 0491; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, s6, s[2:3]492; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]493; GFX11-NEXT:    s_endpgm494;495; GFX12-LABEL: fcmp_sgprX_k0_select_k0_sgprX_f32:496; GFX12:       ; %bb.0:497; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24498; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0499; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)500; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0501; GFX12-NEXT:    s_wait_kmcnt 0x0502; GFX12-NEXT:    s_cmp_nlg_f32 s2, 0503; GFX12-NEXT:    s_cselect_b32 s2, s2, 0504; GFX12-NEXT:    v_mov_b32_e32 v1, s2505; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]506; GFX12-NEXT:    s_endpgm507  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1508  %tid.ext = sext i32 %tid to i64509  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext510  %setcc = fcmp one float %x, 0.0511  %select = select i1 %setcc, float 0.0, float %x512  store float %select, ptr addrspace(1) %out.gep513  ret void514}515 516define amdgpu_kernel void @fcmp_sgprX_k0_select_k0_vgprZ_f32(ptr addrspace(1) %out, float %x, ptr addrspace(1) %z.ptr) #0 {517; SI-LABEL: fcmp_sgprX_k0_select_k0_vgprZ_f32:518; SI:       ; %bb.0:519; SI-NEXT:    s_load_dword s6, s[4:5], 0xb520; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd521; SI-NEXT:    s_mov_b32 s3, 0xf000522; SI-NEXT:    s_mov_b32 s2, 0523; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0524; SI-NEXT:    v_mov_b32_e32 v1, 0525; SI-NEXT:    s_waitcnt lgkmcnt(0)526; SI-NEXT:    buffer_load_dword v2, v[0:1], s[0:3], 0 addr64527; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9528; SI-NEXT:    v_cmp_nlg_f32_e64 vcc, s6, 0529; SI-NEXT:    s_waitcnt vmcnt(0)530; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc531; SI-NEXT:    s_waitcnt lgkmcnt(0)532; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64533; SI-NEXT:    s_endpgm534;535; VI-LABEL: fcmp_sgprX_k0_select_k0_vgprZ_f32:536; VI:       ; %bb.0:537; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34538; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0539; VI-NEXT:    s_waitcnt lgkmcnt(0)540; VI-NEXT:    v_mov_b32_e32 v1, s1541; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2542; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc543; VI-NEXT:    flat_load_dword v3, v[0:1]544; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24545; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c546; VI-NEXT:    s_waitcnt lgkmcnt(0)547; VI-NEXT:    v_mov_b32_e32 v1, s1548; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2549; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc550; VI-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0551; VI-NEXT:    s_waitcnt vmcnt(0)552; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v3, vcc553; VI-NEXT:    flat_store_dword v[0:1], v2554; VI-NEXT:    s_endpgm555;556; GFX10-LABEL: fcmp_sgprX_k0_select_k0_vgprZ_f32:557; GFX10:       ; %bb.0:558; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34559; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0560; GFX10-NEXT:    s_waitcnt lgkmcnt(0)561; GFX10-NEXT:    global_load_dword v1, v0, s[0:1]562; GFX10-NEXT:    s_clause 0x1563; GFX10-NEXT:    s_load_dword s2, s[4:5], 0x2c564; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)565; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24566; GFX10-NEXT:    s_waitcnt lgkmcnt(0)567; GFX10-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0568; GFX10-NEXT:    s_waitcnt vmcnt(0)569; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc570; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]571; GFX10-NEXT:    s_endpgm572;573; GFX11-LABEL: fcmp_sgprX_k0_select_k0_vgprZ_f32:574; GFX11:       ; %bb.0:575; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34576; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0577; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)578; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0579; GFX11-NEXT:    s_waitcnt lgkmcnt(0)580; GFX11-NEXT:    global_load_b32 v1, v0, s[0:1]581; GFX11-NEXT:    s_clause 0x1582; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c583; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24584; GFX11-NEXT:    s_waitcnt lgkmcnt(0)585; GFX11-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0586; GFX11-NEXT:    s_waitcnt vmcnt(0)587; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc588; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]589; GFX11-NEXT:    s_endpgm590;591; GFX12-LABEL: fcmp_sgprX_k0_select_k0_vgprZ_f32:592; GFX12:       ; %bb.0:593; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34594; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0595; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)596; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0597; GFX12-NEXT:    s_wait_kmcnt 0x0598; GFX12-NEXT:    global_load_b32 v1, v0, s[0:1]599; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24600; GFX12-NEXT:    s_wait_kmcnt 0x0601; GFX12-NEXT:    s_cmp_nlg_f32 s2, 0602; GFX12-NEXT:    s_cselect_b64 vcc, -1, 0603; GFX12-NEXT:    s_wait_loadcnt 0x0604; GFX12-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc605; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]606; GFX12-NEXT:    s_endpgm607  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1608  %tid.ext = sext i32 %tid to i64609  %z.gep = getelementptr inbounds float, ptr addrspace(1) %z.ptr, i64 %tid.ext610  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext611  %z = load float, ptr addrspace(1) %z.gep612  %setcc = fcmp one float %x, 0.0613  %select = select i1 %setcc, float 0.0, float %z614  store float %select, ptr addrspace(1) %out.gep615  ret void616}617 618define amdgpu_kernel void @fcmp_sgprX_k0_select_k1_vgprZ_f32(ptr addrspace(1) %out, float %x, ptr addrspace(1) %z.ptr) #0 {619; SI-LABEL: fcmp_sgprX_k0_select_k1_vgprZ_f32:620; SI:       ; %bb.0:621; SI-NEXT:    s_load_dword s6, s[4:5], 0xb622; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd623; SI-NEXT:    s_mov_b32 s3, 0xf000624; SI-NEXT:    s_mov_b32 s2, 0625; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0626; SI-NEXT:    v_mov_b32_e32 v1, 0627; SI-NEXT:    s_waitcnt lgkmcnt(0)628; SI-NEXT:    buffer_load_dword v2, v[0:1], s[0:3], 0 addr64629; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9630; SI-NEXT:    v_cmp_nlg_f32_e64 vcc, s6, 0631; SI-NEXT:    s_waitcnt vmcnt(0)632; SI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc633; SI-NEXT:    s_waitcnt lgkmcnt(0)634; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64635; SI-NEXT:    s_endpgm636;637; VI-LABEL: fcmp_sgprX_k0_select_k1_vgprZ_f32:638; VI:       ; %bb.0:639; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34640; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0641; VI-NEXT:    s_waitcnt lgkmcnt(0)642; VI-NEXT:    v_mov_b32_e32 v1, s1643; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2644; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc645; VI-NEXT:    flat_load_dword v3, v[0:1]646; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24647; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c648; VI-NEXT:    s_waitcnt lgkmcnt(0)649; VI-NEXT:    v_mov_b32_e32 v1, s1650; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2651; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc652; VI-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0653; VI-NEXT:    s_waitcnt vmcnt(0)654; VI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc655; VI-NEXT:    flat_store_dword v[0:1], v2656; VI-NEXT:    s_endpgm657;658; GFX10-LABEL: fcmp_sgprX_k0_select_k1_vgprZ_f32:659; GFX10:       ; %bb.0:660; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34661; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0662; GFX10-NEXT:    s_waitcnt lgkmcnt(0)663; GFX10-NEXT:    global_load_dword v1, v0, s[0:1]664; GFX10-NEXT:    s_clause 0x1665; GFX10-NEXT:    s_load_dword s2, s[4:5], 0x2c666; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)667; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24668; GFX10-NEXT:    s_waitcnt lgkmcnt(0)669; GFX10-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0670; GFX10-NEXT:    s_waitcnt vmcnt(0)671; GFX10-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc672; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]673; GFX10-NEXT:    s_endpgm674;675; GFX11-LABEL: fcmp_sgprX_k0_select_k1_vgprZ_f32:676; GFX11:       ; %bb.0:677; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34678; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0679; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)680; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0681; GFX11-NEXT:    s_waitcnt lgkmcnt(0)682; GFX11-NEXT:    global_load_b32 v1, v0, s[0:1]683; GFX11-NEXT:    s_clause 0x1684; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c685; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24686; GFX11-NEXT:    s_waitcnt lgkmcnt(0)687; GFX11-NEXT:    v_cmp_nlg_f32_e64 vcc, s2, 0688; GFX11-NEXT:    s_waitcnt vmcnt(0)689; GFX11-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc690; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]691; GFX11-NEXT:    s_endpgm692;693; GFX12-LABEL: fcmp_sgprX_k0_select_k1_vgprZ_f32:694; GFX12:       ; %bb.0:695; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34696; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0697; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)698; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0699; GFX12-NEXT:    s_wait_kmcnt 0x0700; GFX12-NEXT:    global_load_b32 v1, v0, s[0:1]701; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24702; GFX12-NEXT:    s_wait_kmcnt 0x0703; GFX12-NEXT:    s_cmp_nlg_f32 s2, 0704; GFX12-NEXT:    s_cselect_b64 vcc, -1, 0705; GFX12-NEXT:    s_wait_loadcnt 0x0706; GFX12-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc707; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]708; GFX12-NEXT:    s_endpgm709  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1710  %tid.ext = sext i32 %tid to i64711  %z.gep = getelementptr inbounds float, ptr addrspace(1) %z.ptr, i64 %tid.ext712  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext713  %z = load float, ptr addrspace(1) %z.gep714  %setcc = fcmp one float %x, 0.0715  %select = select i1 %setcc, float 1.0, float %z716  store float %select, ptr addrspace(1) %out.gep717  ret void718}719 720define amdgpu_kernel void @fcmp_vgprX_k0_select_k1_sgprZ_f32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, float %z) #0 {721; SI-LABEL: fcmp_vgprX_k0_select_k1_sgprZ_f32:722; SI:       ; %bb.0:723; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9724; SI-NEXT:    s_load_dword s8, s[4:5], 0xd725; SI-NEXT:    s_mov_b32 s7, 0xf000726; SI-NEXT:    s_mov_b32 s6, 0727; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0728; SI-NEXT:    v_mov_b32_e32 v1, 0729; SI-NEXT:    s_waitcnt lgkmcnt(0)730; SI-NEXT:    s_mov_b64 s[4:5], s[2:3]731; SI-NEXT:    buffer_load_dword v2, v[0:1], s[4:7], 0 addr64732; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]733; SI-NEXT:    v_mov_b32_e32 v3, s8734; SI-NEXT:    s_waitcnt vmcnt(0)735; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v2736; SI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc737; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64738; SI-NEXT:    s_endpgm739;740; VI-LABEL: fcmp_vgprX_k0_select_k1_sgprZ_f32:741; VI:       ; %bb.0:742; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24743; VI-NEXT:    s_load_dword s4, s[4:5], 0x34744; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0745; VI-NEXT:    s_waitcnt lgkmcnt(0)746; VI-NEXT:    v_mov_b32_e32 v1, s3747; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v2748; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc749; VI-NEXT:    flat_load_dword v3, v[0:1]750; VI-NEXT:    v_mov_b32_e32 v1, s1751; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v2752; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc753; VI-NEXT:    v_mov_b32_e32 v4, s4754; VI-NEXT:    s_waitcnt vmcnt(0)755; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v3756; VI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v4, vcc757; VI-NEXT:    flat_store_dword v[0:1], v2758; VI-NEXT:    s_endpgm759;760; GFX10-LABEL: fcmp_vgprX_k0_select_k1_sgprZ_f32:761; GFX10:       ; %bb.0:762; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24763; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0764; GFX10-NEXT:    s_load_dword s4, s[4:5], 0x34765; GFX10-NEXT:    s_waitcnt lgkmcnt(0)766; GFX10-NEXT:    global_load_dword v1, v0, s[2:3]767; GFX10-NEXT:    s_waitcnt vmcnt(0)768; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v1769; GFX10-NEXT:    v_cndmask_b32_e64 v1, 1.0, s4, vcc770; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]771; GFX10-NEXT:    s_endpgm772;773; GFX11-LABEL: fcmp_vgprX_k0_select_k1_sgprZ_f32:774; GFX11:       ; %bb.0:775; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24776; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0777; GFX11-NEXT:    s_load_b32 s4, s[4:5], 0x34778; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)779; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0780; GFX11-NEXT:    s_waitcnt lgkmcnt(0)781; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3]782; GFX11-NEXT:    s_waitcnt vmcnt(0)783; GFX11-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v1784; GFX11-NEXT:    v_cndmask_b32_e64 v1, 1.0, s4, vcc785; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]786; GFX11-NEXT:    s_endpgm787;788; GFX12-LABEL: fcmp_vgprX_k0_select_k1_sgprZ_f32:789; GFX12:       ; %bb.0:790; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24791; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0792; GFX12-NEXT:    s_load_b32 s4, s[4:5], 0x34793; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)794; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0795; GFX12-NEXT:    s_wait_kmcnt 0x0796; GFX12-NEXT:    global_load_b32 v1, v0, s[2:3]797; GFX12-NEXT:    s_wait_loadcnt 0x0798; GFX12-NEXT:    v_cmp_ngt_f32_e32 vcc, 0, v1799; GFX12-NEXT:    v_cndmask_b32_e64 v1, 1.0, s4, vcc800; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]801; GFX12-NEXT:    s_endpgm802  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1803  %tid.ext = sext i32 %tid to i64804  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext805  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext806  %x = load float, ptr addrspace(1) %x.gep807  %setcc = fcmp olt float %x, 0.0808  %select = select i1 %setcc, float 1.0, float %z809  store float %select, ptr addrspace(1) %out.gep810  ret void811}812 813define amdgpu_kernel void @fcmp_vgprX_k0_select_k1_vgprZ_f32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {814; SI-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_f32:815; SI:       ; %bb.0:816; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9817; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd818; SI-NEXT:    s_mov_b32 s11, 0xf000819; SI-NEXT:    s_mov_b32 s10, 0820; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0821; SI-NEXT:    v_mov_b32_e32 v1, 0822; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]823; SI-NEXT:    s_waitcnt lgkmcnt(0)824; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]825; SI-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc826; SI-NEXT:    s_waitcnt vmcnt(0)827; SI-NEXT:    buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc828; SI-NEXT:    s_waitcnt vmcnt(0)829; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]830; SI-NEXT:    v_cmp_le_f32_e32 vcc, 0, v2831; SI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v3, vcc832; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64833; SI-NEXT:    s_endpgm834;835; VI-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_f32:836; VI:       ; %bb.0:837; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24838; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34839; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0840; VI-NEXT:    s_waitcnt lgkmcnt(0)841; VI-NEXT:    v_mov_b32_e32 v1, s3842; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v4843; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc844; VI-NEXT:    v_mov_b32_e32 v3, s5845; VI-NEXT:    v_add_u32_e32 v2, vcc, s4, v4846; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc847; VI-NEXT:    flat_load_dword v5, v[0:1] glc848; VI-NEXT:    s_waitcnt vmcnt(0)849; VI-NEXT:    flat_load_dword v2, v[2:3] glc850; VI-NEXT:    s_waitcnt vmcnt(0)851; VI-NEXT:    v_mov_b32_e32 v1, s1852; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v4853; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc854; VI-NEXT:    v_cmp_le_f32_e32 vcc, 0, v5855; VI-NEXT:    v_cndmask_b32_e32 v2, 1.0, v2, vcc856; VI-NEXT:    flat_store_dword v[0:1], v2857; VI-NEXT:    s_endpgm858;859; GFX10-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_f32:860; GFX10:       ; %bb.0:861; GFX10-NEXT:    s_clause 0x1862; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24863; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34864; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0865; GFX10-NEXT:    s_waitcnt lgkmcnt(0)866; GFX10-NEXT:    global_load_dword v1, v0, s[2:3] glc dlc867; GFX10-NEXT:    s_waitcnt vmcnt(0)868; GFX10-NEXT:    global_load_dword v2, v0, s[6:7] glc dlc869; GFX10-NEXT:    s_waitcnt vmcnt(0)870; GFX10-NEXT:    v_cmp_le_f32_e32 vcc, 0, v1871; GFX10-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc872; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]873; GFX10-NEXT:    s_endpgm874;875; GFX11-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_f32:876; GFX11:       ; %bb.0:877; GFX11-NEXT:    s_clause 0x1878; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24879; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34880; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0881; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)882; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0883; GFX11-NEXT:    s_waitcnt lgkmcnt(0)884; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc885; GFX11-NEXT:    s_waitcnt vmcnt(0)886; GFX11-NEXT:    global_load_b32 v2, v0, s[4:5] glc dlc887; GFX11-NEXT:    s_waitcnt vmcnt(0)888; GFX11-NEXT:    v_cmp_le_f32_e32 vcc, 0, v1889; GFX11-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc890; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]891; GFX11-NEXT:    s_endpgm892;893; GFX12-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_f32:894; GFX12:       ; %bb.0:895; GFX12-NEXT:    s_clause 0x1896; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24897; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34898; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v0899; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)900; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v0901; GFX12-NEXT:    s_wait_kmcnt 0x0902; GFX12-NEXT:    global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS903; GFX12-NEXT:    s_wait_loadcnt 0x0904; GFX12-NEXT:    global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS905; GFX12-NEXT:    s_wait_loadcnt 0x0906; GFX12-NEXT:    v_cmp_le_f32_e32 vcc, 0, v1907; GFX12-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc908; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]909; GFX12-NEXT:    s_endpgm910  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1911  %tid.ext = sext i32 %tid to i64912  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext913  %z.gep = getelementptr inbounds float, ptr addrspace(1) %z.ptr, i64 %tid.ext914  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext915  %x = load volatile float, ptr addrspace(1) %x.gep916  %z = load volatile float, ptr addrspace(1) %z.gep917  %setcc = fcmp ult float %x, 0.0918  %select = select i1 %setcc, float 1.0, float %z919  store float %select, ptr addrspace(1) %out.gep920  ret void921}922 923define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {924; SI-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i32:925; SI:       ; %bb.0:926; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9927; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd928; SI-NEXT:    s_mov_b32 s11, 0xf000929; SI-NEXT:    s_mov_b32 s10, 0930; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0931; SI-NEXT:    v_mov_b32_e32 v1, 0932; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]933; SI-NEXT:    s_waitcnt lgkmcnt(0)934; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]935; SI-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc936; SI-NEXT:    s_waitcnt vmcnt(0)937; SI-NEXT:    buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc938; SI-NEXT:    s_waitcnt vmcnt(0)939; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]940; SI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v2941; SI-NEXT:    v_cndmask_b32_e32 v2, 2, v3, vcc942; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr64943; SI-NEXT:    s_endpgm944;945; VI-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i32:946; VI:       ; %bb.0:947; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24948; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34949; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0950; VI-NEXT:    s_waitcnt lgkmcnt(0)951; VI-NEXT:    v_mov_b32_e32 v1, s3952; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v4953; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc954; VI-NEXT:    v_mov_b32_e32 v3, s5955; VI-NEXT:    v_add_u32_e32 v2, vcc, s4, v4956; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc957; VI-NEXT:    flat_load_dword v5, v[0:1] glc958; VI-NEXT:    s_waitcnt vmcnt(0)959; VI-NEXT:    flat_load_dword v2, v[2:3] glc960; VI-NEXT:    s_waitcnt vmcnt(0)961; VI-NEXT:    v_mov_b32_e32 v1, s1962; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v4963; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc964; VI-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v5965; VI-NEXT:    v_cndmask_b32_e32 v2, 2, v2, vcc966; VI-NEXT:    flat_store_dword v[0:1], v2967; VI-NEXT:    s_endpgm968;969; GFX10-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i32:970; GFX10:       ; %bb.0:971; GFX10-NEXT:    s_clause 0x1972; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24973; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34974; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0975; GFX10-NEXT:    s_waitcnt lgkmcnt(0)976; GFX10-NEXT:    global_load_dword v1, v0, s[2:3] glc dlc977; GFX10-NEXT:    s_waitcnt vmcnt(0)978; GFX10-NEXT:    global_load_dword v2, v0, s[6:7] glc dlc979; GFX10-NEXT:    s_waitcnt vmcnt(0)980; GFX10-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v1981; GFX10-NEXT:    v_cndmask_b32_e32 v1, 2, v2, vcc982; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]983; GFX10-NEXT:    s_endpgm984;985; GFX11-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i32:986; GFX11:       ; %bb.0:987; GFX11-NEXT:    s_clause 0x1988; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24989; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34990; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v0991; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)992; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v0993; GFX11-NEXT:    s_waitcnt lgkmcnt(0)994; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc995; GFX11-NEXT:    s_waitcnt vmcnt(0)996; GFX11-NEXT:    global_load_b32 v2, v0, s[4:5] glc dlc997; GFX11-NEXT:    s_waitcnt vmcnt(0)998; GFX11-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v1999; GFX11-NEXT:    v_cndmask_b32_e32 v1, 2, v2, vcc1000; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]1001; GFX11-NEXT:    s_endpgm1002;1003; GFX12-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i32:1004; GFX12:       ; %bb.0:1005; GFX12-NEXT:    s_clause 0x11006; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241007; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341008; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01009; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1010; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v01011; GFX12-NEXT:    s_wait_kmcnt 0x01012; GFX12-NEXT:    global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS1013; GFX12-NEXT:    s_wait_loadcnt 0x01014; GFX12-NEXT:    global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS1015; GFX12-NEXT:    s_wait_loadcnt 0x01016; GFX12-NEXT:    v_cmp_lt_i32_e32 vcc, -1, v11017; GFX12-NEXT:    v_cndmask_b32_e32 v1, 2, v2, vcc1018; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]1019; GFX12-NEXT:    s_endpgm1020  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11021  %tid.ext = sext i32 %tid to i641022  %x.gep = getelementptr inbounds i32, ptr addrspace(1) %x.ptr, i64 %tid.ext1023  %z.gep = getelementptr inbounds i32, ptr addrspace(1) %z.ptr, i64 %tid.ext1024  %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i64 %tid.ext1025  %x = load volatile i32, ptr addrspace(1) %x.gep1026  %z = load volatile i32, ptr addrspace(1) %z.gep1027  %setcc = icmp slt i32 %x, 01028  %select = select i1 %setcc, i32 2, i32 %z1029  store i32 %select, ptr addrspace(1) %out.gep1030  ret void1031}1032 1033define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i64(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1034; SI-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i64:1035; SI:       ; %bb.0:1036; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91037; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd1038; SI-NEXT:    s_mov_b32 s11, 0xf0001039; SI-NEXT:    s_mov_b32 s10, 01040; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v01041; SI-NEXT:    v_mov_b32_e32 v1, 01042; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]1043; SI-NEXT:    s_waitcnt lgkmcnt(0)1044; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]1045; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64 glc1046; SI-NEXT:    s_waitcnt vmcnt(0)1047; SI-NEXT:    buffer_load_dwordx2 v[4:5], v[0:1], s[4:7], 0 addr64 glc1048; SI-NEXT:    s_waitcnt vmcnt(0)1049; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]1050; SI-NEXT:    v_cmp_lt_i64_e32 vcc, -1, v[2:3]1051; SI-NEXT:    v_cndmask_b32_e32 v3, 0, v5, vcc1052; SI-NEXT:    v_cndmask_b32_e32 v2, 2, v4, vcc1053; SI-NEXT:    buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr641054; SI-NEXT:    s_endpgm1055;1056; VI-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i64:1057; VI:       ; %bb.0:1058; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241059; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341060; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v01061; VI-NEXT:    s_waitcnt lgkmcnt(0)1062; VI-NEXT:    v_mov_b32_e32 v1, s31063; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v41064; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1065; VI-NEXT:    v_mov_b32_e32 v3, s51066; VI-NEXT:    v_add_u32_e32 v2, vcc, s4, v41067; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc1068; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc1069; VI-NEXT:    s_waitcnt vmcnt(0)1070; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3] glc1071; VI-NEXT:    s_waitcnt vmcnt(0)1072; VI-NEXT:    v_mov_b32_e32 v5, s11073; VI-NEXT:    v_add_u32_e32 v4, vcc, s0, v41074; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc1075; VI-NEXT:    v_cmp_lt_i64_e32 vcc, -1, v[0:1]1076; VI-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc1077; VI-NEXT:    v_cndmask_b32_e32 v0, 2, v2, vcc1078; VI-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]1079; VI-NEXT:    s_endpgm1080;1081; GFX10-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i64:1082; GFX10:       ; %bb.0:1083; GFX10-NEXT:    s_clause 0x11084; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241085; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341086; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 3, v01087; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1088; GFX10-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3] glc dlc1089; GFX10-NEXT:    s_waitcnt vmcnt(0)1090; GFX10-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7] glc dlc1091; GFX10-NEXT:    s_waitcnt vmcnt(0)1092; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc, -1, v[0:1]1093; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc1094; GFX10-NEXT:    v_cndmask_b32_e32 v0, 2, v2, vcc1095; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]1096; GFX10-NEXT:    s_endpgm1097;1098; GFX11-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i64:1099; GFX11:       ; %bb.0:1100; GFX11-NEXT:    s_clause 0x11101; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241102; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341103; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01104; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1105; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 3, v01106; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1107; GFX11-NEXT:    global_load_b64 v[0:1], v4, s[2:3] glc dlc1108; GFX11-NEXT:    s_waitcnt vmcnt(0)1109; GFX11-NEXT:    global_load_b64 v[2:3], v4, s[4:5] glc dlc1110; GFX11-NEXT:    s_waitcnt vmcnt(0)1111; GFX11-NEXT:    v_cmp_lt_i64_e32 vcc, -1, v[0:1]1112; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc1113; GFX11-NEXT:    v_cndmask_b32_e32 v0, 2, v2, vcc1114; GFX11-NEXT:    global_store_b64 v4, v[0:1], s[0:1]1115; GFX11-NEXT:    s_endpgm1116;1117; GFX12-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i64:1118; GFX12:       ; %bb.0:1119; GFX12-NEXT:    s_clause 0x11120; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241121; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341122; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01123; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1124; GFX12-NEXT:    v_lshlrev_b32_e32 v4, 3, v01125; GFX12-NEXT:    s_wait_kmcnt 0x01126; GFX12-NEXT:    global_load_b64 v[0:1], v4, s[2:3] scope:SCOPE_SYS1127; GFX12-NEXT:    s_wait_loadcnt 0x01128; GFX12-NEXT:    global_load_b64 v[2:3], v4, s[4:5] scope:SCOPE_SYS1129; GFX12-NEXT:    s_wait_loadcnt 0x01130; GFX12-NEXT:    v_cmp_lt_i64_e32 vcc, -1, v[0:1]1131; GFX12-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc1132; GFX12-NEXT:    v_cndmask_b32_e32 v0, 2, v2, vcc1133; GFX12-NEXT:    global_store_b64 v4, v[0:1], s[0:1]1134; GFX12-NEXT:    s_endpgm1135  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11136  %tid.ext = sext i32 %tid to i641137  %x.gep = getelementptr inbounds i64, ptr addrspace(1) %x.ptr, i64 %tid.ext1138  %z.gep = getelementptr inbounds i64, ptr addrspace(1) %z.ptr, i64 %tid.ext1139  %out.gep = getelementptr inbounds i64, ptr addrspace(1) %out, i64 %tid.ext1140  %x = load volatile i64, ptr addrspace(1) %x.gep1141  %z = load volatile i64, ptr addrspace(1) %z.gep1142  %setcc = icmp slt i64 %x, 01143  %select = select i1 %setcc, i64 2, i64 %z1144  store i64 %select, ptr addrspace(1) %out.gep1145  ret void1146}1147 1148define amdgpu_kernel void @fcmp_vgprX_k0_select_vgprZ_k1_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1149; SI-LABEL: fcmp_vgprX_k0_select_vgprZ_k1_v4f32:1150; SI:       ; %bb.0:1151; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91152; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd1153; SI-NEXT:    s_mov_b32 s11, 0xf0001154; SI-NEXT:    s_mov_b32 s10, 01155; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01156; SI-NEXT:    v_mov_b32_e32 v2, 01157; SI-NEXT:    v_lshlrev_b32_e32 v4, 4, v01158; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]1159; SI-NEXT:    v_mov_b32_e32 v5, v21160; SI-NEXT:    s_waitcnt lgkmcnt(0)1161; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]1162; SI-NEXT:    buffer_load_dword v6, v[1:2], s[8:11], 0 addr64 glc1163; SI-NEXT:    s_waitcnt vmcnt(0)1164; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64 glc1165; SI-NEXT:    s_waitcnt vmcnt(0)1166; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]1167; SI-NEXT:    v_cmp_nge_f32_e32 vcc, 4.0, v61168; SI-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1169; SI-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1170; SI-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1171; SI-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1172; SI-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr641173; SI-NEXT:    s_endpgm1174;1175; VI-LABEL: fcmp_vgprX_k0_select_vgprZ_k1_v4f32:1176; VI:       ; %bb.0:1177; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241178; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341179; VI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01180; VI-NEXT:    v_lshlrev_b32_e32 v5, 4, v01181; VI-NEXT:    s_waitcnt lgkmcnt(0)1182; VI-NEXT:    v_mov_b32_e32 v2, s31183; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v11184; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc1185; VI-NEXT:    v_mov_b32_e32 v0, s51186; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v51187; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc1188; VI-NEXT:    flat_load_dword v6, v[1:2] glc1189; VI-NEXT:    s_waitcnt vmcnt(0)1190; VI-NEXT:    flat_load_dwordx4 v[0:3], v[3:4] glc1191; VI-NEXT:    s_waitcnt vmcnt(0)1192; VI-NEXT:    v_mov_b32_e32 v7, s11193; VI-NEXT:    v_add_u32_e32 v4, vcc, s0, v51194; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc1195; VI-NEXT:    v_cmp_nge_f32_e32 vcc, 4.0, v61196; VI-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1197; VI-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1198; VI-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1199; VI-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1200; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]1201; VI-NEXT:    s_endpgm1202;1203; GFX10-LABEL: fcmp_vgprX_k0_select_vgprZ_k1_v4f32:1204; GFX10:       ; %bb.0:1205; GFX10-NEXT:    s_clause 0x11206; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241207; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341208; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 2, v01209; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 4, v01210; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1211; GFX10-NEXT:    global_load_dword v6, v4, s[2:3] glc dlc1212; GFX10-NEXT:    s_waitcnt vmcnt(0)1213; GFX10-NEXT:    global_load_dwordx4 v[0:3], v5, s[6:7] glc dlc1214; GFX10-NEXT:    s_waitcnt vmcnt(0)1215; GFX10-NEXT:    v_cmp_nge_f32_e32 vcc, 4.0, v61216; GFX10-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1217; GFX10-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1218; GFX10-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1219; GFX10-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1220; GFX10-NEXT:    global_store_dwordx4 v5, v[0:3], s[0:1]1221; GFX10-NEXT:    s_endpgm1222;1223; GFX11-LABEL: fcmp_vgprX_k0_select_vgprZ_k1_v4f32:1224; GFX11:       ; %bb.0:1225; GFX11-NEXT:    s_clause 0x11226; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241227; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341228; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01229; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1230; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 2, v01231; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 4, v01232; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1233; GFX11-NEXT:    global_load_b32 v5, v1, s[2:3] glc dlc1234; GFX11-NEXT:    s_waitcnt vmcnt(0)1235; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[4:5] glc dlc1236; GFX11-NEXT:    s_waitcnt vmcnt(0)1237; GFX11-NEXT:    v_cmp_nge_f32_e32 vcc, 4.0, v51238; GFX11-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1239; GFX11-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1240; GFX11-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1241; GFX11-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1242; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1243; GFX11-NEXT:    s_endpgm1244;1245; GFX12-LABEL: fcmp_vgprX_k0_select_vgprZ_k1_v4f32:1246; GFX12:       ; %bb.0:1247; GFX12-NEXT:    s_clause 0x11248; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241249; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341250; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01251; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1252; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 2, v01253; GFX12-NEXT:    v_lshlrev_b32_e32 v4, 4, v01254; GFX12-NEXT:    s_wait_kmcnt 0x01255; GFX12-NEXT:    global_load_b32 v5, v1, s[2:3] scope:SCOPE_SYS1256; GFX12-NEXT:    s_wait_loadcnt 0x01257; GFX12-NEXT:    global_load_b128 v[0:3], v4, s[4:5] scope:SCOPE_SYS1258; GFX12-NEXT:    s_wait_loadcnt 0x01259; GFX12-NEXT:    v_cmp_nge_f32_e32 vcc, 4.0, v51260; GFX12-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1261; GFX12-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1262; GFX12-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1263; GFX12-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1264; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1265; GFX12-NEXT:    s_endpgm1266  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11267  %tid.ext = sext i32 %tid to i641268  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext1269  %z.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %z.ptr, i64 %tid.ext1270  %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i64 %tid.ext1271  %x = load volatile float, ptr addrspace(1) %x.gep1272  %z = load volatile <4 x float>, ptr addrspace(1) %z.gep1273  %setcc = fcmp ugt float %x, 4.01274  %select = select i1 %setcc, <4 x float> %z, <4 x float> <float 1.0, float 2.0, float -0.5, float 4.0>1275  store <4 x float> %select, ptr addrspace(1) %out.gep1276  ret void1277}1278 1279define amdgpu_kernel void @fcmp_vgprX_k0_select_k1_vgprZ_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1280; SI-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_v4f32:1281; SI:       ; %bb.0:1282; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91283; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd1284; SI-NEXT:    s_mov_b32 s11, 0xf0001285; SI-NEXT:    s_mov_b32 s10, 01286; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01287; SI-NEXT:    v_mov_b32_e32 v2, 01288; SI-NEXT:    v_lshlrev_b32_e32 v4, 4, v01289; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]1290; SI-NEXT:    v_mov_b32_e32 v5, v21291; SI-NEXT:    s_waitcnt lgkmcnt(0)1292; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]1293; SI-NEXT:    buffer_load_dword v6, v[1:2], s[8:11], 0 addr64 glc1294; SI-NEXT:    s_waitcnt vmcnt(0)1295; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64 glc1296; SI-NEXT:    s_waitcnt vmcnt(0)1297; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]1298; SI-NEXT:    v_cmp_ge_f32_e32 vcc, 4.0, v61299; SI-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1300; SI-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1301; SI-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1302; SI-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1303; SI-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr641304; SI-NEXT:    s_endpgm1305;1306; VI-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_v4f32:1307; VI:       ; %bb.0:1308; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241309; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341310; VI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01311; VI-NEXT:    v_lshlrev_b32_e32 v5, 4, v01312; VI-NEXT:    s_waitcnt lgkmcnt(0)1313; VI-NEXT:    v_mov_b32_e32 v2, s31314; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v11315; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc1316; VI-NEXT:    v_mov_b32_e32 v0, s51317; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v51318; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc1319; VI-NEXT:    flat_load_dword v6, v[1:2] glc1320; VI-NEXT:    s_waitcnt vmcnt(0)1321; VI-NEXT:    flat_load_dwordx4 v[0:3], v[3:4] glc1322; VI-NEXT:    s_waitcnt vmcnt(0)1323; VI-NEXT:    v_mov_b32_e32 v7, s11324; VI-NEXT:    v_add_u32_e32 v4, vcc, s0, v51325; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc1326; VI-NEXT:    v_cmp_ge_f32_e32 vcc, 4.0, v61327; VI-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1328; VI-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1329; VI-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1330; VI-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1331; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]1332; VI-NEXT:    s_endpgm1333;1334; GFX10-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_v4f32:1335; GFX10:       ; %bb.0:1336; GFX10-NEXT:    s_clause 0x11337; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241338; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341339; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 2, v01340; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 4, v01341; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1342; GFX10-NEXT:    global_load_dword v6, v4, s[2:3] glc dlc1343; GFX10-NEXT:    s_waitcnt vmcnt(0)1344; GFX10-NEXT:    global_load_dwordx4 v[0:3], v5, s[6:7] glc dlc1345; GFX10-NEXT:    s_waitcnt vmcnt(0)1346; GFX10-NEXT:    v_cmp_ge_f32_e32 vcc, 4.0, v61347; GFX10-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1348; GFX10-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1349; GFX10-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1350; GFX10-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1351; GFX10-NEXT:    global_store_dwordx4 v5, v[0:3], s[0:1]1352; GFX10-NEXT:    s_endpgm1353;1354; GFX11-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_v4f32:1355; GFX11:       ; %bb.0:1356; GFX11-NEXT:    s_clause 0x11357; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241358; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341359; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01360; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1361; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 2, v01362; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 4, v01363; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1364; GFX11-NEXT:    global_load_b32 v5, v1, s[2:3] glc dlc1365; GFX11-NEXT:    s_waitcnt vmcnt(0)1366; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[4:5] glc dlc1367; GFX11-NEXT:    s_waitcnt vmcnt(0)1368; GFX11-NEXT:    v_cmp_ge_f32_e32 vcc, 4.0, v51369; GFX11-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1370; GFX11-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1371; GFX11-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1372; GFX11-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1373; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1374; GFX11-NEXT:    s_endpgm1375;1376; GFX12-LABEL: fcmp_vgprX_k0_select_k1_vgprZ_v4f32:1377; GFX12:       ; %bb.0:1378; GFX12-NEXT:    s_clause 0x11379; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241380; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341381; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01382; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1383; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 2, v01384; GFX12-NEXT:    v_lshlrev_b32_e32 v4, 4, v01385; GFX12-NEXT:    s_wait_kmcnt 0x01386; GFX12-NEXT:    global_load_b32 v5, v1, s[2:3] scope:SCOPE_SYS1387; GFX12-NEXT:    s_wait_loadcnt 0x01388; GFX12-NEXT:    global_load_b128 v[0:3], v4, s[4:5] scope:SCOPE_SYS1389; GFX12-NEXT:    s_wait_loadcnt 0x01390; GFX12-NEXT:    v_cmp_ge_f32_e32 vcc, 4.0, v51391; GFX12-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1392; GFX12-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1393; GFX12-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1394; GFX12-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1395; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1396; GFX12-NEXT:    s_endpgm1397  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11398  %tid.ext = sext i32 %tid to i641399  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext1400  %z.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %z.ptr, i64 %tid.ext1401  %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i64 %tid.ext1402  %x = load volatile float, ptr addrspace(1) %x.gep1403  %z = load volatile <4 x float>, ptr addrspace(1) %z.gep1404  %setcc = fcmp ugt float %x, 4.01405  %select = select i1 %setcc, <4 x float> <float 1.0, float 2.0, float -0.5, float 4.0>, <4 x float> %z1406  store <4 x float> %select, ptr addrspace(1) %out.gep1407  ret void1408}1409 1410; This must be swapped as a vector type before the condition has1411; multiple uses.1412define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1413; SI-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_v4f32:1414; SI:       ; %bb.0:1415; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91416; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd1417; SI-NEXT:    s_mov_b32 s11, 0xf0001418; SI-NEXT:    s_mov_b32 s10, 01419; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01420; SI-NEXT:    v_mov_b32_e32 v2, 01421; SI-NEXT:    v_lshlrev_b32_e32 v4, 4, v01422; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]1423; SI-NEXT:    v_mov_b32_e32 v5, v21424; SI-NEXT:    s_waitcnt lgkmcnt(0)1425; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]1426; SI-NEXT:    buffer_load_dword v6, v[1:2], s[8:11], 0 addr64 glc1427; SI-NEXT:    s_waitcnt vmcnt(0)1428; SI-NEXT:    buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64 glc1429; SI-NEXT:    s_waitcnt vmcnt(0)1430; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]1431; SI-NEXT:    v_cmp_le_f32_e32 vcc, 4.0, v61432; SI-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1433; SI-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1434; SI-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1435; SI-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1436; SI-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr641437; SI-NEXT:    s_endpgm1438;1439; VI-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_v4f32:1440; VI:       ; %bb.0:1441; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241442; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341443; VI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01444; VI-NEXT:    v_lshlrev_b32_e32 v5, 4, v01445; VI-NEXT:    s_waitcnt lgkmcnt(0)1446; VI-NEXT:    v_mov_b32_e32 v2, s31447; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v11448; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc1449; VI-NEXT:    v_mov_b32_e32 v0, s51450; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v51451; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc1452; VI-NEXT:    flat_load_dword v6, v[1:2] glc1453; VI-NEXT:    s_waitcnt vmcnt(0)1454; VI-NEXT:    flat_load_dwordx4 v[0:3], v[3:4] glc1455; VI-NEXT:    s_waitcnt vmcnt(0)1456; VI-NEXT:    v_mov_b32_e32 v7, s11457; VI-NEXT:    v_add_u32_e32 v4, vcc, s0, v51458; VI-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc1459; VI-NEXT:    v_cmp_le_f32_e32 vcc, 4.0, v61460; VI-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1461; VI-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1462; VI-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1463; VI-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1464; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]1465; VI-NEXT:    s_endpgm1466;1467; GFX10-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_v4f32:1468; GFX10:       ; %bb.0:1469; GFX10-NEXT:    s_clause 0x11470; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241471; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341472; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 2, v01473; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 4, v01474; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1475; GFX10-NEXT:    global_load_dword v6, v4, s[2:3] glc dlc1476; GFX10-NEXT:    s_waitcnt vmcnt(0)1477; GFX10-NEXT:    global_load_dwordx4 v[0:3], v5, s[6:7] glc dlc1478; GFX10-NEXT:    s_waitcnt vmcnt(0)1479; GFX10-NEXT:    v_cmp_le_f32_e32 vcc, 4.0, v61480; GFX10-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1481; GFX10-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1482; GFX10-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1483; GFX10-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1484; GFX10-NEXT:    global_store_dwordx4 v5, v[0:3], s[0:1]1485; GFX10-NEXT:    s_endpgm1486;1487; GFX11-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_v4f32:1488; GFX11:       ; %bb.0:1489; GFX11-NEXT:    s_clause 0x11490; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241491; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341492; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01493; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1494; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 2, v01495; GFX11-NEXT:    v_lshlrev_b32_e32 v4, 4, v01496; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1497; GFX11-NEXT:    global_load_b32 v5, v1, s[2:3] glc dlc1498; GFX11-NEXT:    s_waitcnt vmcnt(0)1499; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[4:5] glc dlc1500; GFX11-NEXT:    s_waitcnt vmcnt(0)1501; GFX11-NEXT:    v_cmp_le_f32_e32 vcc, 4.0, v51502; GFX11-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1503; GFX11-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1504; GFX11-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1505; GFX11-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1506; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1507; GFX11-NEXT:    s_endpgm1508;1509; GFX12-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_v4f32:1510; GFX12:       ; %bb.0:1511; GFX12-NEXT:    s_clause 0x11512; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241513; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341514; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01515; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1516; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 2, v01517; GFX12-NEXT:    v_lshlrev_b32_e32 v4, 4, v01518; GFX12-NEXT:    s_wait_kmcnt 0x01519; GFX12-NEXT:    global_load_b32 v5, v1, s[2:3] scope:SCOPE_SYS1520; GFX12-NEXT:    s_wait_loadcnt 0x01521; GFX12-NEXT:    global_load_b128 v[0:3], v4, s[4:5] scope:SCOPE_SYS1522; GFX12-NEXT:    s_wait_loadcnt 0x01523; GFX12-NEXT:    v_cmp_le_f32_e32 vcc, 4.0, v51524; GFX12-NEXT:    v_cndmask_b32_e32 v3, 4.0, v3, vcc1525; GFX12-NEXT:    v_cndmask_b32_e32 v2, -0.5, v2, vcc1526; GFX12-NEXT:    v_cndmask_b32_e32 v1, 2.0, v1, vcc1527; GFX12-NEXT:    v_cndmask_b32_e32 v0, 1.0, v0, vcc1528; GFX12-NEXT:    global_store_b128 v4, v[0:3], s[0:1]1529; GFX12-NEXT:    s_endpgm1530  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11531  %tid.ext = sext i32 %tid to i641532  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext1533  %z.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %z.ptr, i64 %tid.ext1534  %out.gep = getelementptr inbounds <4 x float>, ptr addrspace(1) %out, i64 %tid.ext1535  %x = load volatile float, ptr addrspace(1) %x.gep1536  %z = load volatile <4 x float>, ptr addrspace(1) %z.gep1537  %setcc = fcmp ugt float 4.0, %x1538  %select = select i1 %setcc, <4 x float> <float 1.0, float 2.0, float -0.5, float 4.0>, <4 x float> %z1539  store <4 x float> %select, ptr addrspace(1) %out.gep1540  ret void1541}1542 1543define amdgpu_kernel void @icmp_vgprX_k0_select_k1_vgprZ_i1(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1544; SI-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i1:1545; SI:       ; %bb.0:1546; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x91547; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd1548; SI-NEXT:    v_mov_b32_e32 v1, 01549; SI-NEXT:    s_mov_b32 s7, 0xf0001550; SI-NEXT:    s_mov_b32 s6, 01551; SI-NEXT:    v_lshlrev_b32_e32 v2, 2, v01552; SI-NEXT:    v_mov_b32_e32 v3, v11553; SI-NEXT:    s_mov_b64 s[2:3], s[6:7]1554; SI-NEXT:    s_waitcnt lgkmcnt(0)1555; SI-NEXT:    s_mov_b64 s[4:5], s[10:11]1556; SI-NEXT:    buffer_load_dword v2, v[2:3], s[4:7], 0 addr64 glc1557; SI-NEXT:    s_waitcnt vmcnt(0)1558; SI-NEXT:    buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 glc1559; SI-NEXT:    s_waitcnt vmcnt(0)1560; SI-NEXT:    s_mov_b64 s[10:11], s[6:7]1561; SI-NEXT:    v_and_b32_e32 v3, 1, v31562; SI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v21563; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v31564; SI-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]1565; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]1566; SI-NEXT:    buffer_store_byte v2, v[0:1], s[8:11], 0 addr641567; SI-NEXT:    s_endpgm1568;1569; VI-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i1:1570; VI:       ; %bb.0:1571; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241572; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341573; VI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01574; VI-NEXT:    s_waitcnt lgkmcnt(0)1575; VI-NEXT:    v_mov_b32_e32 v2, s31576; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v11577; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc1578; VI-NEXT:    v_mov_b32_e32 v4, s51579; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v01580; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc1581; VI-NEXT:    flat_load_dword v2, v[1:2] glc1582; VI-NEXT:    s_waitcnt vmcnt(0)1583; VI-NEXT:    flat_load_ubyte v3, v[3:4] glc1584; VI-NEXT:    s_waitcnt vmcnt(0)1585; VI-NEXT:    v_mov_b32_e32 v1, s11586; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v01587; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1588; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v21589; VI-NEXT:    v_and_b32_e32 v3, 1, v31590; VI-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v31591; VI-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]1592; VI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]1593; VI-NEXT:    flat_store_byte v[0:1], v21594; VI-NEXT:    s_endpgm1595;1596; GFX10-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i1:1597; GFX10:       ; %bb.0:1598; GFX10-NEXT:    s_clause 0x11599; GFX10-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x241600; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x341601; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v01602; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1603; GFX10-NEXT:    global_load_dword v2, v1, s[10:11] glc dlc1604; GFX10-NEXT:    s_waitcnt vmcnt(0)1605; GFX10-NEXT:    global_load_ubyte v3, v0, s[0:1] glc dlc1606; GFX10-NEXT:    s_waitcnt vmcnt(0)1607; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v21608; GFX10-NEXT:    v_and_b32_e32 v1, 1, v31609; GFX10-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v11610; GFX10-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]1611; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[0:1]1612; GFX10-NEXT:    global_store_byte v0, v1, s[8:9]1613; GFX10-NEXT:    s_endpgm1614;1615; GFX11-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i1:1616; GFX11:       ; %bb.0:1617; GFX11-NEXT:    s_clause 0x11618; GFX11-NEXT:    s_load_b128 s[8:11], s[4:5], 0x241619; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x341620; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01621; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1622; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 2, v01623; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1624; GFX11-NEXT:    global_load_b32 v1, v1, s[10:11] glc dlc1625; GFX11-NEXT:    s_waitcnt vmcnt(0)1626; GFX11-NEXT:    global_load_u8 v2, v0, s[0:1] glc dlc1627; GFX11-NEXT:    s_waitcnt vmcnt(0)1628; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v11629; GFX11-NEXT:    v_and_b32_e32 v2, 1, v21630; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)1631; GFX11-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v21632; GFX11-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]1633; GFX11-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[0:1]1634; GFX11-NEXT:    global_store_b8 v0, v1, s[8:9]1635; GFX11-NEXT:    s_endpgm1636;1637; GFX12-LABEL: icmp_vgprX_k0_select_k1_vgprZ_i1:1638; GFX12:       ; %bb.0:1639; GFX12-NEXT:    s_clause 0x11640; GFX12-NEXT:    s_load_b128 s[8:11], s[4:5], 0x241641; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x341642; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01643; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1644; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 2, v01645; GFX12-NEXT:    s_wait_kmcnt 0x01646; GFX12-NEXT:    global_load_b32 v1, v1, s[10:11] scope:SCOPE_SYS1647; GFX12-NEXT:    s_wait_loadcnt 0x01648; GFX12-NEXT:    global_load_u8 v2, v0, s[0:1] scope:SCOPE_SYS1649; GFX12-NEXT:    s_wait_loadcnt 0x01650; GFX12-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v11651; GFX12-NEXT:    v_and_b32_e32 v2, 1, v21652; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)1653; GFX12-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v21654; GFX12-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]1655; GFX12-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s[0:1]1656; GFX12-NEXT:    global_store_b8 v0, v1, s[8:9]1657; GFX12-NEXT:    s_endpgm1658  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11659  %tid.ext = sext i32 %tid to i641660  %x.gep = getelementptr inbounds i32, ptr addrspace(1) %x.ptr, i64 %tid.ext1661  %z.gep = getelementptr inbounds i1, ptr addrspace(1) %z.ptr, i64 %tid.ext1662  %out.gep = getelementptr inbounds i1, ptr addrspace(1) %out, i64 %tid.ext1663  %x = load volatile i32, ptr addrspace(1) %x.gep1664  %z = load volatile i1, ptr addrspace(1) %z.gep1665  %setcc = icmp slt i32 %x, 01666  %select = select i1 %setcc, i1 true, i1 %z1667  store i1 %select, ptr addrspace(1) %out.gep1668  ret void1669}1670 1671; Different types compared vs. selected1672define amdgpu_kernel void @fcmp_vgprX_k0_selectf64_k1_vgprZ_f32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1673; SI-LABEL: fcmp_vgprX_k0_selectf64_k1_vgprZ_f32:1674; SI:       ; %bb.0:1675; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91676; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd1677; SI-NEXT:    s_mov_b32 s11, 0xf0001678; SI-NEXT:    s_mov_b32 s10, 01679; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01680; SI-NEXT:    v_mov_b32_e32 v2, 01681; SI-NEXT:    v_lshlrev_b32_e32 v3, 3, v01682; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]1683; SI-NEXT:    v_mov_b32_e32 v4, v21684; SI-NEXT:    s_waitcnt lgkmcnt(0)1685; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]1686; SI-NEXT:    buffer_load_dword v2, v[1:2], s[8:11], 0 addr64 glc1687; SI-NEXT:    s_waitcnt vmcnt(0)1688; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[3:4], s[4:7], 0 addr64 glc1689; SI-NEXT:    s_waitcnt vmcnt(0)1690; SI-NEXT:    v_mov_b32_e32 v5, 0x3ff000001691; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]1692; SI-NEXT:    v_cmp_le_f32_e32 vcc, 0, v21693; SI-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc1694; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc1695; SI-NEXT:    buffer_store_dwordx2 v[0:1], v[3:4], s[0:3], 0 addr641696; SI-NEXT:    s_endpgm1697;1698; VI-LABEL: fcmp_vgprX_k0_selectf64_k1_vgprZ_f32:1699; VI:       ; %bb.0:1700; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241701; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341702; VI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01703; VI-NEXT:    v_lshlrev_b32_e32 v5, 3, v01704; VI-NEXT:    s_waitcnt lgkmcnt(0)1705; VI-NEXT:    v_mov_b32_e32 v2, s31706; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v11707; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc1708; VI-NEXT:    v_mov_b32_e32 v0, s51709; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v51710; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc1711; VI-NEXT:    flat_load_dword v6, v[1:2] glc1712; VI-NEXT:    s_waitcnt vmcnt(0)1713; VI-NEXT:    flat_load_dwordx2 v[0:1], v[3:4] glc1714; VI-NEXT:    s_waitcnt vmcnt(0)1715; VI-NEXT:    v_mov_b32_e32 v3, s11716; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v51717; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc1718; VI-NEXT:    v_mov_b32_e32 v4, 0x3ff000001719; VI-NEXT:    v_cmp_le_f32_e32 vcc, 0, v61720; VI-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc1721; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc1722; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]1723; VI-NEXT:    s_endpgm1724;1725; GFX10-LABEL: fcmp_vgprX_k0_selectf64_k1_vgprZ_f32:1726; GFX10:       ; %bb.0:1727; GFX10-NEXT:    s_clause 0x11728; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241729; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341730; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 2, v01731; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 3, v01732; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1733; GFX10-NEXT:    global_load_dword v4, v2, s[2:3] glc dlc1734; GFX10-NEXT:    s_waitcnt vmcnt(0)1735; GFX10-NEXT:    global_load_dwordx2 v[0:1], v3, s[6:7] glc dlc1736; GFX10-NEXT:    s_waitcnt vmcnt(0)1737; GFX10-NEXT:    v_cmp_le_f32_e32 vcc, 0, v41738; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x3ff00000, v1, vcc1739; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc1740; GFX10-NEXT:    global_store_dwordx2 v3, v[0:1], s[0:1]1741; GFX10-NEXT:    s_endpgm1742;1743; GFX11-LABEL: fcmp_vgprX_k0_selectf64_k1_vgprZ_f32:1744; GFX11:       ; %bb.0:1745; GFX11-NEXT:    s_clause 0x11746; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241747; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341748; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01749; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1750; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 2, v01751; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 3, v01752; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1753; GFX11-NEXT:    global_load_b32 v3, v1, s[2:3] glc dlc1754; GFX11-NEXT:    s_waitcnt vmcnt(0)1755; GFX11-NEXT:    global_load_b64 v[0:1], v2, s[4:5] glc dlc1756; GFX11-NEXT:    s_waitcnt vmcnt(0)1757; GFX11-NEXT:    v_cmp_le_f32_e32 vcc, 0, v31758; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x3ff00000, v1, vcc1759; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc1760; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]1761; GFX11-NEXT:    s_endpgm1762;1763; GFX12-LABEL: fcmp_vgprX_k0_selectf64_k1_vgprZ_f32:1764; GFX12:       ; %bb.0:1765; GFX12-NEXT:    s_clause 0x11766; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241767; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341768; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01769; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1770; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 2, v01771; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 3, v01772; GFX12-NEXT:    s_wait_kmcnt 0x01773; GFX12-NEXT:    global_load_b32 v3, v1, s[2:3] scope:SCOPE_SYS1774; GFX12-NEXT:    s_wait_loadcnt 0x01775; GFX12-NEXT:    global_load_b64 v[0:1], v2, s[4:5] scope:SCOPE_SYS1776; GFX12-NEXT:    s_wait_loadcnt 0x01777; GFX12-NEXT:    v_cmp_le_f32_e32 vcc, 0, v31778; GFX12-NEXT:    v_cndmask_b32_e32 v1, 0x3ff00000, v1, vcc1779; GFX12-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc1780; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]1781; GFX12-NEXT:    s_endpgm1782  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11783  %tid.ext = sext i32 %tid to i641784  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext1785  %z.gep = getelementptr inbounds double, ptr addrspace(1) %z.ptr, i64 %tid.ext1786  %out.gep = getelementptr inbounds double, ptr addrspace(1) %out, i64 %tid.ext1787  %x = load volatile float, ptr addrspace(1) %x.gep1788  %z = load volatile double, ptr addrspace(1) %z.gep1789  %setcc = fcmp ult float %x, 0.01790  %select = select i1 %setcc, double 1.0, double %z1791  store double %select, ptr addrspace(1) %out.gep1792  ret void1793}1794 1795; Different types compared vs. selected1796define amdgpu_kernel void @fcmp_vgprX_k0_selecti64_k1_vgprZ_f32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1797; SI-LABEL: fcmp_vgprX_k0_selecti64_k1_vgprZ_f32:1798; SI:       ; %bb.0:1799; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91800; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd1801; SI-NEXT:    s_mov_b32 s11, 0xf0001802; SI-NEXT:    s_mov_b32 s10, 01803; SI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01804; SI-NEXT:    v_mov_b32_e32 v2, 01805; SI-NEXT:    v_lshlrev_b32_e32 v3, 3, v01806; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]1807; SI-NEXT:    v_mov_b32_e32 v4, v21808; SI-NEXT:    s_waitcnt lgkmcnt(0)1809; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]1810; SI-NEXT:    buffer_load_dword v2, v[1:2], s[8:11], 0 addr64 glc1811; SI-NEXT:    s_waitcnt vmcnt(0)1812; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[3:4], s[4:7], 0 addr64 glc1813; SI-NEXT:    s_waitcnt vmcnt(0)1814; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]1815; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v21816; SI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc1817; SI-NEXT:    v_cndmask_b32_e32 v0, 3, v0, vcc1818; SI-NEXT:    buffer_store_dwordx2 v[0:1], v[3:4], s[0:3], 0 addr641819; SI-NEXT:    s_endpgm1820;1821; VI-LABEL: fcmp_vgprX_k0_selecti64_k1_vgprZ_f32:1822; VI:       ; %bb.0:1823; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241824; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341825; VI-NEXT:    v_lshlrev_b32_e32 v1, 2, v01826; VI-NEXT:    v_lshlrev_b32_e32 v5, 3, v01827; VI-NEXT:    s_waitcnt lgkmcnt(0)1828; VI-NEXT:    v_mov_b32_e32 v2, s31829; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v11830; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc1831; VI-NEXT:    v_mov_b32_e32 v0, s51832; VI-NEXT:    v_add_u32_e32 v3, vcc, s4, v51833; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v0, vcc1834; VI-NEXT:    flat_load_dword v6, v[1:2] glc1835; VI-NEXT:    s_waitcnt vmcnt(0)1836; VI-NEXT:    flat_load_dwordx2 v[0:1], v[3:4] glc1837; VI-NEXT:    s_waitcnt vmcnt(0)1838; VI-NEXT:    v_mov_b32_e32 v3, s11839; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v51840; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc1841; VI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v61842; VI-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc1843; VI-NEXT:    v_cndmask_b32_e32 v0, 3, v0, vcc1844; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]1845; VI-NEXT:    s_endpgm1846;1847; GFX10-LABEL: fcmp_vgprX_k0_selecti64_k1_vgprZ_f32:1848; GFX10:       ; %bb.0:1849; GFX10-NEXT:    s_clause 0x11850; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241851; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341852; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 2, v01853; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 3, v01854; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1855; GFX10-NEXT:    global_load_dword v4, v2, s[2:3] glc dlc1856; GFX10-NEXT:    s_waitcnt vmcnt(0)1857; GFX10-NEXT:    global_load_dwordx2 v[0:1], v3, s[6:7] glc dlc1858; GFX10-NEXT:    s_waitcnt vmcnt(0)1859; GFX10-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v41860; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc1861; GFX10-NEXT:    v_cndmask_b32_e32 v0, 3, v0, vcc1862; GFX10-NEXT:    global_store_dwordx2 v3, v[0:1], s[0:1]1863; GFX10-NEXT:    s_endpgm1864;1865; GFX11-LABEL: fcmp_vgprX_k0_selecti64_k1_vgprZ_f32:1866; GFX11:       ; %bb.0:1867; GFX11-NEXT:    s_clause 0x11868; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241869; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341870; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01871; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1872; GFX11-NEXT:    v_lshlrev_b32_e32 v1, 2, v01873; GFX11-NEXT:    v_lshlrev_b32_e32 v2, 3, v01874; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1875; GFX11-NEXT:    global_load_b32 v3, v1, s[2:3] glc dlc1876; GFX11-NEXT:    s_waitcnt vmcnt(0)1877; GFX11-NEXT:    global_load_b64 v[0:1], v2, s[4:5] glc dlc1878; GFX11-NEXT:    s_waitcnt vmcnt(0)1879; GFX11-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v31880; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc1881; GFX11-NEXT:    v_cndmask_b32_e32 v0, 3, v0, vcc1882; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]1883; GFX11-NEXT:    s_endpgm1884;1885; GFX12-LABEL: fcmp_vgprX_k0_selecti64_k1_vgprZ_f32:1886; GFX12:       ; %bb.0:1887; GFX12-NEXT:    s_clause 0x11888; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241889; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341890; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v01891; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)1892; GFX12-NEXT:    v_lshlrev_b32_e32 v1, 2, v01893; GFX12-NEXT:    v_lshlrev_b32_e32 v2, 3, v01894; GFX12-NEXT:    s_wait_kmcnt 0x01895; GFX12-NEXT:    global_load_b32 v3, v1, s[2:3] scope:SCOPE_SYS1896; GFX12-NEXT:    s_wait_loadcnt 0x01897; GFX12-NEXT:    global_load_b64 v[0:1], v2, s[4:5] scope:SCOPE_SYS1898; GFX12-NEXT:    s_wait_loadcnt 0x01899; GFX12-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v31900; GFX12-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc1901; GFX12-NEXT:    v_cndmask_b32_e32 v0, 3, v0, vcc1902; GFX12-NEXT:    global_store_b64 v2, v[0:1], s[0:1]1903; GFX12-NEXT:    s_endpgm1904  %tid = call i32 @llvm.amdgcn.workitem.id.x() #11905  %tid.ext = sext i32 %tid to i641906  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext1907  %z.gep = getelementptr inbounds i64, ptr addrspace(1) %z.ptr, i64 %tid.ext1908  %out.gep = getelementptr inbounds i64, ptr addrspace(1) %out, i64 %tid.ext1909  %x = load volatile float, ptr addrspace(1) %x.gep1910  %z = load volatile i64, ptr addrspace(1) %z.gep1911  %setcc = fcmp one float %x, 0.01912  %select = select i1 %setcc, i64 3, i64 %z1913  store i64 %select, ptr addrspace(1) %out.gep1914  ret void1915}1916 1917; Different types compared vs. selected1918define amdgpu_kernel void @icmp_vgprX_k0_selectf32_k1_vgprZ_i32(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {1919; SI-LABEL: icmp_vgprX_k0_selectf32_k1_vgprZ_i32:1920; SI:       ; %bb.0:1921; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x91922; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd1923; SI-NEXT:    s_mov_b32 s11, 0xf0001924; SI-NEXT:    s_mov_b32 s10, 01925; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v01926; SI-NEXT:    v_mov_b32_e32 v1, 01927; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]1928; SI-NEXT:    s_waitcnt lgkmcnt(0)1929; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]1930; SI-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc1931; SI-NEXT:    s_waitcnt vmcnt(0)1932; SI-NEXT:    buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc1933; SI-NEXT:    s_waitcnt vmcnt(0)1934; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]1935; SI-NEXT:    v_cmp_gt_u32_e32 vcc, 2, v21936; SI-NEXT:    v_cndmask_b32_e32 v2, 4.0, v3, vcc1937; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr641938; SI-NEXT:    s_endpgm1939;1940; VI-LABEL: icmp_vgprX_k0_selectf32_k1_vgprZ_i32:1941; VI:       ; %bb.0:1942; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241943; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x341944; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v01945; VI-NEXT:    s_waitcnt lgkmcnt(0)1946; VI-NEXT:    v_mov_b32_e32 v1, s31947; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v41948; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1949; VI-NEXT:    v_mov_b32_e32 v3, s51950; VI-NEXT:    v_add_u32_e32 v2, vcc, s4, v41951; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc1952; VI-NEXT:    flat_load_dword v5, v[0:1] glc1953; VI-NEXT:    s_waitcnt vmcnt(0)1954; VI-NEXT:    flat_load_dword v2, v[2:3] glc1955; VI-NEXT:    s_waitcnt vmcnt(0)1956; VI-NEXT:    v_mov_b32_e32 v1, s11957; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v41958; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc1959; VI-NEXT:    v_cmp_gt_u32_e32 vcc, 2, v51960; VI-NEXT:    v_cndmask_b32_e32 v2, 4.0, v2, vcc1961; VI-NEXT:    flat_store_dword v[0:1], v21962; VI-NEXT:    s_endpgm1963;1964; GFX10-LABEL: icmp_vgprX_k0_selectf32_k1_vgprZ_i32:1965; GFX10:       ; %bb.0:1966; GFX10-NEXT:    s_clause 0x11967; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x241968; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x341969; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v01970; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1971; GFX10-NEXT:    global_load_dword v1, v0, s[2:3] glc dlc1972; GFX10-NEXT:    s_waitcnt vmcnt(0)1973; GFX10-NEXT:    global_load_dword v2, v0, s[6:7] glc dlc1974; GFX10-NEXT:    s_waitcnt vmcnt(0)1975; GFX10-NEXT:    v_cmp_gt_u32_e32 vcc, 2, v11976; GFX10-NEXT:    v_cndmask_b32_e32 v1, 4.0, v2, vcc1977; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]1978; GFX10-NEXT:    s_endpgm1979;1980; GFX11-LABEL: icmp_vgprX_k0_selectf32_k1_vgprZ_i32:1981; GFX11:       ; %bb.0:1982; GFX11-NEXT:    s_clause 0x11983; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x241984; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x341985; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v01986; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)1987; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v01988; GFX11-NEXT:    s_waitcnt lgkmcnt(0)1989; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc1990; GFX11-NEXT:    s_waitcnt vmcnt(0)1991; GFX11-NEXT:    global_load_b32 v2, v0, s[4:5] glc dlc1992; GFX11-NEXT:    s_waitcnt vmcnt(0)1993; GFX11-NEXT:    v_cmp_gt_u32_e32 vcc, 2, v11994; GFX11-NEXT:    v_cndmask_b32_e32 v1, 4.0, v2, vcc1995; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]1996; GFX11-NEXT:    s_endpgm1997;1998; GFX12-LABEL: icmp_vgprX_k0_selectf32_k1_vgprZ_i32:1999; GFX12:       ; %bb.0:2000; GFX12-NEXT:    s_clause 0x12001; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x242002; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x342003; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v02004; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)2005; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v02006; GFX12-NEXT:    s_wait_kmcnt 0x02007; GFX12-NEXT:    global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS2008; GFX12-NEXT:    s_wait_loadcnt 0x02009; GFX12-NEXT:    global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS2010; GFX12-NEXT:    s_wait_loadcnt 0x02011; GFX12-NEXT:    v_cmp_gt_u32_e32 vcc, 2, v12012; GFX12-NEXT:    v_cndmask_b32_e32 v1, 4.0, v2, vcc2013; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1]2014; GFX12-NEXT:    s_endpgm2015  %tid = call i32 @llvm.amdgcn.workitem.id.x() #12016  %tid.ext = sext i32 %tid to i642017  %x.gep = getelementptr inbounds i32, ptr addrspace(1) %x.ptr, i64 %tid.ext2018  %z.gep = getelementptr inbounds float, ptr addrspace(1) %z.ptr, i64 %tid.ext2019  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2020  %x = load volatile i32, ptr addrspace(1) %x.gep2021  %z = load volatile float, ptr addrspace(1) %z.gep2022  %setcc = icmp ugt i32 %x, 12023  %select = select i1 %setcc, float 4.0, float %z2024  store float %select, ptr addrspace(1) %out.gep2025  ret void2026}2027 2028; FIXME: Should be able to handle multiple uses2029define amdgpu_kernel void @fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2(ptr addrspace(1) %out, ptr addrspace(1) %x.ptr, ptr addrspace(1) %z.ptr) #0 {2030; SI-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2:2031; SI:       ; %bb.0:2032; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x92033; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd2034; SI-NEXT:    s_mov_b32 s11, 0xf0002035; SI-NEXT:    s_mov_b32 s10, 02036; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v02037; SI-NEXT:    v_mov_b32_e32 v1, 02038; SI-NEXT:    s_mov_b64 s[6:7], s[10:11]2039; SI-NEXT:    s_waitcnt lgkmcnt(0)2040; SI-NEXT:    s_mov_b64 s[8:9], s[2:3]2041; SI-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc2042; SI-NEXT:    s_waitcnt vmcnt(0)2043; SI-NEXT:    buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc2044; SI-NEXT:    s_waitcnt vmcnt(0)2045; SI-NEXT:    s_mov_b64 s[2:3], s[10:11]2046; SI-NEXT:    v_cmp_nle_f32_e32 vcc, 4.0, v22047; SI-NEXT:    v_cndmask_b32_e64 v2, v3, -1.0, vcc2048; SI-NEXT:    v_cndmask_b32_e64 v3, v3, -2.0, vcc2049; SI-NEXT:    buffer_store_dword v2, v[0:1], s[0:3], 0 addr642050; SI-NEXT:    s_waitcnt vmcnt(0)2051; SI-NEXT:    buffer_store_dword v3, v[0:1], s[0:3], 0 addr642052; SI-NEXT:    s_waitcnt vmcnt(0)2053; SI-NEXT:    s_endpgm2054;2055; VI-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2:2056; VI:       ; %bb.0:2057; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x242058; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x342059; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v02060; VI-NEXT:    s_waitcnt lgkmcnt(0)2061; VI-NEXT:    v_mov_b32_e32 v1, s32062; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v42063; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc2064; VI-NEXT:    v_mov_b32_e32 v3, s52065; VI-NEXT:    v_add_u32_e32 v2, vcc, s4, v42066; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc2067; VI-NEXT:    flat_load_dword v5, v[0:1] glc2068; VI-NEXT:    s_waitcnt vmcnt(0)2069; VI-NEXT:    flat_load_dword v2, v[2:3] glc2070; VI-NEXT:    s_waitcnt vmcnt(0)2071; VI-NEXT:    v_mov_b32_e32 v1, s12072; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v42073; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc2074; VI-NEXT:    v_cmp_nle_f32_e32 vcc, 4.0, v52075; VI-NEXT:    v_cndmask_b32_e64 v3, v2, -1.0, vcc2076; VI-NEXT:    v_cndmask_b32_e64 v2, v2, -2.0, vcc2077; VI-NEXT:    flat_store_dword v[0:1], v32078; VI-NEXT:    s_waitcnt vmcnt(0)2079; VI-NEXT:    flat_store_dword v[0:1], v22080; VI-NEXT:    s_waitcnt vmcnt(0)2081; VI-NEXT:    s_endpgm2082;2083; GFX10-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2:2084; GFX10:       ; %bb.0:2085; GFX10-NEXT:    s_clause 0x12086; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x242087; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x342088; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v02089; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2090; GFX10-NEXT:    global_load_dword v1, v0, s[2:3] glc dlc2091; GFX10-NEXT:    s_waitcnt vmcnt(0)2092; GFX10-NEXT:    global_load_dword v2, v0, s[6:7] glc dlc2093; GFX10-NEXT:    s_waitcnt vmcnt(0)2094; GFX10-NEXT:    v_cmp_nle_f32_e32 vcc, 4.0, v12095; GFX10-NEXT:    v_cndmask_b32_e64 v1, v2, -1.0, vcc2096; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, -2.0, vcc2097; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]2098; GFX10-NEXT:    s_waitcnt_vscnt null, 0x02099; GFX10-NEXT:    global_store_dword v0, v2, s[0:1]2100; GFX10-NEXT:    s_waitcnt_vscnt null, 0x02101; GFX10-NEXT:    s_endpgm2102;2103; GFX11-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2:2104; GFX11:       ; %bb.0:2105; GFX11-NEXT:    s_clause 0x12106; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x242107; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x342108; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v02109; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2110; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v02111; GFX11-NEXT:    s_waitcnt lgkmcnt(0)2112; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3] glc dlc2113; GFX11-NEXT:    s_waitcnt vmcnt(0)2114; GFX11-NEXT:    global_load_b32 v2, v0, s[4:5] glc dlc2115; GFX11-NEXT:    s_waitcnt vmcnt(0)2116; GFX11-NEXT:    v_cmp_nle_f32_e32 vcc, 4.0, v12117; GFX11-NEXT:    v_cndmask_b32_e64 v1, v2, -1.0, vcc2118; GFX11-NEXT:    v_cndmask_b32_e64 v2, v2, -2.0, vcc2119; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1] dlc2120; GFX11-NEXT:    s_waitcnt_vscnt null, 0x02121; GFX11-NEXT:    global_store_b32 v0, v2, s[0:1] dlc2122; GFX11-NEXT:    s_waitcnt_vscnt null, 0x02123; GFX11-NEXT:    s_endpgm2124;2125; GFX12-LABEL: fcmp_k0_vgprX_select_k1_vgprZ_f32_cond_use_x2:2126; GFX12:       ; %bb.0:2127; GFX12-NEXT:    s_clause 0x12128; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x242129; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x342130; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v02131; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)2132; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v02133; GFX12-NEXT:    s_wait_kmcnt 0x02134; GFX12-NEXT:    global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS2135; GFX12-NEXT:    s_wait_loadcnt 0x02136; GFX12-NEXT:    global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS2137; GFX12-NEXT:    s_wait_loadcnt 0x02138; GFX12-NEXT:    v_cmp_nle_f32_e32 vcc, 4.0, v12139; GFX12-NEXT:    v_cndmask_b32_e64 v1, v2, -1.0, vcc2140; GFX12-NEXT:    v_cndmask_b32_e64 v2, v2, -2.0, vcc2141; GFX12-NEXT:    global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS2142; GFX12-NEXT:    s_wait_storecnt 0x02143; GFX12-NEXT:    global_store_b32 v0, v2, s[0:1] scope:SCOPE_SYS2144; GFX12-NEXT:    s_wait_storecnt 0x02145; GFX12-NEXT:    s_endpgm2146  %tid = call i32 @llvm.amdgcn.workitem.id.x() #12147  %tid.ext = sext i32 %tid to i642148  %x.gep = getelementptr inbounds float, ptr addrspace(1) %x.ptr, i64 %tid.ext2149  %z.gep = getelementptr inbounds float, ptr addrspace(1) %z.ptr, i64 %tid.ext2150  %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext2151  %x = load volatile float, ptr addrspace(1) %x.gep2152  %z = load volatile float, ptr addrspace(1) %z.gep2153  %setcc = fcmp ugt float 4.0, %x2154  %select0 = select i1 %setcc, float -1.0, float %z2155  %select1 = select i1 %setcc, float -2.0, float %z2156  store volatile float %select0, ptr addrspace(1) %out.gep2157  store volatile float %select1, ptr addrspace(1) %out.gep2158  ret void2159}2160 2161; Source modifiers abs/neg only work for f322162define amdgpu_kernel void @v_cndmask_abs_neg_f16(ptr addrspace(1) %out, i32 %c, ptr addrspace(1) %fptr) #0 {2163; SI-LABEL: v_cndmask_abs_neg_f16:2164; SI:       ; %bb.0:2165; SI-NEXT:    s_load_dword s8, s[4:5], 0xb2166; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd2167; SI-NEXT:    s_mov_b32 s7, 0xf0002168; SI-NEXT:    s_mov_b32 s2, 02169; SI-NEXT:    v_lshlrev_b32_e32 v0, 1, v02170; SI-NEXT:    v_mov_b32_e32 v1, 02171; SI-NEXT:    s_mov_b32 s3, s72172; SI-NEXT:    s_waitcnt lgkmcnt(0)2173; SI-NEXT:    buffer_load_ushort v0, v[0:1], s[0:3], 0 addr642174; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x92175; SI-NEXT:    s_mov_b32 s6, -12176; SI-NEXT:    s_cmp_lg_u32 s8, 02177; SI-NEXT:    s_waitcnt vmcnt(0)2178; SI-NEXT:    v_cvt_f32_f16_e64 v1, |v0|2179; SI-NEXT:    v_cvt_f32_f16_e64 v0, -v02180; SI-NEXT:    s_cselect_b64 vcc, -1, 02181; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc2182; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02183; SI-NEXT:    s_waitcnt lgkmcnt(0)2184; SI-NEXT:    buffer_store_short v0, off, s[4:7], 02185; SI-NEXT:    s_endpgm2186;2187; VI-LABEL: v_cndmask_abs_neg_f16:2188; VI:       ; %bb.0:2189; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x342190; VI-NEXT:    v_lshlrev_b32_e32 v0, 1, v02191; VI-NEXT:    s_waitcnt lgkmcnt(0)2192; VI-NEXT:    v_mov_b32_e32 v1, s12193; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v02194; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc2195; VI-NEXT:    flat_load_ushort v0, v[0:1]2196; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c2197; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242198; VI-NEXT:    s_waitcnt lgkmcnt(0)2199; VI-NEXT:    s_cmp_lg_u32 s2, 02200; VI-NEXT:    s_cselect_b64 vcc, -1, 02201; VI-NEXT:    s_waitcnt vmcnt(0)2202; VI-NEXT:    v_and_b32_e32 v1, 0x7fff, v02203; VI-NEXT:    v_xor_b32_e32 v0, 0x8000, v02204; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc2205; VI-NEXT:    v_mov_b32_e32 v0, s02206; VI-NEXT:    v_mov_b32_e32 v1, s12207; VI-NEXT:    flat_store_short v[0:1], v22208; VI-NEXT:    s_endpgm2209;2210; GFX10-LABEL: v_cndmask_abs_neg_f16:2211; GFX10:       ; %bb.0:2212; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x342213; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v02214; GFX10-NEXT:    v_mov_b32_e32 v2, 02215; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2216; GFX10-NEXT:    global_load_ushort v0, v0, s[0:1]2217; GFX10-NEXT:    s_clause 0x12218; GFX10-NEXT:    s_load_dword s2, s[4:5], 0x2c2219; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)2220; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242221; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2222; GFX10-NEXT:    s_cmp_lg_u32 s2, 02223; GFX10-NEXT:    s_cselect_b64 vcc, -1, 02224; GFX10-NEXT:    s_waitcnt vmcnt(0)2225; GFX10-NEXT:    v_and_b32_e32 v1, 0x7fff, v02226; GFX10-NEXT:    v_xor_b32_e32 v0, 0x8000, v02227; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc2228; GFX10-NEXT:    global_store_short v2, v0, s[0:1]2229; GFX10-NEXT:    s_endpgm2230;2231; GFX11-TRUE16-LABEL: v_cndmask_abs_neg_f16:2232; GFX11-TRUE16:       ; %bb.0:2233; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342234; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v02235; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 02236; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2237; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v02238; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)2239; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[0:1]2240; GFX11-TRUE16-NEXT:    s_clause 0x12241; GFX11-TRUE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c2242; GFX11-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x242243; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)2244; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s2, 02245; GFX11-TRUE16-NEXT:    s_cselect_b64 s[2:3], -1, 02246; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)2247; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0x7fff, v0.l2248; GFX11-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l2249; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2250; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, s[2:3]2251; GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]2252; GFX11-TRUE16-NEXT:    s_endpgm2253;2254; GFX11-FAKE16-LABEL: v_cndmask_abs_neg_f16:2255; GFX11-FAKE16:       ; %bb.0:2256; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342257; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v02258; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 02259; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2260; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v02261; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)2262; GFX11-FAKE16-NEXT:    global_load_u16 v0, v0, s[0:1]2263; GFX11-FAKE16-NEXT:    s_clause 0x12264; GFX11-FAKE16-NEXT:    s_load_b32 s2, s[4:5], 0x2c2265; GFX11-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x242266; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)2267; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s2, 02268; GFX11-FAKE16-NEXT:    s_cselect_b64 vcc, -1, 02269; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)2270; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v02271; GFX11-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v02272; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2273; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc2274; GFX11-FAKE16-NEXT:    global_store_b16 v2, v0, s[0:1]2275; GFX11-FAKE16-NEXT:    s_endpgm2276;2277; GFX12-TRUE16-LABEL: v_cndmask_abs_neg_f16:2278; GFX12-TRUE16:       ; %bb.0:2279; GFX12-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342280; GFX12-TRUE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v02281; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v1, 02282; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2283; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v02284; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x02285; GFX12-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[0:1]2286; GFX12-TRUE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x242287; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x02288; GFX12-TRUE16-NEXT:    s_cmp_lg_u32 s2, 02289; GFX12-TRUE16-NEXT:    s_cselect_b64 s[2:3], -1, 02290; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x02291; GFX12-TRUE16-NEXT:    v_and_b16 v0.h, 0x7fff, v0.l2292; GFX12-TRUE16-NEXT:    v_xor_b16 v0.l, 0x8000, v0.l2293; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2294; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, s[2:3]2295; GFX12-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]2296; GFX12-TRUE16-NEXT:    s_endpgm2297;2298; GFX12-FAKE16-LABEL: v_cndmask_abs_neg_f16:2299; GFX12-FAKE16:       ; %bb.0:2300; GFX12-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342301; GFX12-FAKE16-NEXT:    v_and_b32_e32 v0, 0x3ff, v02302; GFX12-FAKE16-NEXT:    v_mov_b32_e32 v2, 02303; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2304; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 1, v02305; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x02306; GFX12-FAKE16-NEXT:    global_load_u16 v0, v0, s[0:1]2307; GFX12-FAKE16-NEXT:    s_load_b96 s[0:2], s[4:5], 0x242308; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x02309; GFX12-FAKE16-NEXT:    s_cmp_lg_u32 s2, 02310; GFX12-FAKE16-NEXT:    s_cselect_b64 vcc, -1, 02311; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x02312; GFX12-FAKE16-NEXT:    v_and_b32_e32 v1, 0x7fff, v02313; GFX12-FAKE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v02314; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2315; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc2316; GFX12-FAKE16-NEXT:    global_store_b16 v2, v0, s[0:1]2317; GFX12-FAKE16-NEXT:    s_endpgm2318  %idx = call i32 @llvm.amdgcn.workitem.id.x() #12319  %f.gep = getelementptr half, ptr addrspace(1) %fptr, i32 %idx2320  %f = load half, ptr addrspace(1) %f.gep2321  %f.abs = call half @llvm.fabs.f16(half %f)2322  %f.neg = fneg half %f2323  %setcc = icmp ne i32 %c, 02324  %select = select i1 %setcc, half %f.abs, half %f.neg2325  store half %select, ptr addrspace(1) %out2326  ret void2327}2328 2329define amdgpu_kernel void @v_cndmask_abs_neg_f32(ptr addrspace(1) %out, i32 %c, ptr addrspace(1) %fptr) #0 {2330; SI-LABEL: v_cndmask_abs_neg_f32:2331; SI:       ; %bb.0:2332; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x92333; SI-NEXT:    s_load_dword s8, s[4:5], 0xb2334; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd2335; SI-NEXT:    s_mov_b32 s3, 0xf0002336; SI-NEXT:    s_mov_b32 s6, 02337; SI-NEXT:    s_mov_b32 s7, s32338; SI-NEXT:    v_lshlrev_b32_e32 v0, 2, v02339; SI-NEXT:    v_mov_b32_e32 v1, 02340; SI-NEXT:    s_waitcnt lgkmcnt(0)2341; SI-NEXT:    buffer_load_dword v0, v[0:1], s[4:7], 0 addr642342; SI-NEXT:    s_mov_b32 s2, -12343; SI-NEXT:    s_cmp_lg_u32 s8, 02344; SI-NEXT:    s_cselect_b64 s[4:5], -1, 02345; SI-NEXT:    s_waitcnt vmcnt(0)2346; SI-NEXT:    v_cndmask_b32_e64 v0, -v0, |v0|, s[4:5]2347; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 02348; SI-NEXT:    s_endpgm2349;2350; VI-LABEL: v_cndmask_abs_neg_f32:2351; VI:       ; %bb.0:2352; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x342353; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v02354; VI-NEXT:    s_waitcnt lgkmcnt(0)2355; VI-NEXT:    v_mov_b32_e32 v1, s12356; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v02357; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc2358; VI-NEXT:    flat_load_dword v0, v[0:1]2359; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c2360; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242361; VI-NEXT:    s_waitcnt lgkmcnt(0)2362; VI-NEXT:    s_cmp_lg_u32 s2, 02363; VI-NEXT:    s_cselect_b64 s[2:3], -1, 02364; VI-NEXT:    s_waitcnt vmcnt(0)2365; VI-NEXT:    v_cndmask_b32_e64 v2, -v0, |v0|, s[2:3]2366; VI-NEXT:    v_mov_b32_e32 v0, s02367; VI-NEXT:    v_mov_b32_e32 v1, s12368; VI-NEXT:    flat_store_dword v[0:1], v22369; VI-NEXT:    s_endpgm2370;2371; GFX10-LABEL: v_cndmask_abs_neg_f32:2372; GFX10:       ; %bb.0:2373; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x342374; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v02375; GFX10-NEXT:    v_mov_b32_e32 v1, 02376; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2377; GFX10-NEXT:    global_load_dword v0, v0, s[0:1]2378; GFX10-NEXT:    s_clause 0x12379; GFX10-NEXT:    s_load_dword s2, s[4:5], 0x2c2380; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)2381; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242382; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2383; GFX10-NEXT:    s_cmp_lg_u32 s2, 02384; GFX10-NEXT:    s_cselect_b64 s[2:3], -1, 02385; GFX10-NEXT:    s_waitcnt vmcnt(0)2386; GFX10-NEXT:    v_cndmask_b32_e64 v0, -v0, |v0|, s[2:3]2387; GFX10-NEXT:    global_store_dword v1, v0, s[0:1]2388; GFX10-NEXT:    s_endpgm2389;2390; GFX11-LABEL: v_cndmask_abs_neg_f32:2391; GFX11:       ; %bb.0:2392; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342393; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v02394; GFX11-NEXT:    v_mov_b32_e32 v1, 02395; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)2396; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 2, v02397; GFX11-NEXT:    s_waitcnt lgkmcnt(0)2398; GFX11-NEXT:    global_load_b32 v0, v0, s[0:1]2399; GFX11-NEXT:    s_clause 0x12400; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c2401; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x242402; GFX11-NEXT:    s_waitcnt lgkmcnt(0)2403; GFX11-NEXT:    s_cmp_lg_u32 s2, 02404; GFX11-NEXT:    s_cselect_b64 s[2:3], -1, 02405; GFX11-NEXT:    s_waitcnt vmcnt(0)2406; GFX11-NEXT:    v_cndmask_b32_e64 v0, -v0, |v0|, s[2:3]2407; GFX11-NEXT:    global_store_b32 v1, v0, s[0:1]2408; GFX11-NEXT:    s_endpgm2409;2410; GFX12-LABEL: v_cndmask_abs_neg_f32:2411; GFX12:       ; %bb.0:2412; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342413; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v02414; GFX12-NEXT:    v_mov_b32_e32 v1, 02415; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)2416; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 2, v02417; GFX12-NEXT:    s_wait_kmcnt 0x02418; GFX12-NEXT:    global_load_b32 v0, v0, s[0:1]2419; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x242420; GFX12-NEXT:    s_wait_kmcnt 0x02421; GFX12-NEXT:    s_cmp_lg_u32 s2, 02422; GFX12-NEXT:    s_cselect_b64 s[2:3], -1, 02423; GFX12-NEXT:    s_wait_loadcnt 0x02424; GFX12-NEXT:    v_cndmask_b32_e64 v0, -v0, |v0|, s[2:3]2425; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]2426; GFX12-NEXT:    s_endpgm2427  %idx = call i32 @llvm.amdgcn.workitem.id.x() #12428  %f.gep = getelementptr float, ptr addrspace(1) %fptr, i32 %idx2429  %f = load float, ptr addrspace(1) %f.gep2430  %f.abs = call float @llvm.fabs.f32(float %f)2431  %f.neg = fneg float %f2432  %setcc = icmp ne i32 %c, 02433  %select = select i1 %setcc, float %f.abs, float %f.neg2434  store float %select, ptr addrspace(1) %out2435  ret void2436}2437 2438define amdgpu_kernel void @v_cndmask_abs_neg_f64(ptr addrspace(1) %out, i32 %c, ptr addrspace(1) %fptr) #0 {2439; SI-LABEL: v_cndmask_abs_neg_f64:2440; SI:       ; %bb.0:2441; SI-NEXT:    s_load_dword s8, s[4:5], 0xb2442; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd2443; SI-NEXT:    s_mov_b32 s7, 0xf0002444; SI-NEXT:    s_mov_b32 s2, 02445; SI-NEXT:    v_lshlrev_b32_e32 v0, 3, v02446; SI-NEXT:    v_mov_b32_e32 v1, 02447; SI-NEXT:    s_mov_b32 s3, s72448; SI-NEXT:    s_waitcnt lgkmcnt(0)2449; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 addr642450; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x92451; SI-NEXT:    s_mov_b32 s6, -12452; SI-NEXT:    s_cmp_lg_u32 s8, 02453; SI-NEXT:    s_waitcnt vmcnt(0)2454; SI-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v12455; SI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v12456; SI-NEXT:    s_cselect_b64 vcc, -1, 02457; SI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc2458; SI-NEXT:    s_waitcnt lgkmcnt(0)2459; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 02460; SI-NEXT:    s_endpgm2461;2462; VI-LABEL: v_cndmask_abs_neg_f64:2463; VI:       ; %bb.0:2464; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x342465; VI-NEXT:    v_lshlrev_b32_e32 v0, 3, v02466; VI-NEXT:    s_waitcnt lgkmcnt(0)2467; VI-NEXT:    v_mov_b32_e32 v1, s12468; VI-NEXT:    v_add_u32_e32 v0, vcc, s0, v02469; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc2470; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]2471; VI-NEXT:    s_load_dword s2, s[4:5], 0x2c2472; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242473; VI-NEXT:    s_waitcnt lgkmcnt(0)2474; VI-NEXT:    s_cmp_lg_u32 s2, 02475; VI-NEXT:    s_cselect_b64 vcc, -1, 02476; VI-NEXT:    s_waitcnt vmcnt(0)2477; VI-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v12478; VI-NEXT:    v_xor_b32_e32 v1, 0x80000000, v12479; VI-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc2480; VI-NEXT:    v_mov_b32_e32 v3, s12481; VI-NEXT:    v_mov_b32_e32 v2, s02482; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]2483; VI-NEXT:    s_endpgm2484;2485; GFX10-LABEL: v_cndmask_abs_neg_f64:2486; GFX10:       ; %bb.0:2487; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x342488; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 3, v02489; GFX10-NEXT:    v_mov_b32_e32 v3, 02490; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2491; GFX10-NEXT:    global_load_dwordx2 v[0:1], v0, s[0:1]2492; GFX10-NEXT:    s_clause 0x12493; GFX10-NEXT:    s_load_dword s2, s[4:5], 0x2c2494; GFX10-NEXT:    s_waitcnt_depctr depctr_vm_vsrc(0)2495; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x242496; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2497; GFX10-NEXT:    s_cmp_lg_u32 s2, 02498; GFX10-NEXT:    s_cselect_b64 vcc, -1, 02499; GFX10-NEXT:    s_waitcnt vmcnt(0)2500; GFX10-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v12501; GFX10-NEXT:    v_xor_b32_e32 v1, 0x80000000, v12502; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc2503; GFX10-NEXT:    global_store_dwordx2 v3, v[0:1], s[0:1]2504; GFX10-NEXT:    s_endpgm2505;2506; GFX11-LABEL: v_cndmask_abs_neg_f64:2507; GFX11:       ; %bb.0:2508; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342509; GFX11-NEXT:    v_and_b32_e32 v0, 0x3ff, v02510; GFX11-NEXT:    v_mov_b32_e32 v3, 02511; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)2512; GFX11-NEXT:    v_lshlrev_b32_e32 v0, 3, v02513; GFX11-NEXT:    s_waitcnt lgkmcnt(0)2514; GFX11-NEXT:    global_load_b64 v[0:1], v0, s[0:1]2515; GFX11-NEXT:    s_clause 0x12516; GFX11-NEXT:    s_load_b32 s2, s[4:5], 0x2c2517; GFX11-NEXT:    s_load_b64 s[0:1], s[4:5], 0x242518; GFX11-NEXT:    s_waitcnt lgkmcnt(0)2519; GFX11-NEXT:    s_cmp_lg_u32 s2, 02520; GFX11-NEXT:    s_cselect_b64 vcc, -1, 02521; GFX11-NEXT:    s_waitcnt vmcnt(0)2522; GFX11-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v12523; GFX11-NEXT:    v_xor_b32_e32 v1, 0x80000000, v12524; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)2525; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc2526; GFX11-NEXT:    global_store_b64 v3, v[0:1], s[0:1]2527; GFX11-NEXT:    s_endpgm2528;2529; GFX12-LABEL: v_cndmask_abs_neg_f64:2530; GFX12:       ; %bb.0:2531; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x342532; GFX12-NEXT:    v_and_b32_e32 v0, 0x3ff, v02533; GFX12-NEXT:    v_mov_b32_e32 v3, 02534; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)2535; GFX12-NEXT:    v_lshlrev_b32_e32 v0, 3, v02536; GFX12-NEXT:    s_wait_kmcnt 0x02537; GFX12-NEXT:    global_load_b64 v[0:1], v0, s[0:1]2538; GFX12-NEXT:    s_load_b96 s[0:2], s[4:5], 0x242539; GFX12-NEXT:    s_wait_kmcnt 0x02540; GFX12-NEXT:    s_cmp_lg_u32 s2, 02541; GFX12-NEXT:    s_cselect_b64 vcc, -1, 02542; GFX12-NEXT:    s_wait_loadcnt 0x02543; GFX12-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v12544; GFX12-NEXT:    v_xor_b32_e32 v1, 0x80000000, v12545; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)2546; GFX12-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc2547; GFX12-NEXT:    global_store_b64 v3, v[0:1], s[0:1]2548; GFX12-NEXT:    s_endpgm2549  %idx = call i32 @llvm.amdgcn.workitem.id.x() #12550  %f.gep = getelementptr double, ptr addrspace(1) %fptr, i32 %idx2551  %f = load double, ptr addrspace(1) %f.gep2552  %f.abs = call double @llvm.fabs.f64(double %f)2553  %f.neg = fneg double %f2554  %setcc = icmp ne i32 %c, 02555  %select = select i1 %setcc, double %f.abs, double %f.neg2556  store double %select, ptr addrspace(1) %out2557  ret void2558}2559 2560attributes #0 = { nounwind }2561attributes #1 = { nounwind readnone }2562