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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=SI %s2; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=VI %s3 4; GCN-LABEL: {{^}}mac_f16:5; GCN: {{buffer|flat}}_load_ushort v[[A_F16:[0-9]+]]6; GCN: {{buffer|flat}}_load_ushort v[[B_F16:[0-9]+]]7; GCN: {{buffer|flat}}_load_ushort v[[C_F16:[0-9]+]]8; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]9; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]10; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]11; SI: v_mac_f32_e32 v[[C_F32]], v[[A_F32]], v[[B_F32]]12; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]13; SI: buffer_store_short v[[R_F16]]14; VI: v_mac_f16_e32 v[[C_F16]], v[[A_F16]], v[[B_F16]]15; VI: buffer_store_short v[[C_F16]]16; GCN: s_endpgm17define amdgpu_kernel void @mac_f16(18 ptr addrspace(1) %r,19 ptr addrspace(1) %a,20 ptr addrspace(1) %b,21 ptr addrspace(1) %c) #0 {22entry:23 %a.val = load half, ptr addrspace(1) %a24 %b.val = load half, ptr addrspace(1) %b25 %c.val = load half, ptr addrspace(1) %c26 27 %t.val = fmul half %a.val, %b.val28 %r.val = fadd half %t.val, %c.val29 30 store half %r.val, ptr addrspace(1) %r31 ret void32}33 34; GCN-LABEL: {{^}}mac_f16_same_add:35; SI: v_mad_f32 v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}}, [[ADD:v[0-9]+]]36; SI: v_mac_f32_e32 [[ADD]], v{{[0-9]+}}, v{{[0-9]+}}37 38; VI: v_mad_f16 v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}}, [[ADD:v[0-9]+]]39; VI: v_mac_f16_e32 [[ADD]], v{{[0-9]+}}, v{{[0-9]+}}40; GCN: s_endpgm41define amdgpu_kernel void @mac_f16_same_add(42 ptr addrspace(1) %r0,43 ptr addrspace(1) %r1,44 ptr addrspace(1) %a,45 ptr addrspace(1) %b,46 ptr addrspace(1) %c,47 ptr addrspace(1) %d,48 ptr addrspace(1) %e) #0 {49entry:50 %a.val = load half, ptr addrspace(1) %a51 %b.val = load half, ptr addrspace(1) %b52 %c.val = load half, ptr addrspace(1) %c53 %d.val = load half, ptr addrspace(1) %d54 %e.val = load half, ptr addrspace(1) %e55 56 %t0.val = fmul half %a.val, %b.val57 %r0.val = fadd half %t0.val, %c.val58 59 %t1.val = fmul half %d.val, %e.val60 %r1.val = fadd half %t1.val, %c.val61 62 store half %r0.val, ptr addrspace(1) %r063 store half %r1.val, ptr addrspace(1) %r164 ret void65}66 67; GCN-LABEL: {{^}}mac_f16_neg_a:68; SI: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], v{{[0-9]+}}69; SI: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], v{{[0-9]+}}70; SI: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], v{{[0-9]+}}71; SI: v_mad_f32 v{{[0-9]+}}, -[[CVT_A]], [[CVT_B]], [[CVT_C]]72 73; VI-NOT: v_mac_f1674; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}75; GCN: s_endpgm76define amdgpu_kernel void @mac_f16_neg_a(77 ptr addrspace(1) %r,78 ptr addrspace(1) %a,79 ptr addrspace(1) %b,80 ptr addrspace(1) %c) #0 {81entry:82 %a.val = load half, ptr addrspace(1) %a83 %b.val = load half, ptr addrspace(1) %b84 %c.val = load half, ptr addrspace(1) %c85 86 %a.neg = fneg half %a.val87 %t.val = fmul half %a.neg, %b.val88 %r.val = fadd half %t.val, %c.val89 90 store half %r.val, ptr addrspace(1) %r91 ret void92}93 94; GCN-LABEL: {{^}}mac_f16_neg_b:95; SI: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], v{{[0-9]+}}96; SI: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], v{{[0-9]+}}97; SI: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], v{{[0-9]+}}98; SI: v_mad_f32 v{{[0-9]+}}, -[[CVT_A]], [[CVT_B]], [[CVT_C]]99 100; VI-NOT: v_mac_f16101; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}102; GCN: s_endpgm103define amdgpu_kernel void @mac_f16_neg_b(104 ptr addrspace(1) %r,105 ptr addrspace(1) %a,106 ptr addrspace(1) %b,107 ptr addrspace(1) %c) #0 {108entry:109 %a.val = load half, ptr addrspace(1) %a110 %b.val = load half, ptr addrspace(1) %b111 %c.val = load half, ptr addrspace(1) %c112 113 %b.neg = fneg half %b.val114 %t.val = fmul half %a.val, %b.neg115 %r.val = fadd half %t.val, %c.val116 117 store half %r.val, ptr addrspace(1) %r118 ret void119}120 121; GCN-LABEL: {{^}}mac_f16_neg_c:122; SI: v_cvt_f32_f16_e32123; SI: v_cvt_f32_f16_e32124; SI: v_cvt_f32_f16_e32125; SI: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}126 127; VI-NOT: v_mac_f16128; VI: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}129; GCN: s_endpgm130define amdgpu_kernel void @mac_f16_neg_c(131 ptr addrspace(1) %r,132 ptr addrspace(1) %a,133 ptr addrspace(1) %b,134 ptr addrspace(1) %c) #0 {135entry:136 %a.val = load half, ptr addrspace(1) %a137 %b.val = load half, ptr addrspace(1) %b138 %c.val = load half, ptr addrspace(1) %c139 140 %c.neg = fneg half %c.val141 %t.val = fmul half %a.val, %b.val142 %r.val = fadd half %t.val, %c.neg143 144 store half %r.val, ptr addrspace(1) %r145 ret void146}147 148; GCN-LABEL: {{^}}mac_f16_neg_a_safe_fp_math:149; SI: v_sub_f32_e32 v[[NEG_A:[0-9]+]], 0, v{{[0-9]+}}150; SI: v_mac_f32_e32 v{{[0-9]+}}, v[[NEG_A]], v{{[0-9]+}}151; VI: v_sub_f16_e32 v[[NEG_A:[0-9]+]], 0, v{{[0-9]+}}152; VI: v_mac_f16_e32 v{{[0-9]+}}, v[[NEG_A]], v{{[0-9]+}}153; GCN: s_endpgm154define amdgpu_kernel void @mac_f16_neg_a_safe_fp_math(155 ptr addrspace(1) %r,156 ptr addrspace(1) %a,157 ptr addrspace(1) %b,158 ptr addrspace(1) %c) #0 {159entry:160 %a.val = load half, ptr addrspace(1) %a161 %b.val = load half, ptr addrspace(1) %b162 %c.val = load half, ptr addrspace(1) %c163 164 %a.neg = fsub half 0.0, %a.val165 %t.val = fmul half %a.neg, %b.val166 %r.val = fadd half %t.val, %c.val167 168 store half %r.val, ptr addrspace(1) %r169 ret void170}171 172; GCN-LABEL: {{^}}mac_f16_neg_b_safe_fp_math:173; SI: v_sub_f32_e32 v[[NEG_A:[0-9]+]], 0, v{{[0-9]+}}174; SI: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A]]175; VI: v_sub_f16_e32 v[[NEG_A:[0-9]+]], 0, v{{[0-9]+}}176; VI: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A]]177; GCN: s_endpgm178define amdgpu_kernel void @mac_f16_neg_b_safe_fp_math(179 ptr addrspace(1) %r,180 ptr addrspace(1) %a,181 ptr addrspace(1) %b,182 ptr addrspace(1) %c) #0 {183entry:184 %a.val = load half, ptr addrspace(1) %a185 %b.val = load half, ptr addrspace(1) %b186 %c.val = load half, ptr addrspace(1) %c187 188 %b.neg = fsub half 0.0, %b.val189 %t.val = fmul half %a.val, %b.neg190 %r.val = fadd half %t.val, %c.val191 192 store half %r.val, ptr addrspace(1) %r193 ret void194}195 196; GCN-LABEL: {{^}}mac_f16_neg_c_safe_fp_math:197; SI: v_sub_f32_e32 v[[NEG_A:[0-9]+]], 0, v{{[0-9]+}}198; SI: v_mac_f32_e32 v[[NEG_A]], v{{[0-9]+}}, v{{[0-9]+}}199; VI: v_sub_f16_e32 v[[NEG_A:[0-9]+]], 0, v{{[0-9]+}}200; VI: v_mac_f16_e32 v[[NEG_A]], v{{[0-9]+}}, v{{[0-9]+}}201; GCN: s_endpgm202define amdgpu_kernel void @mac_f16_neg_c_safe_fp_math(203 ptr addrspace(1) %r,204 ptr addrspace(1) %a,205 ptr addrspace(1) %b,206 ptr addrspace(1) %c) #0 {207entry:208 %a.val = load half, ptr addrspace(1) %a209 %b.val = load half, ptr addrspace(1) %b210 %c.val = load half, ptr addrspace(1) %c211 212 %c.neg = fsub half 0.0, %c.val213 %t.val = fmul half %a.val, %b.val214 %r.val = fadd half %t.val, %c.neg215 216 store half %r.val, ptr addrspace(1) %r217 ret void218}219 220; GCN-LABEL: {{^}}mac_f16_neg_a_nsz_fp_math:221; SI: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], v{{[0-9]+}}222; SI: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], v{{[0-9]+}}223; SI: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], v{{[0-9]+}}224; SI: v_mad_f32 v{{[0-9]+}}, -[[CVT_A]], [[CVT_B]], [[CVT_C]]225 226; VI-NOT: v_mac_f16227; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]}}228; GCN: s_endpgm229define amdgpu_kernel void @mac_f16_neg_a_nsz_fp_math(230 ptr addrspace(1) %r,231 ptr addrspace(1) %a,232 ptr addrspace(1) %b,233 ptr addrspace(1) %c) #1 {234entry:235 %a.val = load half, ptr addrspace(1) %a236 %b.val = load half, ptr addrspace(1) %b237 %c.val = load half, ptr addrspace(1) %c238 239 %a.neg = fsub nsz half 0.0, %a.val240 %t.val = fmul half %a.neg, %b.val241 %r.val = fadd half %t.val, %c.val242 243 store half %r.val, ptr addrspace(1) %r244 ret void245}246 247; GCN-LABEL: {{^}}mac_f16_neg_b_nsz_fp_math:248; SI: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], v{{[0-9]+}}249; SI: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], v{{[0-9]+}}250; SI: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], v{{[0-9]+}}251; SI: v_mad_f32 v{{[0-9]+}}, -[[CVT_A]], [[CVT_B]], [[CVT_C]]252 253; VI-NOT: v_mac_f16254; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]}}255; GCN: s_endpgm256define amdgpu_kernel void @mac_f16_neg_b_nsz_fp_math(257 ptr addrspace(1) %r,258 ptr addrspace(1) %a,259 ptr addrspace(1) %b,260 ptr addrspace(1) %c) #1 {261entry:262 %a.val = load half, ptr addrspace(1) %a263 %b.val = load half, ptr addrspace(1) %b264 %c.val = load half, ptr addrspace(1) %c265 266 %b.neg = fsub nsz half 0.0, %b.val267 %t.val = fmul half %a.val, %b.neg268 %r.val = fadd half %t.val, %c.val269 270 store half %r.val, ptr addrspace(1) %r271 ret void272}273 274; GCN-LABEL: {{^}}mac_f16_neg_c_nsz_fp_math:275; SI: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], v{{[0-9]+}}276; SI: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], v{{[0-9]+}}277; SI: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], v{{[0-9]+}}278; SI: v_mad_f32 v{{[0-9]+}}, [[CVT_A]], [[CVT_B]], -[[CVT_C]]279 280; VI-NOT: v_mac_f16281; VI: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]}}282; GCN: s_endpgm283define amdgpu_kernel void @mac_f16_neg_c_nsz_fp_math(284 ptr addrspace(1) %r,285 ptr addrspace(1) %a,286 ptr addrspace(1) %b,287 ptr addrspace(1) %c) #1 {288entry:289 %a.val = load half, ptr addrspace(1) %a290 %b.val = load half, ptr addrspace(1) %b291 %c.val = load half, ptr addrspace(1) %c292 293 %c.neg = fsub nsz half 0.0, %c.val294 %t.val = fmul half %a.val, %b.val295 %r.val = fadd half %t.val, %c.neg296 297 store half %r.val, ptr addrspace(1) %r298 ret void299}300 301; GCN-LABEL: {{^}}mac_v2f16:302; GCN: {{buffer|flat}}_load_dword v[[A_V2_F16:[0-9]+]]303; GCN: {{buffer|flat}}_load_dword v[[B_V2_F16:[0-9]+]]304; GCN: {{buffer|flat}}_load_dword v[[C_V2_F16:[0-9]+]]305 306; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]307; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]308; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]309 310; SI-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]311; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]312; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]313 314; SI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]315; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_1:[0-9]+]], v[[C_F16_1]]316; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V2_F16]]317 318; SI-DAG: v_mac_f32_e32 v[[C_F32_0]], v[[A_F32_0]], v[[B_F32_0]]319; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_LO:[0-9]+]], v[[C_F32_0]]320; SI-DAG: v_mac_f32_e32 v[[C_F32_1]], v[[A_F32_1]], v[[B_F32_1]]321; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[C_F32_1]]322; SI: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]323; VI-NOT: and324; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_LO]], v[[R_F16_HI]]325 326; VI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]327; VI-DAG: v_mac_f16_sdwa v[[C_F16_1]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1328; VI-DAG: v_mac_f16_e32 v[[C_V2_F16]], v[[A_V2_F16]], v[[B_V2_F16]]329; VI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[C_F16_1]]330; VI-NOT: and331; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[C_V2_F16]], v[[R_F16_HI]]332 333; GCN: {{buffer|flat}}_store_dword v[[R_V2_F16]]334; GCN: s_endpgm335define amdgpu_kernel void @mac_v2f16(336 ptr addrspace(1) %r,337 ptr addrspace(1) %a,338 ptr addrspace(1) %b,339 ptr addrspace(1) %c) #0 {340entry:341 %a.val = load <2 x half>, ptr addrspace(1) %a342 call void @llvm.amdgcn.s.barrier() #2343 %b.val = load <2 x half>, ptr addrspace(1) %b344 call void @llvm.amdgcn.s.barrier() #2345 %c.val = load <2 x half>, ptr addrspace(1) %c346 347 %t.val = fmul <2 x half> %a.val, %b.val348 %r.val = fadd <2 x half> %t.val, %c.val349 350 store <2 x half> %r.val, ptr addrspace(1) %r351 ret void352}353 354; GCN-LABEL: {{^}}mac_v2f16_same_add:355; SI-DAG: v_mad_f32 v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}356; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}357; SI-DAG: v_mad_f32 v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}358; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}359 360; VI-DAG: v_mac_f16_sdwa v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1361; VI-DAG: v_mad_f16 v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}362; VI-DAG: v_mac_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1363; VI-DAG: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}364 365; GCN: s_endpgm366define amdgpu_kernel void @mac_v2f16_same_add(367 ptr addrspace(1) %r0,368 ptr addrspace(1) %r1,369 ptr addrspace(1) %a,370 ptr addrspace(1) %b,371 ptr addrspace(1) %c,372 ptr addrspace(1) %d,373 ptr addrspace(1) %e) #0 {374entry:375 %a.val = load <2 x half>, ptr addrspace(1) %a376 %b.val = load <2 x half>, ptr addrspace(1) %b377 %c.val = load <2 x half>, ptr addrspace(1) %c378 %d.val = load <2 x half>, ptr addrspace(1) %d379 %e.val = load <2 x half>, ptr addrspace(1) %e380 381 %t0.val = fmul <2 x half> %a.val, %b.val382 %r0.val = fadd <2 x half> %t0.val, %c.val383 384 %t1.val = fmul <2 x half> %d.val, %e.val385 %r1.val = fadd <2 x half> %t1.val, %c.val386 387 store <2 x half> %r0.val, ptr addrspace(1) %r0388 store <2 x half> %r1.val, ptr addrspace(1) %r1389 ret void390}391 392; GCN-LABEL: {{^}}mac_v2f16_neg_a:393; SI: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], {{v[0-9]+}}394; SI: v_cvt_f32_f16_e32 [[CVT1:v[0-9]+]], {{v[0-9]+}}395 396; SI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}397; SI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}398 399; VI-NOT: v_mac_f16400; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}401; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}402; GCN: s_endpgm403define amdgpu_kernel void @mac_v2f16_neg_a(404 ptr addrspace(1) %r,405 ptr addrspace(1) %a,406 ptr addrspace(1) %b,407 ptr addrspace(1) %c) #0 {408entry:409 %a.val = load <2 x half>, ptr addrspace(1) %a410 %b.val = load <2 x half>, ptr addrspace(1) %b411 %c.val = load <2 x half>, ptr addrspace(1) %c412 413 %a.neg = fneg <2 x half> %a.val414 %t.val = fmul <2 x half> %a.neg, %b.val415 %r.val = fadd <2 x half> %t.val, %c.val416 417 store <2 x half> %r.val, ptr addrspace(1) %r418 ret void419}420 421; GCN-LABEL: {{^}}mac_v2f16_neg_b422; SI: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], {{v[0-9]+}}423; SI: v_cvt_f32_f16_e32 [[CVT1:v[0-9]+]], {{v[0-9]+}}424; SI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}425; SI: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}426 427 428; VI-NOT: v_mac_f16429; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}430; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}431; GCN: s_endpgm432define amdgpu_kernel void @mac_v2f16_neg_b(433 ptr addrspace(1) %r,434 ptr addrspace(1) %a,435 ptr addrspace(1) %b,436 ptr addrspace(1) %c) #0 {437entry:438 %a.val = load <2 x half>, ptr addrspace(1) %a439 %b.val = load <2 x half>, ptr addrspace(1) %b440 %c.val = load <2 x half>, ptr addrspace(1) %c441 442 %b.neg = fneg <2 x half> %b.val443 %t.val = fmul <2 x half> %a.val, %b.neg444 %r.val = fadd <2 x half> %t.val, %c.val445 446 store <2 x half> %r.val, ptr addrspace(1) %r447 ret void448}449 450; GCN-LABEL: {{^}}mac_v2f16_neg_c:451; SI: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], {{v[0-9]+}}452; SI: v_cvt_f32_f16_e32 [[CVT1:v[0-9]+]], {{v[0-9]+}}453; SI: v_cvt_f32_f16_e32 [[CVT2:v[0-9]+]], {{v[0-9]+}}454; SI: v_cvt_f32_f16_e32 [[CVT3:v[0-9]+]], {{v[0-9]+}}455; SI: v_cvt_f32_f16_e32 [[CVT4:v[0-9]+]], {{v[0-9]+}}456; SI: v_cvt_f32_f16_e32 [[CVT5:v[0-9]+]], {{v[0-9]+}}457 458; SI-DAG: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}459; SI-DAG: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}460 461; VI-NOT: v_mac_f16462; VI: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}463; VI: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}464; GCN: s_endpgm465define amdgpu_kernel void @mac_v2f16_neg_c(466 ptr addrspace(1) %r,467 ptr addrspace(1) %a,468 ptr addrspace(1) %b,469 ptr addrspace(1) %c) #0 {470entry:471 %a.val = load <2 x half>, ptr addrspace(1) %a472 %b.val = load <2 x half>, ptr addrspace(1) %b473 %c.val = load <2 x half>, ptr addrspace(1) %c474 475 %c.neg = fneg <2 x half> %c.val476 %t.val = fmul <2 x half> %a.val, %b.val477 %r.val = fadd <2 x half> %t.val, %c.neg478 479 store <2 x half> %r.val, ptr addrspace(1) %r480 ret void481}482 483; GCN-LABEL: {{^}}mac_v2f16_neg_a_safe_fp_math:484 485; SI: v_sub_f32_e32 v[[NEG_A0:[0-9]+]], 0, v{{[0-9]+}}486; SI: v_sub_f32_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}}487; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v[[NEG_A0]], v{{[0-9]+}}488; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v[[NEG_A1]], v{{[0-9]+}}489 490; VI-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0491; VI-DAG: v_sub_f16_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}}492; VI-DAG: v_sub_f16_sdwa v[[NEG_A0:[0-9]+]], [[ZERO]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1493; VI-DAG: v_mac_f16_sdwa v{{[0-9]+}}, v[[NEG_A0]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1494; VI-DAG: v_mac_f16_e32 v{{[0-9]+}}, v[[NEG_A1]], v{{[0-9]+}}495 496; GCN: s_endpgm497define amdgpu_kernel void @mac_v2f16_neg_a_safe_fp_math(498 ptr addrspace(1) %r,499 ptr addrspace(1) %a,500 ptr addrspace(1) %b,501 ptr addrspace(1) %c) #0 {502entry:503 %a.val = load <2 x half>, ptr addrspace(1) %a504 %b.val = load <2 x half>, ptr addrspace(1) %b505 %c.val = load <2 x half>, ptr addrspace(1) %c506 507 %a.neg = fsub <2 x half> <half 0.0, half 0.0>, %a.val508 %t.val = fmul <2 x half> %a.neg, %b.val509 %r.val = fadd <2 x half> %t.val, %c.val510 511 store <2 x half> %r.val, ptr addrspace(1) %r512 ret void513}514 515; GCN-LABEL: {{^}}mac_v2f16_neg_b_safe_fp_math:516 517; SI: v_sub_f32_e32 v[[NEG_A0:[0-9]+]], 0, v{{[0-9]+}}518; SI: v_sub_f32_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}}519; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A0]]520; SI-DAG: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A1]]521 522; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0523; VI: v_sub_f16_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}}524; VI: v_sub_f16_sdwa v[[NEG_A0:[0-9]+]], [[ZERO]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1525; VI-DAG: v_mac_f16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD526; VI-DAG: v_mac_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v[[NEG_A1]]527 528; GCN: s_endpgm529define amdgpu_kernel void @mac_v2f16_neg_b_safe_fp_math(530 ptr addrspace(1) %r,531 ptr addrspace(1) %a,532 ptr addrspace(1) %b,533 ptr addrspace(1) %c) #0 {534entry:535 %a.val = load <2 x half>, ptr addrspace(1) %a536 %b.val = load <2 x half>, ptr addrspace(1) %b537 %c.val = load <2 x half>, ptr addrspace(1) %c538 539 %b.neg = fsub <2 x half> <half 0.0, half 0.0>, %b.val540 %t.val = fmul <2 x half> %a.val, %b.neg541 %r.val = fadd <2 x half> %t.val, %c.val542 543 store <2 x half> %r.val, ptr addrspace(1) %r544 ret void545}546 547; GCN-LABEL: {{^}}mac_v2f16_neg_c_safe_fp_math:548 549; SI: v_sub_f32_e32 v[[NEG_A0:[0-9]+]], 0, v{{[0-9]+}}550; SI: v_sub_f32_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}}551; SI-DAG: v_mac_f32_e32 v[[NEG_A0]], v{{[0-9]+}}, v{{[0-9]+}}552; SI-DAG: v_mac_f32_e32 v[[NEG_A1]], v{{[0-9]+}}, v{{[0-9]+}}553 554; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0555; VI: v_sub_f16_e32 v[[NEG_A1:[0-9]+]], 0, v{{[0-9]+}}556; VI: v_sub_f16_sdwa v[[NEG_A0:[0-9]+]], [[ZERO]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1557; VI-DAG: v_mac_f16_sdwa v[[NEG_A0]], v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1558; VI-DAG: v_mac_f16_e32 v[[NEG_A1]], v{{[0-9]+}}, v{{[0-9]+}}559 560; GCN: s_endpgm561define amdgpu_kernel void @mac_v2f16_neg_c_safe_fp_math(562 ptr addrspace(1) %r,563 ptr addrspace(1) %a,564 ptr addrspace(1) %b,565 ptr addrspace(1) %c) #0 {566entry:567 %a.val = load <2 x half>, ptr addrspace(1) %a568 %b.val = load <2 x half>, ptr addrspace(1) %b569 %c.val = load <2 x half>, ptr addrspace(1) %c570 571 %c.neg = fsub <2 x half> <half 0.0, half 0.0>, %c.val572 %t.val = fmul <2 x half> %a.val, %b.val573 %r.val = fadd <2 x half> %t.val, %c.neg574 575 store <2 x half> %r.val, ptr addrspace(1) %r576 ret void577}578 579; GCN-LABEL: {{^}}mac_v2f16_neg_a_nsz_fp_math:580; SI: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], {{v[0-9]+}}581; SI: v_cvt_f32_f16_e32 [[CVT1:v[0-9]+]], {{v[0-9]+}}582; SI: v_cvt_f32_f16_e32 [[CVT2:v[0-9]+]], {{v[0-9]+}}583; SI: v_cvt_f32_f16_e32 [[CVT3:v[0-9]+]], {{v[0-9]+}}584; SI: v_cvt_f32_f16_e32 [[CVT4:v[0-9]+]], {{v[0-9]+}}585; SI: v_cvt_f32_f16_e32 [[CVT5:v[0-9]+]], {{v[0-9]+}}586 587; SI-DAG: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}588; SI-DAG: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}589 590; VI-NOT: v_mac_f16591; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}592; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}593; GCN: s_endpgm594define amdgpu_kernel void @mac_v2f16_neg_a_nsz_fp_math(595 ptr addrspace(1) %r,596 ptr addrspace(1) %a,597 ptr addrspace(1) %b,598 ptr addrspace(1) %c) #1 {599entry:600 %a.val = load <2 x half>, ptr addrspace(1) %a601 %b.val = load <2 x half>, ptr addrspace(1) %b602 %c.val = load <2 x half>, ptr addrspace(1) %c603 604 %a.neg = fsub nsz <2 x half> <half 0.0, half 0.0>, %a.val605 %t.val = fmul <2 x half> %a.neg, %b.val606 %r.val = fadd <2 x half> %t.val, %c.val607 608 store <2 x half> %r.val, ptr addrspace(1) %r609 ret void610}611 612; GCN-LABEL: {{^}}mac_v2f16_neg_b_nsz_fp_math:613; SI: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], {{v[0-9]+}}614; SI: v_cvt_f32_f16_e32 [[CVT1:v[0-9]+]], {{v[0-9]+}}615; SI: v_cvt_f32_f16_e32 [[CVT2:v[0-9]+]], {{v[0-9]+}}616; SI: v_cvt_f32_f16_e32 [[CVT3:v[0-9]+]], {{v[0-9]+}}617; SI: v_cvt_f32_f16_e32 [[CVT4:v[0-9]+]], {{v[0-9]+}}618; SI: v_cvt_f32_f16_e32 [[CVT5:v[0-9]+]], {{v[0-9]+}}619 620; SI-DAG: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}621; SI-DAG: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}622 623; VI-NOT: v_mac_f16624; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}625; VI: v_mad_f16 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}}626; GCN: s_endpgm627define amdgpu_kernel void @mac_v2f16_neg_b_nsz_fp_math(628 ptr addrspace(1) %r,629 ptr addrspace(1) %a,630 ptr addrspace(1) %b,631 ptr addrspace(1) %c) #1 {632entry:633 %a.val = load <2 x half>, ptr addrspace(1) %a634 %b.val = load <2 x half>, ptr addrspace(1) %b635 %c.val = load <2 x half>, ptr addrspace(1) %c636 637 %b.neg = fsub nsz <2 x half> <half 0.0, half 0.0>, %b.val638 %t.val = fmul <2 x half> %a.val, %b.neg639 %r.val = fadd <2 x half> %t.val, %c.val640 641 store <2 x half> %r.val, ptr addrspace(1) %r642 ret void643}644 645; GCN-LABEL: {{^}}mac_v2f16_neg_c_nsz_fp_math:646; SI: v_cvt_f32_f16_e32 [[CVT0:v[0-9]+]], {{v[0-9]+}}647; SI: v_cvt_f32_f16_e32 [[CVT1:v[0-9]+]], {{v[0-9]+}}648; SI: v_cvt_f32_f16_e32 [[CVT2:v[0-9]+]], {{v[0-9]+}}649; SI: v_cvt_f32_f16_e32 [[CVT3:v[0-9]+]], {{v[0-9]+}}650; SI: v_cvt_f32_f16_e32 [[CVT4:v[0-9]+]], {{v[0-9]+}}651; SI: v_cvt_f32_f16_e32 [[CVT5:v[0-9]+]], {{v[0-9]+}}652 653; SI-DAG: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}654; SI-DAG: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[0-9]+}}655 656; VI-NOT: v_mac_f16657; VI: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[-0-9]}}658; VI: v_mad_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, -v{{[-0-9]}}659; GCN: s_endpgm660define amdgpu_kernel void @mac_v2f16_neg_c_nsz_fp_math(661 ptr addrspace(1) %r,662 ptr addrspace(1) %a,663 ptr addrspace(1) %b,664 ptr addrspace(1) %c) #1 {665entry:666 %a.val = load <2 x half>, ptr addrspace(1) %a667 %b.val = load <2 x half>, ptr addrspace(1) %b668 %c.val = load <2 x half>, ptr addrspace(1) %c669 670 %c.neg = fsub nsz <2 x half> <half 0.0, half 0.0>, %c.val671 %t.val = fmul <2 x half> %a.val, %b.val672 %r.val = fadd <2 x half> %t.val, %c.neg673 674 store <2 x half> %r.val, ptr addrspace(1) %r675 ret void676}677 678declare void @llvm.amdgcn.s.barrier() #2679 680attributes #0 = { nounwind "no-signed-zeros-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" }681attributes #1 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }682attributes #2 = { nounwind convergent }683